Sorting Architecture Research Articles

Wireless sensor network-based machine learning framework for smart cities in intelligent waste management

Environmental safety is one of the key issues that are directly related to a country's prosperity. One of the most fundamental aspects of a sustainable economy is waste management and recycling. Better recycling safety and efficiency may be achieved via the use of intelligent devices rather than manual effort. In this research, we describe a machine learning-based architecture for smart trash collection and sorting using the Internet of Things and wireless sensor networks. The goal of this study was to develop an autonomous method for producing an efficient and intelligent waste parameter monitoring system for a novel waste management system, using the Internet of Things (IoT) and Long Range (LoRa) technologies. Several possibilities are explored, all of which may be applied to the development of the three nodes. The number of trash cans, garbage stench, air quality, weight, smoke levels, and waste categories are all tracked in real-time via the Internet of Things and the Thing Speak Cloud Platform, which can be set up in numerous places. In the end, a fog layer-deployed intelligent waste classification framework consists mostly of four layers: input, feature, classification, and output. Using the Thrash Box dataset, the proposed system develops a categorization method into trash classes such as household, medical, and electronic garbage, in addition to object identification. Traditional machine learning methods, such as the multi-kernel support vector machine (SVM) and the Adaboost ensemble classifier, are employed in the classification layer, while the Resnet-101 deep convolutional neural network model is used in the feature layer. Experiments were conducted to evaluate the suggested method's ability to classify garbage and provide accurate predictions about their respective categories. Compared to other state-of-the-art models, the suggested method's performance was shown to be superior in the presented trials.

K-Degree Parallel Comparison-Free Hardware Sorter for Complete Sorting

This paper presents a novel parallel comparison-free hardware sorting architecture that sorts N, n-bit elements consuming linear worst case sorting latency of O(N) clock-cycles utilizing k-parallel clusters. A parallel cluster contains a number of identical blocks utilizing a few fundamental logic components. The architecture achieves a speed-up of nnk+k over non-parallel architectures. The proposed sorting architecture identifies the largest element in every cycle with smaller clock periods compared to state-of-the-art comparison-free approaches and does not require any kind of pre-processing of the input data set, unlike most of the existing hardware sorters. The experimental result shows the degree of parallelism (k) for 16-bit, 32-bit, and 64-bit elements are respectively {4}, {4, 5, 6, 7, 8} and {8} to achieve maximum system throughput. This sorter achieves a throughput of ≈194 Million-Elements-per-second (MEps) for k=6 and, it is ≈142 MEps for k=8 to sort 256 elements of 32-bit and 64-bit, respectively, whereas it is ≈159 MEps for k=6 to sort 512 elements of 40-bit.

Hardware Support for Efficient and Low-Power Data Sorting in Massive Data Application: The 3-D Sorting Method

Sorting is an inseparable part of applications that process massive amounts of data. A hardware-designed sorter increases the performance at the cost of increasing the required resources, the issue that is limited in the field-programmable gate array (FPGA) chips. This article proposes a new ultralow-power three-dimensional hardware sorting architecture, the so-called ULP-Sorter, based on multidimensional sorting algorithm. The hardware resources and power consumption are significantly decreased in the ULP-Sorter architecture in comparison with previous state-of-the-art techniques. The simulation results show that ULP-Sorter reduces number of look-up tables and registers by 70% and 35.7%, respectively, in comparison to previous state-of-the-art techniques. ULP-Sorter reduces the FPGAs power consumption on average by 48.7% in comparison with previous state-of-the-art techniques. The results indicate that ULP-Sorter is a suitable architecture for edge computing devices with limited power and area constrains.

Interleaved Local Sorting for Successive Cancellation List Decoding of Polar Codes

In the successive cancellation list decoding of polar codes, the metric sorting dominates the overall decoding latency. To reduce the latency of metric sorting, this paper proposes a new sorting method, called interleaved local sorting, which divides the metrics to be sorted into several groups and locally sorts each group independently. In addition, an interleaving scheme is proposed to recover the performance degradation caused by the local sorting. A hardware architecture effective in reducing the overall latency as well as the hardware complexity is also proposed based on the proposed metric sorting. The evaluation results show that the proposed interleaved local sorting architecture outperforms the state-of-the-art metric sorting architectures in terms of latency and hardware complexity when the list size is not small.

A Two-Directional BigData Sorting Architecture on FPGAs

Sorting is pivotal data analytics and becomes challenging with intensive computation on drastically growing data volume. Sorting on FPGA has shown superior throughput, but the limited in-system memory causes vast data transferring to/from external storage when handling a large dataset. We propose a two-directional sorting (2DSort) architecture which sorts data sequences on both horizontal and vertical directions. 2DSort significantly reduces the costly data transmission by tracking the data on FPGA and writes back the data to external storage when the final sorting position is determined. 2DSort shows average 38.5 percent runtime enhancement in comparison to state-of-the-art bigdata sorting engine on FPGA.

Hardware Dynamic Memory Manager for Hard Real-Time Systems

This paper presents novel hardware architecture of dynamic memory manager providing memory allocation and deallocation operations that are suitable for hard real-time and safety-critical systems due to very high determinism of these operations. The proposed memory manager implements Worst-Fit algorithm for selection of suitable free block of memory that can be used by the external environment, e.g. CPU. The deterministic timing of the memory allocation and deallocation operations is essential for hard real-time systems. The proposed memory manager performs these operations in nearly constant time thanks to the adoption of hardware-accelerated max queue, which is a data structure that continuously provides the largest free block of memory in two clock cycles regardless of actual number or constellation of existing free blocks of memory. In order to minimize the overhead caused by implementing the memory management in hardware, the max queue was optimized by developing a new sorting architecture, called Rocket-Queue. The Rocket-Queue architecture as well as the whole memory manager is described in this paper in detail. The memory manager and the Rocket-Queue architecture were verified using simplified version of UVM and applying billions of randomly generated instructions as testing inputs. The Rocket-Queue architecture was synthesized into Intel FPGA Cyclone V with 100 MHz clock frequency and the results show that it consumes from 17,06% to 38,67% less LUTs than the existing architecture, called Systolic Array. The memory manager implemented in a form of a coprocessor that provides four custom instructions was synthesized into 28nm TSMC HPM technology with 1 GHz clock frequency and 0.9V power supply. The ASIC synthesis results show that the Rocket-Queue based memory manager can occupy up to 24,59% smaller chip area than the Systolic Array based manager. In terms of total power consumption, the Rocket-Queue based memory manager consumes from 15,16% to 42,95% less power.

A Hybrid Pipelined Architecture for High Performance Top-K Sorting on FPGA

We present a hybrid pipelined sorting architecture capable of finding and producing as its output the K largest elements from an input sequence. The architecture consists of a bitonic sorter and L cascaded sorting units. The sorting unit is designed to output P elements during every cycle with the aim of increasing the throughput and lowering the latency. The function of the bitonic sorter is to generate a segmented ordered sequence. The sorting unit processes this sequence to identify and output the P largest elements. Hence, the K=PL largest elements are obtained after the segmented ordered sequence proceeds through L cascaded sorting units. Variable-length and continuous sequences are supported by the proposed sorting architecture. The results of the implementation show that the sorting architecture can achieve a throughput of 22.88 GB/s with P=16 on a state-of-the-art Field Programmable Gate Array (FPGA).

RTHS: A Low-Cost High-Performance Real-Time Hardware Sorter, Using a Multidimensional Sorting Algorithm

This paper proposes a novel hardware-based multidimensional sorting algorithm and its respective architecture, called real-time hardware sorter (RTHS), for emerging data intensive processing applications where performance and resource conservation are serious concerns. The basic idea behind RTHS is to reduce the hardware complexity of parallel hardware sorting architectures (PHSAs) through a high-performance scalable matrix-based sorting method. The proposed method can also be used for implementing Min/Max queues or finding the largest/smallest records exclusively in the big data application. Implementing the RTHS design on a Virtex-7 field-programmable gate array (FPGA) reveals that the number of lookup tables (LUTs) of the proposed method has decreased by 66.3% and 87.3% compared to the conventional Bitonic sorting network (CBSN) and the state-of-the-art PHSA, respectively. In addition, the number of required registers for the proposed method has decreased by 94.8% compared to the state-of-the-art PHSA.

A hybrid CPU/GPU approach for optimizing sorting throughput

The GPU is an effective architecture for sorting due to its massive parallelism and high memory bandwidth. However, for input datasets that exceed global memory capacity, the communication overhead between host (CPU) and GPU may degrade the overall performance of heterogeneous approaches. Thus, to achieve performance gains over multi-core parallel CPU algorithms, heterogeneous sorting using the GPU needs to obviate communication overheads. We provide a detailed overview of current host-GPU data transfer mechanisms and advance several methods of mitigating the associated performance bottlenecks. Using these methods, we develop a heterogeneous CPU/GPU sorting algorithm that effectively exploits the architecture. Furthermore, we demonstrate that, while out-of-place GPU sorting achieves the best performance, an in-place sort has the potential to further reduce some host-side bottlenecks, which encourages several future research priorities. Our approaches mitigate several bottlenecks, as demonstrated on single- and dual-GPU platforms, achieving speedups up to 3.47× over the parallel reference implementation on the CPU. We discuss future research for heterogeneous sorting in the multi-GPU NVLink era.

Hybrid Sorting Architecture for Low-latency Successive Cancellation List Decoding of Polar Codes

This paper presents a new sorting architecture for low-latency successive cancellation list decoding (SCLD) of polar codes. By investigating the dataflow of SCLD, it is discovered that the metric sorting and the metric computation, which have been performed in a serial manner, can be parallelized if the metric sorter is decomposable into two subcomponents. To exploit such a property, a low-complexity sorting architecture adequate for the decomposition is developed by hybridizing bitonic and odd-even sorts. The proposed architecture not only diminishes the latency of SCLD significantly, but also attains the hardware complexity as low as that of the state-of-the-art work.

Reliable real-time task scheduler based on Rocket Queue architecture

This paper presents the design of an improved task scheduler for real-time and safety-critical systems, where it is important to deal with real-time requirements and reliability requirements simultaneously. The proposed scheduler implements EDF algorithm for the optimal scheduling of hard real-time tasks, which is essential for real-time operating systems. The proposed task scheduler allows removing any task from the queue according to task ID and regardless of the actual position of the task within the queue, which is important for flexibility of the scheduler for its future extensions. Both operations of the scheduler, i.e. task adding and task killing take always constant time (two clock cycles) to execute regardless of the actual or the maximum number of tasks within the scheduler. The scheduler was verified using simplified version of UVM and applying millions of instructions with randomly generated sort values. The scheduler, implemented in a form of a coprocessor, was synthesized into Intel FPGA Cyclone V with 100MHz clock frequency. There are two improvements proposed that can significantly reduce resource costs of the scheduler, which is achieved by replacing static deadlines with dynamic deadlines and using a new Rocket Queue architecture for sorting of the tasks according to their deadline values. When both improvements are applied simultaneously, the total ALM cost savings are in the range from 42,59% to 60,18% and the total amount of registers is reduced by 73,74% to 74,87%, depending on the scheduler capacity. The spared resources are then used for implementation of two different variations of TMR in order to increase fault tolerance of the scheduler. The resource cost reductions achieved also indirectly increase the reliability of such scheduler because of reduced probability that a fault occurs.

Efficient Sorting Architecture for List-Fast-SSC Decoding of Polar Codes

Polar codes have been proven to achieve the symmetric capacity of memoryless channel. Compared with a successive cancellation list decoder, list-Fast simplified-successive cancellation generates more candidate paths, which leads to more resource costs and higher decoding latency. To remedy this drawback, we present a simplified sorting architecture. An $M*L$ ordered candidate path matrix is constructed by preliminary sorter, where $M$ and $L$ denote the number of candidate path expanded by one constituent code and the list size of the decoder, respectively. Then, we eliminate the candidate paths that are definitely not in the $L$ best paths by the proposed lossless pruning algorithm. Finally, a compatible sorting network combining the advantages of bitonic sorter and odd–even sorter is proposed. Numerical results show that for $L=32$ and $M=8$ , the proposed architecture can reduce 66.7% of candidate paths and save 52.3% of compare and swap units (CASUs) and 25% of CASU stages compared with the odd–even sorter.

Computer Generation of High Throughput and Memory Efficient Sorting Designs on FPGA

Accelerating sorting using dedicated hardware to fully utilize the memory bandwidth for Big Data applications has gained much interest in the research community. Recently, parallel sorting networks have been widely employed in hardware implementations due to their high data parallelism and low control overhead. In this paper, we propose a systematic methodology for mapping large-scale bitonic sorting networks onto FPGA. To realize data permutations in the sorting network, we develop a novel RAM-based design by vertically “folding” the classic Clos network. By utilizing the proposed design for data permutation, we develop a hardware generator to automatically build bitonic sorting architectures on FPGAs. For given input size, data width and data parallelism, the hardware generator specializes both the datapath and the control unit for sorting and generates a design in high level hardware description language. We demonstrate trade-offs among throughput, latency and area using two illustrative sorting designs including a high throughput design and a resource efficient design. With a data parallelism of p (2 ≤ p ≤ N/2), the high throughput design sorts an N-key sequence with latency 6N=p + o(N), throughputp results per cycle and uses 6N + o(N) memory. This achieves optimal memory efficiency (defined as the ratio of throughput to the amount of on-chip memory used by the design) and outperforms the state-of-the-art. Experimental results show that the designs obtained by our proposed hardware generator achieve 49 to 112 percent improvement in energy efficiency and 56 to 430 percent higher memory efficiency compared with the state-of-the-art.

Improved Sorting Architecture for ${K}$ -Best MIMO Detection

This brief presents an improved sorting architecture for ${K}$ -best multiple-input multiple-output (MIMO) detection. In the proposed architecture, two properties of the ${K}$ -best MIMO detection are exploited for simplifications: the order among siblings from the same parent node can be easily identified; the order among the ${K}$ -best nodes is dispensable. Besides, the generalized mergesort-based architecture for the ${K}$ -best sorting is presented so that the proposed sorter can be constructed for any power-of-two ${K}$ and modulation scheme. Compared to the conventional ones, the proposed architecture lowers not only the hardware complexity but also the latency significantly.

Modular Serial Pipelined Sorting Architecture for Continuous Variable-Length Sequences with a Very Simple Control Strategy

Modular Serial Pipelined Sorting Architecture for Continuous Variable-Length Sequences with a Very Simple Control Strategy

A Low Cost VLSI Architecture for Spike Sorting Based on Feature Extraction with Peak Search.

The goal of this paper is to present a novel VLSI architecture for spike sorting with high classification accuracy, low area costs and low power consumption. A novel feature extraction algorithm with low computational complexities is proposed for the design of the architecture. In the feature extraction algorithm, a spike is separated into two portions based on its peak value. The area of each portion is then used as a feature. The algorithm is simple to implement and less susceptible to noise interference. Based on the algorithm, a novel architecture capable of identifying peak values and computing spike areas concurrently is proposed. To further accelerate the computation, a spike can be divided into a number of segments for the local feature computation. The local features are subsequently merged with the global ones by a simple hardware circuit. The architecture can also be easily operated in conjunction with the circuits for commonly-used spike detection algorithms, such as the Non-linear Energy Operator (NEO). The architecture has been implemented by an Application-Specific Integrated Circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture is well suited for real-time multi-channel spike detection and feature extraction requiring low hardware area costs, low power consumption and high classification accuracy.

Efficient Sorting Architecture for Successive-Cancellation-List Decoding of Polar Codes

This brief presents an efficient sorting architecture for successive-cancellation-list decoding of polar codes. In order to avoid performing redundant sorting operations on the metrics that are already sorted in the previous step of decoding, the proposed architecture separately processes the sorted metrics and unsorted ones. In addition, the odd–even sort network is adopted as a basic building block to further reduce the hardware complexity while sustaining low latencies for various list sizes. On average, the proposed architecture requires less than 50% of the compare-and-swap units demanded by the area-efficient sorting networks in the literature.

An Efficient VLSI Architecture for Multi-Channel Spike Sorting Using a Generalized Hebbian Algorithm.

A novel VLSI architecture for multi-channel online spike sorting is presented in this paper. In the architecture, the spike detection is based on nonlinear energy operator (NEO), and the feature extraction is carried out by the generalized Hebbian algorithm (GHA). To lower the power consumption and area costs of the circuits, all of the channels share the same core for spike detection and feature extraction operations. Each channel has dedicated buffers for storing the detected spikes and the principal components of that channel. The proposed circuit also contains a clock gating system supplying the clock to only the buffers of channels currently using the computation core to further reduce the power consumption. The architecture has been implemented by an application-specific integrated circuit (ASIC) with 90-nm technology. Comparisons to the existing works show that the proposed architecture has lower power consumption and hardware area costs for real-time multi-channel spike detection and feature extraction.

FPGA Based Packet Classification Using Multi-Pipeline Architecture

This paper proposes a decision-tree-based linear multi-pipeline architecture on FPGA’s for packet sorting. We reflect on the next-generation packet classification problems where more than 5-tuple packet header fields has been classified. From traditional fixed 5-tuple matching, Multi-field packet classification has been evolved for flexible matching with arbitrary combination of numerous packet header fields. The recently proposed Open Flow switching requires classifying each packet using up to 12-tuple packet header fields. It become a great task to develop scalable solutions for next-generation packet classification that support larger rule sets, additional packet header fields and higher throughput. This paper proposes a 2-D multi-pipeline decision-tree-based architecture for next-generation packet classification which exploits the abundant parallelism and other desirable features such as current field-programmable gate arrays (FPGAs),. We propose several optimization techniques for the state-of-the-art decision-tree-based algorithm by examine the various traditional 5-tuple packet classification methods. By using set of 12-tuple rules, the framework has been developed to partition the rule set into multiple subsets each of which is built into an optimized decision tree. To maximize the memory utilization. a tree-to-pipeline mapping scheme is carefully designed while underneath high throughput. Our proposed architecture can store up to 1K synthetic 12-tuple rules or 10K real-life 5-tuple rules in on-chip memory of a single up to date FPGA, and maintain 80 or 40 Gbps throughput for least packets of size (40 bytes) respectively. To utilize the memory properly and to sustaining high throughput, a mapping scheme based on tree-to-pipeline is designed carefully. This paper deal with the profuse parallelism and other preferred features provided by present field-programmable gate arrays and propose a 2-D multi-pipeline decision tree based architecture for next-generation packet sorting. The Verilog Hardware description languages (VHDL) are used to design the proposed architecture and synthesized using Xilinx Software.

Efficient Architecture for Spike Sorting in Reconfigurable Hardware

This paper presents a novel hardware architecture for fast spike sorting. The architecture is able to perform both the feature extraction and clustering in hardware. The generalized Hebbian algorithm (GHA) and fuzzy C-means (FCM) algorithm are used for feature extraction and clustering, respectively. The employment of GHA allows efficient computation of principal components for subsequent clustering operations. The FCM is able to achieve near optimal clustering for spike sorting. Its performance is insensitive to the selection of initial cluster centers. The hardware implementations of GHA and FCM feature low area costs and high throughput. In the GHA architecture, the computation of different weight vectors share the same circuit for lowering the area costs. Moreover, in the FCM hardware implementation, the usual iterative operations for updating the membership matrix and cluster centroid are merged into one single updating process to evade the large storage requirement. To show the effectiveness of the circuit, the proposed architecture is physically implemented by field programmable gate array (FPGA). It is embedded in a System-on-Chip (SOC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient spike sorting design for attaining high classification correct rate and high speed computation.