Solid Diffusion Source Research Articles

Phosphorus emitter profile control for silicon solar cell using the doss diffusion technique

The Doped Oxide Solid Source (DOSS) diffusion technique is well suited for fine-tuning of the surface concentration. The dopant surface concentration is important during phosphorus emitter diffusion due to the opposite requirements of a lowly doped emitter for good blue response and a sufficiently high surface concentration for a good ohmic contact. The sources are made in the laboratory using the standard POCl3 diffusion technique. DOSS Diffusions were carried out in the temperature range 850-1050°C using sources with different doping levels obtained by varying the POCl3 partial pressure from 0.004 % to 4.28 %. The electrical profiles were measured using the Stripping Hall profiling technique. Phosphorus diffusion profiles with the complete elimination of the dead layer have been obtained over a large range of source concentrations for all investigated diffusion temperatures. The residual diffusion oxide thickness increased with both temperature and source doping level within the range 7.5-30 nm. XPS profiling indicated that the composition of the residual glass was a mixture of P2O5 and SiO2.

Enhancement mode AlGaN/GaN HEMTs by fluorine ion thermal diffusion with high Vth stability

A method of fluorine ion thermal diffusion has been proposed to realize enhancement-mode AlGaN/GaN HEMTs. By AlF3 solid diffusion source, fluorine ion has successfully diffused in the gate region of AlGaN layer at 800 °C 2 h with a diffusion depth about 20 nm demonstrated by secondary ion mass spectrometry. The fabricated device exhibits a positive threshold voltage of 1.8 V, a drain current density of 95 mA mm−1 at Vg = 4 V, a peak transconductance of 50 mS mm−1, a breakdown voltage of 700 V. Besides, the device is also demonstrated with good Vth stability under different stress conditions.

POROUS SILICON FABRICATION PROCESS FOR OPTICAL REFLECTORS

We describe the use of porous silicon fabrication technique for fabricating non-manhattan structures in silicon using wet etching. The fabrication method is simple to set up, economical and produces smooth etched surface. A solid source diffusion of N++ in a P type wafer with low stress thermally grown silicon nitride is used as a masking layer. Comparison of porous silicon etches with wafers solid source diffusion and implanted diffusion is presented. The result show that areas where a solid source diffusion is used form an etch angle of 70-80°, however using an implanted diffusion the etch angle is closer to 90°. The selectivity of the etch during porous silicon fabrication using any of the above two as masking layer results in fabrication of high aspect ratio non-manhattan structures. These structures since are wet etched do not have surface roughness and can be used for optical applications.

Fabrication and Modeling of High-Efficiency Front Junction N-Type Silicon Solar Cells With Tunnel Oxide Passivating Back Contact

This paper reports on in-depth understanding, modeling, and fabrication of 23.8% efficient 4 cm2 n-type Float Zone (FZ) silicon cells with a selective boron emitter and photolithography contact on front and tunnel oxide passivating contact on the back. Tunnel oxide passivating contact composed of a very thin chemically grown silicon oxide (∼15 A) capped with plasma-enhanced chemical vapor deposition (PECVD) grown 20 nm n+ poly Si gave excellent surface passivation and carrier selectivity with very low saturation current density (∼5 fA/cm2). A high-quality boron selective emitter was formed using ion implantation and solid source diffusion to minimize metal recombination and emitter saturation current density. Process optimization resulted in a cell $V_{{\rm{oc}}}$ of 712 mV, $J_{{\rm{sc}}}$ of 41.2 mA/cm2, and FF of 0.811. A simple methodology is used to model these cells which replaces tunnel oxide passivating contact region by electron and hole recombination velocities extracted from measured saturation current density of tunnel oxide passivating contact region and analysis. Using this approach and two-dimensional device modeling gave an excellent match between the measured and simulated cell parameters and efficiency, supporting excellent passivation and carrier selectivity of these contacts. Extended simulations showed that 26% cell efficiency can be achieved with this cell structure by further optimization of wafer quality, emitter profile, and contact design.

An experimental study of solid source diffusion by spin on dopants and its application for minimal silicon-on-insulator CMOS fabrication

Solid source diffusions of phosphorus (P) and boron (B) into the half-inch (12.5 mm) minimal silicon (Si) wafers by spin on dopants (SOD) have been systematically investigated and the physical-vapor-deposited (PVD) titanium nitride (TiN) metal gate minimal silicon-on-insulator (SOI) complementary metal–oxide–semiconductor (CMOS) field-effect transistors (FETs) have successfully been fabricated using the developed SOD thermal diffusion technique. It was experimentally confirmed that a low temperature oxidation (LTO) process which depresses a boron silicide layer formation is effective way to remove boron-glass in a diluted hydrofluoric acid (DHF) solution. It was also found that top Si layer thickness of SOI wafers is reduced in the SOD thermal diffusion process because of its consumption by thermal oxidation owing to the oxygen atoms included in SOD films, which should be carefully considered in the ultrathin SOI device fabrication. Moreover, normal operations of the fabricated minimal PVD-TiN metal gate SOI-CMOS inverters, static random access memory (SRAM) cells and ring oscillators have been demonstrated. These circuit level results indicate that no remarkable particles and interface traps were introduced onto the minimal wafers during the device fabrication, and the developed solid source diffusion by SOD is useful for the fabrication of functional logic gate minimal SOI-CMOS integrated circuits.

Codiffusion Sources and Barriers for the Assembly of Back-Contact Back-Junction Solar Cells

In this study, several diffusion sources are investigated, aiming at codiffusion for the fabrication of back-contact back-junction (BC-BJ) silicon solar cell. As a gaseous diffusion source, a POCl3-diffusion process is investigated, and for solid diffusion sources, phosphorus- and boron-doped silicate glass (PSG and BSG) deposited by the means of plasma-enhanced chemical vapor deposition are considered. The n+-doped areas diffused from a solid PSG layer allow for a precise adjustment of the sheet resistance $(R_{{\rm sh}})$ in the range of 40–400 Ω/sq, along with a dark saturation current density $(J_{o})$ of 55 fA/cm $^{2}$ . Subsequently, boron diffusion from solid BSG layer leads to p+-doped areas with high doping levels ( $R_{\rm sh}=$ 50 Ω/sq). However, gaseous POCl3 diffusion in combination with solid boron diffusion from the BSG layer can only be successfully performed if the BSG layer is protected with an SiO x layer. Furthermore, by adjusting the gas flows during POCl3 diffusion, n+-doped areas with $R_{{\rm sh}}$ in the range of 150– 300 Ω/sq are achieved. The corresponding surfaces feature $J_{o}$ values of 30 fA/cm $^{2}$ . The result of this study is a flexible codiffusion setup allowing for the efficient integration in advanced process chains of BC-BJ solar cells which results in the cell efficiencies well above above $\eta =$ 20%.

Thin PSG Process for 4H-SiC MOSFET

The use of phosphorous as a passivating agent for the SiO2/4H-SiC interface increases the field effect channel mobility of 4H-SiC MOSFET to twice the value, 30-40cm2/V-s, that is obtained with a high temperature anneal in nitric oxide (NO). A solid SiP2O7 planar diffusion source is used to produce P2O5 for the passivation of the interface. Incorporation of phosphorous into SiO2 leads to formation of phosphosilicate glass (PSG) which is known to be a polar material causes device instability. With a new modified thin phosphorous (P) passivation process, as described in this abstract, we can improve the stability of MOSFETs significantly with mobility around 75cm2/V.s.

Co-Diffused Back-Contact Back-Junction Silicon Solar Cells without Gap Regions

In this paper, first generation back-contact back-junction (BC-BJ) silicon solar cells with cell efficiencies well above η = 20% were fabricated. The process sequence is industrially feasible, requires only one high-temperature step (codiffusion), and relies only on industrially available pattering technologies. The silicon-doping is performed from pre-patterned solid diffusion sources, which allow for the precise adjustment of phosphorusand boron-doping levels. Based on the investigated process technologies, BC-BJ solar cells with gap and without gap between adjacent n+ - and p+ -doped areas were processed. On the one hand, a strong reduction of the process effort is possible by omitting the gap regions. On the other hand, parasitic tunneling currents through the narrow space charge region may occur. Hence, deep doped areas were realized to avoid tunneling currents in gap-free BC-BJ cells. This paper finishes with a detailed characterization of the manufactured cells including important cell measurements like I-V, SunsVOC, quantum efficiency, and an analysis of the cell specific fill factor losses.

ChemInform Abstract: Phosphorus Doping of Silicon Using a Solid Planar Diffusion Source at Reduced Pressures.

A silicon pyrophosphate-containing (SiP 2 O 7 ) solid planar diffusion source has been evaluated for phosphorus doping of silicon at reduced pressures. A reduction in pressure generally results in improvements in the uniformity of doping. At the edges of 3 in. silicon wafers diffused at 1000°C, maximum deviations in sheet resistance are reduced from approximately 15 to approximately 5%, if total pressure is reduced from 1 atm to 5 torr. This improvement is even more significant for diffusion at 900°C, where the maximum deviation is reduced from approximately 100% to approximately 10% by the same reduction in total pressure

Numerical modeling of large-scale solid-source diffusion experiments in Callovo-Oxfordian clay

Diffusion and retention parameters of clays are commonly derived from in situ diffusion experiments which are performed by injecting dissolved tracers in packed sections of boreholes drilled in clay formations. Interpretation of these experiments is prone to uncertainties caused by the filter, the gap and the drilling-disturbed zone. The large-scale solid-source diffusion experiment (SSDE) overcomes the uncertainties of in situ diffusion experiments because tracers are emplaced in a clay plug at the center of a cylindrical clay block (30 cm high and 30 cm in diameter). Sampling of the clay block along vertical boreholes at the end of the experiment provides a 3-D tracer distribution from which the effective diffusion, D e, and K d are estimated. Numerical models of SSDE performed in samples of Callovo-Oxfordian clay with HTO and 85Sr 2+ are presented here. Experiments are modelled with 2-D axi-symmetric finite element grids because clay bedding is parallel to the bases of the blocks. The model takes into account diffusion anisotropy and is solved with CORE 2DV4. Relevant diffusion and retention parameters are identified by sensitivity analyses. Parameters are estimated by solving the inverse problem. Uncertainties in parameters of the clay plug do not affect the estimation of clay parameters because tracer activities are not sensitive to clay plug parameters. Tritium data show axial symmetry with mild fluctuations and allow the accurate estimation of horizontal D e which ranges from 4.04 × 10 −11 to 4.51 × 10 −11 m 2/s. Vertical D e is smaller than horizontal D e by a factor (anisotropy ratio) which ranges from 1.79 to 3.8. 85Sr 2+ data show a large scatter and provide only crude estimates of K d and horizontal D e.

N -type emitter surface passivation in c-Si solar cells by means of antireflective amorphous silicon carbide layers

Emitter saturation current densities (JOe) of phosphorus-diffused planar c-Si solar cell emitters passivated by silicon carbide (SiCx) layers have been determined in a wide sheet resistance range (20–500Ω∕sq). Phosphorus diffusions were performed using solid planar diffusion sources without employing any drive-in step. Stacks of two SiCx layers were deposited by plasma enhanced chemical vapor deposition: first a thin silicon rich layer with excellent passivating properties and then an antireflective carbon rich layer. The thickness of the passivating layer was optimized, reaching a trade-off between the better passivation achieved for thicker layers and the increased light absorption within the layer, which reduced the photocurrent. The surface recombination velocity and the optical losses were determined for each configuration and used to calculate photovoltaic conversion efficiency limits for 50 and 90Ω∕sq emitters. In both cases, optimum configuration is for the stacks with passivating layers that are about 8nm thick.

The vertical replacement-gate (VRG) MOSFET

We have fabricated and demonstrated a new device called the vertical replacement-gate (VRG) MOSFET. This is the first MOSFET ever built in which: (1) all critical transistor dimensions are controlled precisely without lithography and dry etch, (2) the gate length is defined by a deposited film thickness, independently of lithography and etch, and (3) a high-quality gate oxide is grown on a single-crystal Si channel. In addition to this unique combination, the VRG-MOSFET includes self-aligned source/drain extensions (SDEs) formed by solid source diffusion (SSD), small parasitic overlap, junction, and source/drain capacitances, and a replacement-gate approach to enable alternative gate stacks. We have demonstrated nMOSFETs with an initial VRG process, and pMOSFETs with a more mature process. Since both sides of the device pillar drive in parallel, the drive current per μm of coded width can far exceed that of advanced planar MOSFETs. Our 100 nm VRG-pMOSFETs with t OX=25 Å drive 615 μA/μm at 1.5 V with I OFF=8 nA/μm—80% more drive than specified in the 1999 ITRS Roadmap at the same I OFF. Our 50 nm VRG-pMOSFETs with t OX=25 Å approach the 1.0 V roadmap target of I ON=350 μA/μm at I OFF=20 nA/μm without the need for a hyperthin (<20 Å) gate oxide. We have described a process for integrating n-channel and p-channel VRG-MOSFETs to form side-by-side CMOS that retains the key VRG advantages while providing packing density and process complexity that is competitive with traditional planar CMOS. All of this is achieved using current manufacturing methods, materials, and tools, and high-performance devices with 50 nm physical gate lengths ( L G) have been demonstrated with precise gate length control without advanced lithography.

Control of a Metal-Electrode Work Function by Solid-State Diffusion of Nitrogen

AbstractThe work function of a metal gate electrode has been adjusted with the introduction of nitrogen by solid-source diffusion from an over-stoichiometric TiN1+x layer. RBS measurements have shown that measurable concentrations of nitrogen can be diffused into a 10nm Ta layer at moderate anneal temperatures (&gt;500°C), and that this concentration increases with temperature in the range 500-1000°C. Capacitance-voltage measurements have been carried out on 10nm tantalum layers on Al2O3. These measurements have indicated that the work function of tantalum changes by -0.08eV due to the presence of the over-stoichiometric TiN1+x covering layer during anneal (800°C/30”). Similar C-V measurements have been carried out on 10nm molybdenum layers on SiO2 and on Al2O3 dielectrics. These have shown that the work function of molybdenum is substantially different for metal stacks with the TiN1+x covering layer after a similar anneal. The work function changes by -0.52eV for molybdenum on SiO2 and by -1.1eV for molybdenum on Al2O3. The results suggest great potential for molybdenum as a candidate for a single-metal dual-work function approach to integrating metal gates into future CMOS technologies.

Impact of N/sub 2/O activation treatment on junction characteristics of p/sup +//n junctions formed by a solid diffusion source

The authors have investigated p/sup +//n junctions formed by a solid-boron-source under different activation ambient gases. It was found that the junction depth strongly depends on the activation ambient gas and the corresponding flow rate. Especially in the N/sub 2/O ambient, the diffusion of boron is enormously enhanced. Furthermore, the thermal stability of CoSi/sub 2/ is profoundly improved by the N/sub 2/O treatment during activation.

Development of an emitter for industrial silicon solar cells using the doped oxide solid source diffusion technique

The aim of this paper is to demonstrate for the first time the feasibility of fabricating large-area screen-printed monocrystalline silicon solar cells using the Doped Oxide Solid Source (DOSS) diffusion technique. This process was applied to form the n +p emitter junction from highly doped sources prepared in a POCl 3 ambient. The diffusions were performed under a pure nitrogen flow in the temperature range 900–1050°C. In this investigation attention was devoted to the influence of the source doping level on the fill factor. The solar cells were fabricated on industrial quality 4-inch Cz wafers using a simple processing sequence incorporating screen-printed contacts and a TiO 2 antireflection coating deposited by spin-on. Fill factors as high as 79% were obtained. The potential benefit of retaining for passivation purposes the thin residual oxide grown during phosphorus diffusion was evaluated. These first experiments led to a cell efficiency close to 10%.

The Application of Solid Source Diffusion in the Vertical Replacement-Gate (VRG) MOSFET

AbstractWe discuss the first use of solid source diffusion (SSD) to form shallow, self-aligned SDEs in a novel device known as the Vertical Replacement-Gate (VRG) MOSFET. This is the only MOSFET ever built that combines 1) a gate length controlled precisely through a deposited film thickness, independently of lithography and etch, and 2) a high-quality gate oxide grown on a single-crystal Si channel. The use of SSD in this novel geometry allows us to transform the precise gate length control afforded by the VRG process into precise, lithography-independent channel length control. In the VRG-nMOS process, silicon nitride offset spacers separate the phosphosilicate glass (PSG) SSD dopant sources from the polysilicon gate. These offset spacers, whose critical dimensions are also controlled by film thicknesses, allow us to precisely tune the gate-source and gate-drain overlaps in order to optimize the capacitance/series resistance tradeoff. These parasitic overlap capacitances have precluded the high-frequency operation of many previous vertical MOSFETs. In this paper, we discuss the SIMS and sheet resistance characterization of shallow phosphorus junctions formed in one-dimensional SSD experiments. We will also discuss the scanning capacitance characterization of two-dimensional doping profiles of VRG-nMOSFETs with gate lengths down to 50 nm.

High sensitivity acoustic transducers with thin p+ membranes and gold back-plate

High sensitivity acoustic transducers (microphones) have been fabricated on 5″ wafers in a production environment and the experimental results are presented. One of the main advantage of this microphone design is that it can be fabricated on a single wafer eliminating the need for the multiple wafers and subsequent wafers bonding steps as in conventional designs. The devices use thin (∼3 μm) p+ silicon membranes as the active movable element and a thick perforated plated gold back plate. The p+ membranes are fabricated using an optimized boron solid source diffusion at 1150°C. Ethylene–Diamine–Pyro-Catecol (EDP) etching at 100°C was performed from the backside of double-sided polished wafers to release the thin silicon membranes. The zero-bias capacitance with the air gap was 2.2 pF and it increased to 2.4 pF at 9 V. The frequency response was measured and the measured sensitivity of 5.28 mV/Pa at 5 V and 10.77 mV/Pa at 9 V at 1 kHz are among the highest reported in literature for micro-machined acoustic transducers.

Surface and thin film analysis of CdTe layers for solar cells

A solid state diffusion source with appropriate concentrations of donor and acceptor impurities has been used for studying the processes which occur during the thermal treatment of CdTe layers. The surface of the CdTe is investigated by XPS before and after annealing. The element ratios on the CdTe layer surface are determined in at%. Mathematical processing of the XP spectra is used to establish the ratios between the elements bound on the CdTe layer surface. The chemistry of the annealing-caused changes in CdTe layer properties are discussed.

Solid planar diffusion sources based on phosphorus nitride prepared by a one-stage process in a pulse discharge

Some properties of phosphorus-nitride-based coatings as planar diffusion sources have been studied. The synthesis and deposition were carried out in a one-stage process using a low pressure pulsed electric discharge. By spectroscopic means some details of the coating deposition mechanism were investigated.

Ultra-shallow raised p+−n junctions formed by diffusion from selectively depositedIn-situ doped Si0.7Ge0.3

In this paper, a novel raised p+−n junction formation technique is presented. The technique makes use ofin- situ doped, selectively deposited Si0.7Ge0.3 as a solid diffusion source. In this study, the films were deposited in a tungsten halogen lamp heated cold-walled rapid thermal processor using SiCl2H2, GeH4, and B2H6. The microstructure of the Si0.7Ge0.3 layer resembles that of a heavily defected epitaxial layer with a high density of misfit dislocations, micro-twins, and stacking faults. Conventional furnace annealing or rapid thermal annealing were used to drive the boron from thein- situ doped Si0.7Ge0.3 source into silicon to form ultra-shallow p+−n junctions. Segregation at the Si0.7Ge0.3/Si interface was observed resulting in an approximately 3:1 boron concentration discontinuity at the interface. Junction profiles as shallow as a few hundred angstroms were formed at a background concentration of 1017 cm−3.