Solder Interconnects Research Articles

Mechanism on preferred orientation roof-type Cu6Sn5 grain formation in micro-bump with (111) nanotwinned copper UBM

The (111) nanotwinned copper films used as a novel under bump metallization (UBM) were applied in micro-bump solder technology for 3D packaging. The orientation and morphology of interfacial Cu 6 Sn 5 grains on (111) nanotwinned copper UBMs were investigated by soldering at different temperatures (250 °C and 300 °C). The (11−20) preferred orientation roof-type Cu 6 Sn 5 intermetallic compound (IMC) formed on Sn/(111) nanotwinned copper interface at a higher soldering temperature of 300 °C; while random orientation scallop-type Cu 6 Sn 5 grains formed on Sn/(111) nanotwinned copper interface at lower soldering temperature of 250 °C. The preferred orientation relationships between and interfacial roof-type Cu 6 Sn 5 grains and (111) nanotwinned copper UBMs are {11−20} Cu6Sn5 ||{111} copper in 〈0001〉 Cu6Sn5 ||〈011〉 copper and {11–20} Cu6Sn5 ||{111} copper in 〈10−10〉 Cu6Sn5 ||〈112〉 copper . Moreover, the average shear strength of the (111) nanotwinned copper/Sn/(111) nanotwinned copper solder interconnects soldered at 300 °C (40.19 MPa) is 30% higher than that soldered at 250 °C (31.09 MPa). This study provides an insight in controlling the morphology and orientation of interfacial Cu 6 Sn 5 grains on the (111) nanotwinned copper used as UBMs for the 3D packaging application. • Random intersecting angles of roof-type Cu 6 Sn 5 grains formed on (111) nt-Cu UBM. • ORs: {11–20} η ||{111} Cu in <0001> η ||<011 > Cu , {11–20} η ||{111} Cu in<10–10 > η||<112 > Cu . • Average shear strength of the solder interconnects soldered at 300 °C is 40.19 MPa.

Interfacial reaction, shear behavior and microhardness of Cu-Sn TLP bonding joints bearing CuZnAl powder for 3D packaging

The process of transient liquid phase bonding to form intermetallic compound solder joints can effectively achieve 3D chip stack interconnection. However, there are a large number of void defects in IMC solder joints due to the rapid reaction between elements, which reduces the reliability of the chip stack interconnection. In this study, the interfacial reaction, shear behavior and microhardness of CuSn TLP bonding joints were investigated by adding 0.5 wt% CuZnAl powder into the pure Sn interconnect solder. Adding CuZnAl powder can remarkably retard the growth of intermetallic compound and voids in the bonding joints, which is attributed to the fact that CuZnAl powder can reduce the concentration gradient of Cu in the interface region. Compared with the Cu-Sn-Cu bonding joints, the shear strength of composite bonding joints was increased by 12%–19.7%, and the microhardness of composite bonding joints was also improved.

Mechanical Performance and Reliability of a Sn–Ag–Cu–Sb Alloy at Elevated Temperatures

Solder interconnects are essential to the reliability of electronic devices. The addition of alloying elements was reported to provide beneficial effects to the microstructure and mechanical reliability of lead-free solder alloys. In this work, the effects of Sb addition on the mechanical behavior of SAC305 solder alloy were investigated. Based on differential thermal analysis, it was observed that melting point of SAC-Sb solder was slightly higher than that of SAC305. The mechanical behavior was studied at different temperatures (25 °C-125 °C) and strain rates ( 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-4</sup> - 1×10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-2</sup> 1/s) for SAC-Sb and SAC 305 solders as a comparison. From the results, ultimate tensile strength of SAC-Sb (10-72 MPa) was generally higher than that of SAC305 (4.54-61.5 MPa) at the aforementioned test conditions. A linear relation between the UTS and yield strength and temperature was identified for test results of SAC305, but the relation was found to be nonlinear for SAC-Sb solder because of solution strengthening effect of Sb in the Sn matrix. Parameters of Anand model were estimated based on mechanical behavior of SAC-Sb and SAC305 solders. Next, the model was used to evaluate thermal fatigue life of an insulated gate bipolar transistor (IGBT) module with SAC-Sb and SAC305 as chip-to-directed bonding copper (DBC) and DBC-to-baseplate attachment materials by finite element modeling. The increase of maximum inelastic strain in one thermal cycle in SAC-Sb solder joints was lower than that in SAC305 solder joints. This result indicates that SAC-Sb solder can provide a considerably better fatigue life under harsh service conditions.

No-flow underfill: Effect of chip placement speed on the void formation using numerical method

No-flow underfill process can enhance the production lead time since the curing and reflow of solder interconnect and underfill are achieved simultaneously. Additionally, no-flow underfill can produce near void-free flow during the assembly process. This paper investigates the effect of chip placement speed towards the void formation of no-flow underfill process using numerical simulation and experimental methods. The findings show that the increase in chip placement speed effectively increased the gauge pressure and velocity of the underfill flow. The highest chip placement speed of 14 ​mm/s produces 12,300 ​Pa of gauge pressure and 0.1 ​m/s of underfill flow velocity. The flow profiles revealed that finger-like profile was formed above 5 ​mm/s speed during the compression process of no-flow underfill that will lead to issue of void formation in the ball grid array (BGA) region. This study recommended the usage of below 5 ​mm/s of chip placement speed to minimize the issue of finger-like formation and subsequently void formation.

Crystalline Silicon (c-Si) Solar Cell Interconnect Damage Prediction Function Based on Effect of Temperature Ramps and Dwells on Creep Damage under Field Thermal Cycling

c-Si solar cell interconnection damages from thermal cycles emanate from cumulative damage contributions from the various load steps in a typical thermal cycle. In general, a typical thermal cycle involves five thermal load steps, namely: 1st cold dwell, ramp-up, hot dwell, ramp-down, and 2nd cold dwell. To predict the contributions of each of these load steps to creep damage in soldered interconnections, each of the respective load steps needs to be profiled to accurately fit a function capable of predicting the damage contributions from a given number of thermal cycles. In this study, a field thermal cycle profile generated from in situ thermal cyclings at a test site in Kumasi, a hot humid region of sub-Saharan Africa, is used to predict damage in solar cell interconnections from accumulated creep energy density using finite element analysis (FEA). The damage was assessed for two different solder formulations, namely: Pb60Sn40 and Sn3.8Ag0.7Cu (lead-free). The results from the FEA simulations show that the cooling (ramp-down) load steps accounted for the highest accumulated creep energy density (ACED) damage in solder interconnections. The ramp-up load steps followed this closely. The cumulative contributions of the two load steps accounted for 78% and 88% of the total damage per cycle in the Pb60Sn40 and Sn3.8Ag0.7Cu solder interconnections, respectively. Furthermore, a study of the damage profiles from each of the five load steps revealed that each of the damage functions from the various load steps is a step function involving the first two thermal cycles, on one hand, and the remaining 10 thermal cycles on the other hand. The damage from the first two thermal cycles can be predicted from a logarithmic function, whereas the damage from the remaining 10 thermal cycles is predicted using six-order polynomial functions. The ACED results computed from the damage functions are in close agreement with the results from the FEA simulation. The functions generated provide useful relations for the prediction of the life (number of cycles to failure) of solder interconnections in solar cells. The systematic approach used in this study can be repeated for other test sites to generate damage functions for the prediction of the life of c-Si PV cells with SnPb and lead-free solder interconnections.

Effect of high current pulses on solder interfacial reaction and interconnect reliability

The trend of electrification and miniaturization brings the reliability of interconnects to the forefront. The solder joints are subjected to thermo-mechanical mismatch due to the Joule heating and electromigration (EM)-induced degradation under high current stressing conditions. However, most of the studies are limited to lab test samples or lab test conditions, which lack transferability in engineering applications. In this paper, automotive electronic components are studied subjected to field-like current pulse conditions. The work aims to understand the field-relevant failure modes of solder joints exposed to high current stressing via experimental and numerical investigations. Shunt components with and without Ni plating are analyzed in power cycling tests. A polarity effect is observed in the growth of intermetallic compounds (IMCs). The thickness of IMC at the anode exhibits an approximately linear growth with current stressing time, whereas the thickness of IMC at the cathode remains almost unchanged or slightly decreased. Ni, as diffusion barrier, serves to restrain Cu consumption from the terminals of shunts and also reduces Cu mass transport into and within the solder. The net Cu flux at the interface and in the solder is discussed to analyze the IMC growth kinetics. The shunts with Ni plating undergo less EM of Cu and yield longer lifetime. Voids and crack formation are detected in computer tomography (CT) scans and cross-sectional analysis by scanning electron microscopy (SEM). Finite element method (FEM) is implemented to simulate thermo-electro-mechanical fields of the assembly under power cycling test conditions. The distribution of divergence of material flux density corresponds well with the location of voids formation and provides good estimation for the lifetime.

Study on Creep Damage in Sn60Pb40 and Sn3.8Ag0.7Cu (Lead-Free) Solders in c-Si Solar PV Cell Interconnections under In-Situ Thermal Cycling in Ghana

A numerical study on the creep damage in soldered interconnects in c-Si solar photovoltaic cells has been conducted using equivalent creep strain, accumulated creep strain and accumulated creep energy density methods. The study used data from outdoor weathering of photovoltaic (PV) modules over a three-year period (2012–2014) to produce temperature cycle profiles that served as thermal loads and boundary conditions for the investigation of the soldered interconnects’ thermo-mechanical response when exposed to real-world conditions. A test region average (TRA) temperature cycle determined in a previous study for the 2012–2014 data was also used. The appropriate constitutive models of constituent materials forming a typical solar cell were utilized to generate accurate material responses to evaluate the damage from the thermal cycles. This study modeled two forms of soldered interconnections: Sn60Pb40 (SnPb) and Sn3.8Ag0.7Cu (Pb-free). The results of the damage analysis of the interconnections generated from the thermal cycle loads using accumulated creep strain method showed that the Pb-free solder interconnection recorded greater damage than that of the SnPb-solder interconnection for the TRA, 2012, 2013 and 2014 temperature cycles. The percentage changes from SnPb to Pb-free were 57.96%, 43.61%, 44.87% and 45.43%, respectively. This shows significant damage to the Pb-free solder under the TRA conditions. Results from the accumulated creep energy density (ACED) method showed a percentage change of 71.4% (from 1.3573 × 105 J/mm3 to 2.3275 × 105 J/mm3) in accumulated creep energy density by replacing SnPb-solder with Pb-free solder interconnection during the TRA thermal cycle. At the KNUST test site in Kumasi, Ghana, the findings show that Sn60Pb40 solder interconnections are likely to be more reliable than Pb-free solder interconnections. The systematic technique employed in this study would be useful to the thermo-mechanical reliability research community. The study also provides useful information to PV design and manufacturing engineers for the design of robust PV modules.

Preparation and sintering characteristics of nanosilver-tin core–shell paste

Nanosilver paste, an interconnect solder, is a common choice in the electronic packaging industry; however, higher sintering temperatures and lower sintering strength limit its application. At present, core–shell nanoslurry has been studied and applied to chip interconnection. Based on the mechanism of heterogeneous flocculation, we have developed a new nanosilver wrapped tin paste (Sn@Ag paste), and according to the decomposition temperature of the organic dispersant in the slurry, a corresponding sintering process with a temperature of 300 °C was developed. The Sn@Ag core–shell structure makes Sn have good dispersibility and oxidation resistance, and the sintered product of the slurry is a mixture of a solid solution of Ag and an Ag3Sn phase. Among them, the hard and brittle phase Ag3Sn acts as a dispersion strengthening effect in the Ag matrix phase, and the solid solution of Ag acts as a replacement solid solution strengthening. With the increase of doping Sn content, the sintering strength is significantly improved. When the Sn content is 5%, the joint shear strength reaches the highest value of 55 Mpa, which is higher than the pure nanosilver paste by 10 Mpa. This new nanosilver wrapped tin paste technology has the characteristics of low-temperature sintering and high-temperature service.

Copper Trace Fatigue Life Modeling for Rigid Electronic Assemblies

While solder interconnects tend to be the focus of reliability studies in electronics, increased exposure to flexural loads and the use of stiffer (higher density) packages are raising concern regarding the fatigue failure of copper metallization (traces and solder pads) on printed circuit boards. To better understand the failure risks of copper trace, experiments examining the effect of variations in solder pad and trace design on the fatigue durability of copper traces were conducted. Experiments were also conducted to determine the impact of assembly variations, presence of surface finish, solder mask, and assembled components, on the fatigue durability of the traces. The durability data collected from the experiment was used in conjunction with the finite element analysis estimated critical trace strain ranges to develop a set of compatible fatigue model constants that best fit the failure behavior observed in the tests. Finally, the established fatigue life model constants were validated with additional tests conducted at different load level. The predicted cycles to failure compared well with the experimental cycles to failure.

Study of Different Dispensing Patterns of No-Flow Underfill Using Numerical and Experimental Methods

Abstract The conventional capillary underfill process has been a common practice in the industry, somehow the process is costly and time-consuming. Thus, no-flow underfill process is developed to increase the effective lead time production since it integrates the simultaneous reflow and cure of the solder interconnect and underfill. This paper investigates the effect of different dispense patterns of no-flow underfill process by mean of numerical and experimental method. Finite volume method (FVM) was used for the three-dimensional (3D) simulation to simulate the compression flow of the no-flow underfill. Experiments were carried out to complement the simulation validity and the results from both studies have reached a good agreement. The findings show that of all three types of dispense patterns, the combined shape dispense pattern shows better chip filling capability. The dot pattern has the highest velocity and pressure distribution with values of 0.0172 m/s and 813 Pa, respectively. The high-pressure region is concentrated at the center of the chip and decreases out toward the edge. Low in pressure and velocity flow factor somehow lead to issue associated with possibility of incomplete filling or void formation. Dot dispense pattern shows less void formation since it produces high-pressure underfill flow within the ball grid array (BGA). This paper provides reliable insight into the industry to choose the best dispense pattern of recently favorable no-flow underfill process.

Life prediction in c-Si solar cell interconnections under in-situ thermal cycling in Kumasi in Ghana

PurposeA numerical study on the reliability of soldered interconnects of c-Si solar photovoltaic cells has been conducted.Design/methodology/approachA three-year data (2012–2014) from outdoor weathering of PV modules was used to generate temperature cycle profiles to serve as thermal loads and boundary conditions for the investigation of the thermo-mechanical response of the soldered interconnects when subjected to real outdoor conditions using finite element analysis (FEA) Software (Ansys. 18.2). Two types of soldered interconnections, namely, Sn60Pb40 and Sn3.8Ag0.7Cu (Pb-free), were modelled in this study.FindingsLife prediction results from accumulated creep energy density damage show that the solder interconnects will achieve maximum life under the 2014 thermal cycle loading. In particular, the Sn60Pb40 solder interconnection is expected to achieve 14,153 cycles (25.85 years) whilst the Pb-free solder interconnection is expected to achieve 9,249 cycles (16.89 years). Additionally, under the test region average (TRA) thermal cycle, the Pb-free and Pb-Sn solder interconnections are expected to achieve 7,944 cycles (13.69 years) and 12,814 cycles (23.4 years), respectively. The study shows that Sn60Pb40 solder interconnections are likely to exhibit superior reliability over the Pb-free solder interconnections at the test site.Practical implicationsThis study would be useful to electronics manufacturing industry in the search for a suitable alternative to SnPb solders and also the thermo-mechanical reliability research community and manufacturers in the design of robust PV modules.Originality/valueThe study has provided TRA data/results which could be used to represent the test region instead of a particular year. The study also indicates that more than six thermal cycles are required before any meaningful conclusions can be drawn. Finally, the life of the two types of solders (SnPb and Pb-free) as interconnecting materials for c-Si PV have been predicted for the test region (Kumasi in sub-Saharan Africa).

Electrical and Microstructural Reliability of Pressureless Silver-Sintered Joints on Silicon Carbide Power Modules Under Thermal Cycling and High-Temperature Storage

Low-temperature and pressureless silver (Ag) sintering was applied to a 1200 V/200 A silicon carbide (SiC) metal-oxide-semiconductor field-effect transistor (MOSFET) power module with a Ag-finished silicon nitride active metal-brazed substrate, and the results were evaluated for applicability in electric and hybrid electric vehicles. The sintering was performed at 220–240°C, 90 min in vacuum under nitrogen gas conditions; the bonding strength, bonding layer thickness (BLT), void content, and densification of the as-sintered Ag joints were 39 MPa, 71.4 µm, 2%, and 90.5%, respectively. The shear strength, BLT, densification, and microstructure of the Ag-sintered joints were compared before and after the thermal cycling test (− 50–150°C, 1100 cycles, TCT) and high temperature storage test (200°C, 1000 h, HTST). To simultaneously compare the electrical properties of the SiC power module with lead (Pb)-free solder joints, the same SiC MOSFET power module was manufactured using a Sn-3.0Ag-0.5Cu (SAC305) Pb-free solder. The shear strength and densification after TCT and HTST were 35.5 MPa and 39.7 MPa, as well as 92.8% and 94.8%, respectively. The on-resistance and total switching efficiency of the SiC power module with the Ag-sintered joint were also compared to those of the SAC305 solder joint module, which evinced maximum values of 7.3 mΩ and 10.7 mJ that were superior to those of 8.5 mΩ and 11.3 mJ for the SAC305 solder joint, respectively. Under the same measurement conditions, the maximum generated current and voltage values are lower than those of the solder joint module, so it is envisaged that stable power module operation is realizable for long-term use. The Ag-sintered joint surpassed the SAC305 solder interconnects in terms of the electrical and mechanical reliability of the power module. When a SiC wide band gap device was used, it was discovered that Ag sintering was superior to Pb-free solder interconnects to increase the power conversion efficiency of the power module.

Bond shear strength of Al2O3 nanoparticles reinforced 2220-capacitor/SAC305 solder interconnects reflowed on bare and Ni-coated copper substrate

The influence of Al2O3 nanoparticles addition in trace amounts and electroless Ni–P substrate coating on the microstructure development and bond shear strength of Sn-3.0Ag–0.5Cu (SAC305) solder joint were investigated. The performance and reliability of the 2220-capacitor joints with Al2O3 nanoparticle reinforced nanocomposites reflowed on Cu and Ni–P coated substrate were analyzed under varying high-temperature environments. The addition of nanoparticles enhanced the wettability and microhardness of the solder and considerably refined the joint microstructure. The dispersion and adsorption of Al2O3 nanoparticles resulted in the suppression of intermetallic (IMC) growth at the interface and refinement of the β-Sn grains as well as IMC precipitates into the matrix. The Ni–P coating on the substrate significantly retarded the IMC growth kinetics resulting in the formation of a thin and uniform IMC layer at the joint interface. The thermal stability and performance of the joint under high-temperature environments were enhanced due to the Ni–P coating on the substrate. Compared to the unreinforced SAC305 solder joint with bare Cu substrate, joints with SAC305 + 0.05Al2O3 composite showed about 17% higher shear strength with bare Cu substrate and about 27% higher strength with Ni–P coated substrate. The Weibull distribution analysis indicates a significant improvement in joint reliability of the 2220-capacitor/SAC305 solder assembly using SAC305 + 0.05Al2O3 nanocomposite and Ni-coated substrate. The ANOVA study suggests that the solder joint performance majorly depends on the operating environment, solder composition, and the substrate finish.

Research on Wiener Degradation Model and Failure Mechanism of Interconnect Solder Joints Under Random Vibration Load

Electronic packaging solder joints are the key parts of mechanical fixation and electrical interconnection between electronic chips and printed circuit boards, which are prone to failure and lead to electronic device failures under the action of vibration environment stress. In regard to the failure characterization and degradation modeling of electronic packaging solder joints under vibration load, this paper adopts environmental stress tests, builds a vibration failure test platform, designs a vibration load excitation spectrum, and obtains solder joint degradation data under vibration stress; it uses the square root amplitude, form factors, and kurtosis factors to characterize the solder joint degradation process, which effectively identify the solder joint degradation node, and improve the data monotonicity of the solder joint degradation process; the Wiener process is used to build a solder joint multi-stage degradation model. Based on the EM algorithm, the hyperparameters of the degradation model have been optimized, and the universal test of the Wiener degradation model with multiple samples is carried out in accordance with the LB index. The analysis shows that the effectiveness of different samples is as high as 87.5%, which verifies the universality of the Wiener degradation model; Based on the crack morphology subject to the solder joint test and the features of the solder joint in the multi-stages, the paper analyzes the crack propagation behavior of the solder joint, and clarifies the failure mechanism of the solder joint.

Comparison of Nondestructive Testing Methods for Solder, Sinter, and Adhesive Interconnects in Power and Opto-Electronics

Reliability is one of the major requirements for power and opto-electronic devices across all segments. High operation temperature and/or high thermomechanical stress cause defects and degradation of materials and interconnects, which may lead to malfunctions with costly or even life-threatening consequences. To avoid or at least reduce failures, nondestructive testing (NDT) methods are common within development and production of power and opto-electronics. Currently, the dominating NDT methods are X-ray, scanning acoustic microscopy (SAM), and transient thermal analysis (TTA). However, they have different strengths and weaknesses with respect to materials and mechanical designs. This paper compares these NDT methods for different interconnect technologies, i.e., reflow soldering, adhesive, and sintered interconnection. While X-ray provided adequate results for soldered interfaces, inspection of adhesives and sintered interconnects was not possible. With SAM, evaluation of adhesives and sintered interconnects was also feasible, but quality depended strongly on the sample under test. TTA enabled sufficiently detailed results for all the interconnect applications. Automated TTA equipment, as the in-house developed tester used within this investigation, enabled measurement times compatible with SAM and X-ray. In the investigations, all methods revealed their pros and cons, and their selection has to depend on the sample under tests and the required analysis depth and data details. In the paper, guidelines are formulated for an appropriate decision on the NDT method depending on sample and requirements.

Accelerated mechanical low cycle fatigue in isothermal solder interconnects

Properly assessing the underlying physics of failure is critical in predicting the long term reliability of electronic packages in their intended field applications, yet traditional reliability demonstration methods are complicated by time and cost considerations as well as deterministic inadequacies when considering thermomechanical failures. In this work, an alternative reliability testing apparatus and associated protocol were utilized to provide clarity and insight to solder fatigue mechanisms at the device scale; targeting rapid testing times with minimal cost while preserving fatigue life prediction accuracy. A test stand was developed to allow for bi-directional application of shear stress at elevated steady-state temperatures. Utilizing the mechanical force of springs to apply shear loads to solder interconnects within the devices, the reliability of a given device to withstand repeated cycling was studied using in situ resistance monitoring techniques to detect the number of cycles-to-failure (CTF) based on a 30% resistance increase criterion. A mathematical method for quantifying the plastic work density (amount of damage) sustained by the solder interconnects prior to failure was developed relying on the relationship between Hooke's Law for springs and damage deflection to accurately assess the mechanical strength of tested devices.

Evolution of Anand Parameters With Elevated Temperature Aging for SnAgCu Lead-free Alloys

Abstract Electronic components in downhole oil drilling and gas industry applications, automotive, and avionics may be exposed to high temperatures (&amp;gt;150 °C) and high strain rates (1–100 per sec) during storage, operation, and handling, which can contribute to the failures of electronic devices. Temperatures in these applications can exceed 200 °C, which is close to melting point for SnAgCu (SAC) alloys. Prior studies at low strain rates have shown property evolution even under moderate exposure to high temperature. In this paper, the evolution of Anand parameters for unaged and aged SAC (SAC105 and SAC-Q) lead-free solder alloys at high strain rates has been investigated induced under sustained periods of thermal aging. The thermal aged lead-free SAC solder alloys specimen has been tested at high strain rates (10–75 per sec) at elevated temperatures of (25 °C–200 °C). The SAC lead-free solder samples were subjected to isothermal aging at 50 °C up to 1-year before testing. To describe the material constitutive behavior, the Anand Viscoplastic model has been used. The effect of thermal aging on Anand parameters also has been investigated. In order to verify the accuracy of the model, the computed Anand parameters have been used to simulate the uni-axial tensile test. The material constitutive behavior has been implemented in a finite element framework to simulate the drop events using the Anand constitutive model and determine the plastic work per shock event. The plastic work per shock event is a measure of the damage progression in the solder interconnects. The constitutive model has been used to simulate the shock event of a ball-grid array package on printed circuit board assembly.

Impact of Conformal Coating Induced Stress on Wafer Level Chip Scale Package Thermal Cycling Performance

Conformal coating is commonly used for harsh environment to protect electronics from moisture and chemical contaminants. But the stresses imparted by the conformal coating can cause degradation to the package thermal cycle performance. Full coverage of the component with conformal coating material can prevent potential corrosion induced degradation but imply a local compression stress during thermal cycling, resulting a different thermal cycling performance compared to non-coated components. In this study, 8x8mm2 wafer level chip scale packages (WLCSP) were subjected to 5% NaCl aqueous spray test with and without full conformal coating, then thermal cycled from -40ºC to +125ºC. Weibull reliability statistics indicated that fully conformal coated components experience characteristic life cycle number reduction from 404 cycles to 307 cycles, a 24% lifetime reduction, comparing to no conformal coated, no salt spray test applied components. The correlation between crack propagation and localized recrystallization were compared in a series of cross section analyses using polarized imaging and electro-backscattered diffraction, which revealed that the conformal coating induced a z-axis tension and compression strain during thermal cycling, resulting in an accelerated degradation at the solder interconnect. Linear Laser profilometer measurements showed that fully conformal coated samples experienced a higher z-axis height displacement change relative to non-conformal coated samples when exposed to 125 °C with 10 minutes dwell. To prevent this z-axis strain a reworkable edgebond adhesive was applied with full conformal coating configuration, which demonstrate an increase of characteristic lifecycle number to 2783 cycles, suggesting that the mitigation of the z-axis strain can vastly enhance the thermal cycling performance.

A short review: Properties of superconducting solder

Development of electronic devices were moving towards miniaturization, multifunction and increasingly specific service environment of solder interconnects, where this drive to the higher requirements on the solder properties. Without solder, it would be impossible to produce the infinite electronic devices that define the 21st century. Hence, solder is important in the design and engineering process. This review paper was summarized on the literature of the low-temperature solder systems for superconducting solder materials, which provide further theoretical basis for the study of superconducting solder of electronic and aerospace applications. Pb-Bi system is the most satisfactory solder as a superconducting solder, but due to the restrictions of the lead usage, so new Pb-free superconducting solder need to be invented. Of those Pb-free superconducting materials had been studied, the Sn-In-Bi ternary solder system show the greatest superconducting properties as compared to other Pb-free superconducting solder where TC = 6.9 K, HC2 (4.2 K) = 0.18 T and JC (4.2 K, 0.01 T) = 1.3 × 108 A/m2 respectively.

Comparative Study on Reliability and Advanced Numerical Analysis of BGA Subjected to Product-Level Drop Impact Test for Portable Electronics

In this paper, drop reliability of various PBA (printed board assembly) mounting structures is investigated and compared. Then, we built SAC305 (Sn3.0Ag0.5Cu) interconnects for BGA (ball grid array) package failure model to evaluate the drop impact reliability of handheld devices. In order to simulate actual behavior of the solder joint under the drop impact load of handheld devices, we perform explicit full FEA (finite element analysis) modeling. However, this takes a lot of computing time because of the large aspect ratio of element size between solder joints and other structures such as PCB (printed circuit board) and electronic packages. Therefore, an effective way to represent solder interconnects for FEA is needed which would be relatively simpler yet detailed. Comparable board-level drop tests are conducted after equipping test vehicles with various fixtures considering PBA mounting structures, which make it possible to apply different loading conditions to BGA packages. The results show different drop impact life for solder interconnects depending on the mounting design of the PBA. Particularly, the solder interconnect of the component located at the middle of the PCB exhibits the shortest impact life where the highest tensile stress occurs. Also, the mounting design restraining PBA deflections shows better reliability under the drop impact loading. Sequentially, simulating with a PBA composed of the BGA package and the PCB is considered to assess the feasibility of the solder ball failure modeling when the drop impact load is applied. Especially, for the modeling of the solder balls, detailed solid model and simple beam model are compared regarding computational efficiency and numerical accuracy. We found that the simple beam model significantly shortens computational time from 110 h to less than an hour. Accordingly, the feasibility of the beam model for the solder balls is shown by correlating the stress level and the drop impact life obtained from the experiments.