Smart CutTM Process Research Articles

A comparative 1/ f noise study of GeOI wafers obtained by the Ge enrichment technique and the Smart Cut technology

This paper presents an experimental investigation of Low-frequency Noise (LFN) measurements on Germanium-On-Insulator (GeOI) PMOS transistors processed on different wafers. The wafers are obtained by Ge enrichment technique and by Smart Cut™ technology. The slow oxide trap densities of back interface are used as a figure of merit to evaluate the process. The Smart Cut™ process is evaluated by studying GeOI pMOSFETs, and the enrichment process by studying Si 1− x Ge x ( x = 25% and 35%) pMOSFETs. The buried oxide is used as a back gate for experimental purposes. The extracted values are of the same order of magnitude for both processes and are close to those of state of art buried oxide SiO 2/Si interfaces, demonstrating that both the Smart Cut™ and enrichment techniques produce equally good quality interfaces.

Fabrication, structural and electrical properties of compressively strained Ge-on-insulator substrates

Compressively strained germanium-on-insulator (c-GeOI) substrates with a definitely reduced defect density are expected to yield superior hole mobilities together with low off-state currents in p-type metal oxide semiconductor field effect transistors (MOSFETs). In order to fabricate c-GeOI wafers, we started with double-side polished Si(0 0 1) substrates and grew, by reduced pressure-chemical vapour deposition, Si0.15Ge0.85 virtual substrates (VS) on the front side. The wafer curvature was compensated thanks to the deposition of a thick Ge layer on the backside. We then grew, after a chemical mechanical polishing, various thickness (37–148 nm) Ge layers. They stayed smooth (root-mean-square roughness <5 Å) and pseudomorphically strained on the VS underneath (perpendicular lattice parameter: 5.681 Å ⇔ bulk Ge lattice parameter: 5.658 Å) up to a 74 nm thickness. These c-Ge layers were then bonded on oxidized Si substrates using the SmartCut™ process. The resulting c-GeOI substrates were of high crystalline quality, compressively strained and smooth. The threading dislocations density (8 × 105 cm−2 ⇔ 1.7 × 105 cm−2 for the SiGe VS template used to strain the c-Ge layers) was indeed 20 times less than the one associated with conventional GeOI substrates obtained from thick Ge epilayers. Pseudo-MOSFET measurements were performed to quantify the hole mobility gain in those c-GeOI substrates. A +150% enhancement compared to conventional silicon-on-insulator substrates was evidenced, validating the interest of these stacks.

Heterogeneous Integration of Compound Semiconductors

The ability to tailor compound semiconductors and to integrate them onto foreign substrates can lead to superior or novel functionalities with a potential impact on various areas in electronics, optoelectronics, spintronics, biosensing, and photovoltaics. This review provides a brief description of different approaches to achieve this heterogeneous integration, with an emphasis on the ion-cut process, also known commercially as the Smart-Cut™ process. This process combines semiconductor wafer bonding and undercutting using defect engineering by light ion implantation. Bulk-quality heterostructures frequently unattainable by direct epitaxial growth can be produced, provided that a list of technical criteria is fulfilled, thus offering an additional degree of freedom in the design and fabrication of heterogeneous and flexible devices. Ion cutting is a generic process that can be employed to split and transfer fine monocrystalline layers from various crystals. Materials and engineering issues as well as our current understanding of the underlying physics involved in its application to cleaving thin layers from freestanding GaN, InP, and GaAs wafers are presented.

Fabrication of Silicon on Diamond (SOD) substrates by either the Bonded and Etched-back SOI (BESOI) or the Smart-Cut™ technology

In this paper, Silicon on Diamond (SOD) substrates were fabricated using the direct bonding process in two different technologies: the BESOI (Bonded and Etched-back SOI) and the Smart-Cut™ process. The polycrystalline diamond (C∗) film deposited by Chemical Vapor Deposition assisted by Microwave Plasma (MPCVD) was planarized by an innovative process which induces a significant decrease of the diamond surface roughness (1.2nm for the 200nm diamond layer). The planarization method as well as the entire SOD substrate process by the BESOI or the Smart-Cut™ technology are described in the paper. Cross sectional high-resolution transmission microscopy reveals the good quality of the future silicon channel on top of the thin diamond layer.

105 nm Gate length pMOSFETs with high-K and metal gate fabricated in a Si process line on 200 mm GeOI wafers

We report on the fabrication and electrical characterization of deep sub-micron (gate length down to 105nm) GeOI pMOSFETs. The Ge layer obtained by hetero-epitaxy on Si wafers has been transferred using the Smart CutTM process to fabricate 200mm GeOI wafers with Ge thickness down to 60–80nm. A full Si MOS compatible pMOSFET process was implemented with HfO2/TiN gate stack. The electrical characterization of the fabricated devices and the systematic analysis of the measured performances (ION, IOFF, transconductance, low field mobility, S, DIBL) demonstrate the potential of pMOSFET on GeOI for advanced technological nodes. The dependence of these parameters have been analyzed with respect to the gate length, showing very good transport properties (μh∼250cm2/V/s, ION=436μA/μm for LG=105nm), and OFF current densities comparable or better than those reported in the literature.

Characterization of bonded silicon-on-aluminum-nitride wafers with RBS, TEM and HRXRD techniques

Bonded silicon-on-insulator (SOI) materials via the Smart-cut TM (or ion-cut) process attract increasing interests due to their great capability and versatility in fabricating novel virtual substrates. Previously we reported the successful fabrication of silicon-on-aluminum-nitride (SOAN) structure with smart-cut process [C.L. Men, Z. Xu, Z. An, X.Y. Xie, M. Zhang, C.L. Lin, Physica B 324 (2002) 229]. In this work, we characterize the bonded SOAN structure with Rutherford backscattering spectroscopy (RBS), transmission electron microscopy (TEM) together with Kikuchi line diffraction patterns, and high resolution X-ray diffraction (HRXRD) techniques. It is found that, after smart-cut process, the top Si layer preserves a rather good single crystalline quality, while strain is induced in top Si and can be altered in the annealing step. The rotational misalignment during bonding step can be evaluated by Kikuchi line patterns. Our discussions here may be common for all bonded virtual substrates via smart-cut technology.

Microwave Performance of AlGaN/GaN High-Electron-Mobility Transistors on Si/SiO2/Poly-SiC Substrates

The radiofrequency (RF) performance of AlGaN/GaN high-electron-mobility transistors (HEMTs) grown by molecular beam epitaxy (MBE) on Si-on-poly-SiC (SopSiC) substrates formed by the Smart-CutTM process is reported. This provides a low-cost, high-thermal-conductivity substrate for power applications. HEMTs with a 0.5 μm gate length show cutoff frequencies (f T) of 18 to 27 GHz for gate-to-drain distances of 3 to 32 μm and a maximum frequency of oscillation (f max) of 43 to 47 GHz. The f max values are slightly lower than comparable devices on sapphire, SiC or Si alone. This approach looks promising for applications requiring cheap large-area substrates and better thermal management than provided by pure Si substrates alone.

Recent Achievement in the GaN Epitaxy on Silicon and Engineering Substrates

Since the middle of the 90's, many techniques of growing GaN epitaxy have been developed, using either MOCVD or MBE growth methods. Historically, Sapphire and Silicon Carbide have been primarily the substrates used to gorw the GaN Epilayers. The reason was the low mismatch between GaN and these Compounds semiconductors. However each of them has its drawbacks. Poor thermal conductivity for the Sapphire matters as far as the power density going through the device increases. About the SiC, the perfect material after Diamond to dissipate the heat, face significant challenges to increase substrates diameter greater than 3 inches. By going in these directions, the industrialization of the GaN Epitaxy won't be able to increase its capacity to large volume and large diameter and will remain as a technology for a niche market. Picogiga has worked on the development of alternative approach which assures the capability to increase production easily. Obviously because its maturity, its availability, Silicon substrates must be our best choice material. Secondly thank to the Smart-CutTM process developed by Soitec, Picogiga has transferred this new technique to the Compound Semiconductor. This technique has opened new ways to optimize the GaN technology, to improve performances, to remain cost competitive.

Al Ga N ∕ Ga N high electron mobility transistors on Si∕SiO2/poly-SiC substrates

Al Ga N ∕ Ga N high electron mobility transistors were grown by molecular beam epitaxy on Si on poly-SiC substrates formed by the Smart Cut™ process. The Smart Cut™ approach is an alternative solution to provide both a high resistivity and an excellent thermal conductivity template needed for power applications. Although the structure has not been optimized, devices with 0.7μm gate length show breakdown voltage of &amp;gt;250V, fT of 18GHz, and fmax of 65GHz.

Investigation of silicon-on-insulator (SOI) substrate preparation using the smart-cutTM process

A promising technology called smart-cutTM process based on the hydrogen ion implantation and wafer bonding was proposed to prepare the SOI wafers. In this work, the ion implanter applied in the VLSI fabrication process, namely AMAT 9500×R, was used to implant the hydrogen ions, which were extracted from a PH3 plasma gas. The depth profile of the ion-implanted hydrogen in silicon wafers was measured by TOF-SIMS, and the result are in good agreement with the simulation result from SRIM simulator. Experimental results demonstrate that the SOI layer can be successfully transferred from the hydrogen-implanted wafer onto the handle wafer, and the thickness of the transferred SOI layer is approximate to the average projected range of hydrogen ions obtained from TOF-SIMS data. However, some bubble-like non-transferred regions appear on the surface of SOI wafers and two techniques have been reported, which may be effectively used to eliminate this phenomenon. The surface roughness was analyzed by AFM and indicated that a follow-up chemical mechanical polishing was necessary to improve the surface roughness of the SOI layer after the smart-cutTM process.

Strain characterization of strained silicon on insulator wafers

We show that it is possible to combine both silicon on insulator and strained silicon structures, which are usually considered as independent solutions to improve the performance of silicon-based CMOS transistors. Using Raman spectrometry and electron microscopy, we studied one kind of virtual Si 1− x Ge x substrate produced by reduced pressure-chemical vapor deposition, and the strained silicon thin film grown on top of this substrate. These structures are transferred on a silicon substrate using the SMART CUT TM process to form strained silicon on insulator wafers (SSOI). The main result is that the overlayers in the silicon on insulator structures keep the same stress than they had before transfer. The stress, measured in SSOI wafers with Si layers as thin as 10 nm, is not affected by high temperature annealing up to 1000 °C.

Layer Splitting by H-Ion Implantation in Silicon: Lower Limit on Layer Thickness?

AbstractThe Smart-Cut™ process and its variants involve H and/or He ion implantation and annealing to neatly exfoliate a layer of material as thin as the ion range. At low ion energy, as required for further miniaturisation, several effects may inhibit the process. We implanted undoped Si (100), (110) and (111) with 5 keV H or D ions at doses below (3–4×1016/cm2) or above (5.5×1016/cm2) the critical dose for blistering. The samples were either isochronally annealed for 1h or 2h in three steps at 500, 550 and 600°C, or subjected to thermal desorption spectroscopy (TDS) with linear ramps of 7.5 K/min up to 500, 550 or 600°C. The surface morphology was observed at each step by scanning electron or atomic force microscopy. Below the critical blistering dose, TDS only shows a broad high temperature (∼525°C) peak, while above that dose, a low temperature peak (∼360°C) also appears, though weakly in the case of (110) samples. The exfoliated area (as % of total surface) increases with temperature, and also varies with wafer orientation, being minimum for (110) samples and maximum for (111) samples. This orientation effect is much more pronounced for H-implants than for D-implants. All these trends indicate that ion channelling leads to an inhibition of exfoliation.