Small Input Capacitance Research Articles

Optimal Dynamic and Steady-State Performance of PV-Interfaced Converters Using Adaptive Observers

The voltage regulation of a grid-tied PV system is constantly perturbed for the maximum power point tracking (MPPT), the transients of which determine the dynamic MPPT efficiency. Meanwhile, the PV-link voltage ripple coupled from the DC to single-phase AC power conversion adversely affects the static MPPT efficiency. Thus, optimal dynamic and steady-state performance is necessary to maximize the solar energy harvest. This brief proposes a novel adaptive mechanism preserving the advantages of two observers: the classical extended state observer and reduced-order generalized proportional integral observer. Simulation and experimental results prove the enhanced performance regarding the overshoot-free fast transient response and steady state against disturbances, even with small input capacitance. Meanwhile, the observer switching happens seamlessly through the proposed mechanism, which is confirmed analytically and experimentally.

A 6-Bit 20 GS/s Time-Interleaved Two-Step Flash ADC in 40 nm CMOS

A 6-bit 20 GS/s 16-channel time-interleaved (TI) analog-to-digital converter (ADC) using a two-step flash ADC with a sample-and-hold (S/H) sharing technique and a gain-boosted voltage-to-time converter (VTC) is presented for high-speed wireline communication systems. By sharing one S/H between coarse and fine stages in the two-step flash ADC, the input bandwidth as well as area and power efficiency can be improved without a gain error between coarse and fine ADCs. Thanks to an eight-time interpolation using the gain-boosted VTC, the fine ADC has a small gate capacitance without a speed penalty, even in a small input voltage range. A prototype ADC implemented in a 40 nm CMOS process occupies a 0.1 mm2 active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset and gain calibrations were 0.45 and 0.39 least significant bit (LSB), respectively. With a 9.042 GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) were 30.12 and 40.23 dB, respectively. The small input capacitance of the sub-ADC enables a power-efficient track-and-hold amplifier (THA), resulting in a power consumption of 56.2 mW under a supply voltage of 0.9 V. The prototype ADC achieves a figure of merit (FoM) of 107.4 fJ/conversion-step at 20 GS/s.

A 16-nW-57-dBm Sensitivity Wakeup Receiver Using MEMS-Based Matching Network

This letter presents a nanowatt-level detector-first wakeup receiver using microelectromechanical system (MEMS)-based matching network (MN). The aluminum nitride (AlN) piezoelectric MEMS resonator is utilized to implement the impedance MN for high passive gain to improve the receiver sensitivity. The high- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Q$ </tex-math></inline-formula> MEMS-based MN also greatly improves the receiver’s out-of-band interference rejection. Gate-biased envelope detector (ED) with small input capacitance is used for RF-to-baseband direct conversion. The wakeup receiver is implemented in a 180-nm CMOS process. It obtains −57-dBm sensitivity with 1-kbps ON-OFF keying (OOK) data rate at 789 MHz while consuming only 16-nW power consumption.

An 8-Bit 10-GS/s 16× Interpolation-Based Time-Domain ADC With &lt;1.5-ps Uncalibrated Quantization Steps

This article presents an 8-bit time-domain analog-to-digital converter (ADC) that achieves 10 GS/s by aggregating only four time-interleaved channels. It also experiences less than 3.0-dB signal-to-noise and distortion ratio (SNDR) drop at an 18-GHz input frequency from a dc input due to its small input capacitance and inherent voltage-to-time converter (VTC)-based sub-channel buffer. A 16 $\times $ time-interpolation-based time-to-digital converter (TDC) resolves in two steps while allowing both the inter-stage gain and the quantization step to be free from calibration over process, supply voltage, and temperature (PVT) variations. Furthermore, through a timing-extended residue transfer scheme, the metastability error rate is suppressed to $^{-8}$ . Fabricated in a 65-nm CMOS process, the prototype ADC achieves a 40.1-dB SNDR for a Nyquist input signal at 10 GS/s while consuming 50.8 mW from a 1.0-V power supply, yielding a Walden figure-of-merit of 61.5 fJ/conversion-step.

A 624 V 5 A All‐GaN Integrated Cascode for Power‐Switching Applications

An all‐GaN integrated cascode device with an output current of 5 A, threshold voltage of +0.65 V and breakdown voltage of 624 V is demonstrated. Compared with the commercial 600 V hybrid GaN plus Si cascode device (TPH3202), the integrated cascode exhibits a significantly reduced delay time when switched at 200 V and 2.7 A. This is attributed to the absence of a Si metal–oxide–semiconductor field‐effect transistor (MOSFET) driver, leading to a much smaller input capacitance as indicated by the high voltage capacitance measurements. In addition, the integrated cascode device shows a reduced ringing effect due to monolithic integration. When compared with commercial 600 V standalone GaN devices (GS66502B and GS‐065‐004), a reduced Miller effect is observed for the integrated cascode when switched under low gate‐driving current conditions. The results demonstrate the advantages of the cascode device to switch with low gate‐driving current using cheaper, faster, and more efficient gate drivers.

A Power Ripple Compensator for DC Nanogrids via a Solid-State Converter

This paper presents a method for improving the reliability of DC nanogrids by decreasing the input capacitance requirement. The nanogrid DC bus capacitance requirement is reduced by utilizing the zero-sequence operation mode of the solid state converter (SSC). This SSC is often considered as the main DC nanogrid energy control unit that is linking the nanogrid with the main utility AC grid and managing the nanogrid elements. The proposed method injects a zero-sequence voltage in the SSC AC filter capacitors to compensate the low frequency power ripples that are imposed on the DC bus. The proposed method compensates power ripple due to non-linear loads, linear loads, distorted grids, and load variations. Moreover, the compensation method does not require additional components that are commonly used with the existing power ripple compensators. Furthermore, practical considerations of the proposed control are discussed in the paper regarding stabilization of the nanogrid in case of lack of critical damping. The analysis and results demonstrated that a 50 μF total capacitance is sufficient at the DC bus for 500V/5kW DC nanogrid to achieve negligible DC bus voltage ripple. Thereby, with such small DC nanogrid input capacitance, the DC link capacitor can be a film type capacitor to enhance the reliability of the nanogrid.

Nanoscale FET-Based Transduction toward Sensitive Extended-Gate Biosensors.

Owing to their simple and low-cost architecture, extended-gate biosensors based on the combination of a disposable sensing part and a reusable transducer have been widely utilized for the label-free electrical detection of chemical and biological species. Previous studies have demonstrated that sensitive and selective detection of ions and biomolecules can be achieved by controlled modification of the sensing part with an ion-selective membrane and receptors of interest. However, no systematic studies have been performed on the impact of the transducer on sensing performance. In this paper, we introduce the concept of a nanoscale field-effect transistor (FET) as a reusable and sensitive transducer for extended-gate biosensors. The capacitive effect from the external sensing part can degrade the sensing performance, but the nanoscale FET can reduce this effect. The nanoscale FET with a gate-all-around (GAA) structure exhibits a higher pH sensitivity than a commercially available FET, which is widely used in conventional extended-gate biosensors. A sensitivity reduction is observed for the commercial FET, whereas the pH sensitivity is insensitive to the area of the sensing region in the nanoscale FET, thus allowing the scaling of the detection area. Our analysis based on a capacitive model suggests that the high pH sensitivity in the compact sensing area originates from the small input capacitance of the nanoscale FET transducer. Moreover, a decrease in the nanowire width of the GAA FET leads to an improvement in the pH sensitivity. The extended-gate approach with the nanoscale FET-based transduction can pave the way for a highly sensitive analysis of chemical and biological species with a small sample volume.

Flicker-Free Single-Switch Quadratic Boost LED Driver Compatible With Electronic Transformers

MR16 lighting system with a high-frequency step-down electronic transformer is widely used in commercial lighting. In this paper, a single-switch quadratic boost light emitting diode (LED) driver compatible with electronic transformers for the MR16 lighting system is proposed and analyzed. It combines a prestage boost power factor correction (PFC) converter and a second-stage boost dc–dc converter with a single switch. The effect of the dc link voltage ripple of the prestage boost PFC converter on the output of the second-stage boost dc–dc converter is eliminated by a fast voltage mode control loop of a second-stage circuit. Therefore, flicker-free low ripple LED current is achieved. With a small dc link voltage ripple of prestage, the turn- on time of the active switch is almost constant in a half-line cycle. Therefore, PFC can be achieved with inductor current of prestage operating in a discontinuous conduction mode. With small input capacitance, the proposed LED driver presents a good compatibility performance with different kinds of electronic transformers. Furthermore, the proposed LED driver needs only one active switch and one control loop, which makes circuit volume small and low cost. Finally, a 4 W LED driver for a small-size MR16 lighting system is provided to verify the studied results.

A 400-MS/s 10-b 2-b/Step SAR ADC With 52-dB SNDR and 5.61-mW Power Dissipation in 65-nm CMOS

We present a single-channel 10-b 400-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) embodying a proposed 2-b/step conversion scheme with single reference voltage for the IEEE 802.11ac. By means of the said scheme, the proposed ADC requires only three capacitor arrays instead of at least four capacitor arrays in other capacitor digital-to-analog converter-based 2-b/step SAR ADCs. The proposed ADC features a small input capacitance loading, thereby alleviating the driving requirement of the power-hungry input buffer in the IEEE 802.11ac system; and features a symmetrical architecture with highly matched interconnections. In addition, the proposed ADC embodies a proposed high-speed dynamic comparator with kickback noise cancelation and high-speed successive approximation (SA) control logic for high conversion rate and resolution. The proposed ADC prototype fabricated in 65-nm CMOS process achieves signal-to-noise-and-distortion-ratio >52 dB across 200-MHz Nyquist bandwidth, while dissipating 5.61-mW power. The ADC prototype, when benchmarked with state-of-the-art 2-b/step SAR ADCs, features a highly competitive figure-of-merit, i.e., 43 fJ/conv.step.

A 50 mV Fully-Integrated Self-Startup Circuit for Thermal Energy Harvesting

A fully-integrated self-startup circuit with ultra-low voltage for thermal energy harvesting is presented in this paper. The converter is composed of an enhanced swing LC oscillator and a charge pump with decreased equivalent input capacitance. The LC oscillator has ultra-low input voltage and high output voltage swing, and the charge pump has a fast charging speed and small equivalent input capacitance. This circuit is designed with 0.18[Formula: see text][Formula: see text]m standard CMOS process. The simulation results show that the output voltage is in the range of 0.14[Formula: see text]V and 2.97[Formula: see text]V when the input voltage is changed from 50[Formula: see text]mV to 150[Formula: see text]mV. The output voltage could reach 2.87[Formula: see text]V at the input voltage of 150[Formula: see text]mV and the load of 1[Formula: see text]M[Formula: see text]. The maximum efficiency is in the range of 10.0% and 14.8% when the input voltage is changed from 0.2[Formula: see text]V to 0.4[Formula: see text]V. The circuit is suitable for thermoelectric energy harvesting to start with ultra-low input voltage.

A 220-MS/s 9-Bit 2X Time-Interleaved SAR ADC With a 133-fF Input Capacitance and a FOM of 37 fJ/conv in 65-nm CMOS

This brief presents a 9-bit 2X time-interleaved successive approximation (SAR) analog-to-digital converter (ADC) for high-speed applications. The proposed ADC fabricated in TSMC's 65-nm general-purpose process occupies an area of 0.0338 mm 2 and consists of two time-interleaved channels, each operating at 110 MS/s. The sampling capacitor is separated from the capacitive DAC array by performing the input and DAC reference subtraction in the current domain rather than as done traditionally in the charge domain. This allows for an extremely small input capacitance of 133 fF. The measured ADC SFDR is 57 dB and the measured ENOB is 7.55 bits at Nyquist rate while using 1.55-mW power from a 1-V supply.

Efficient Broadband Current-Mode Adder- Quantizer Design for Continuous-Time Sigma–Delta Modulators

A 3-bit current-mode flash quantizer with current summing stage in a commercial 90-nm CMOS technology is presented. The topology is intended for low-power feed-forward continuous-time sigma–delta modulators. Current summation is realized using a common-gate structure. Replicas of the input signal current are compared with the reference currents through high-impedance nodes that ease the signal quantization. The comparison stage employs reset switches to enable fast comparisons. The proposed approach involves zero crossing comparators, and it employs current references instead of voltage references that demand a power-hungry resistive ladder. Results show that the proposed current-mode approach is faster than the conventional voltage-mode flash approach, and it requires a smaller input capacitance while consuming 53% less power. A 3-bit prototype design has a measured effective number of bits over 2.6 bits up to 2-GHz clock frequency with 10-MHz full-scale input signal. At 1.48-GHz clock frequency, the static differential nonlinearity (DNL) and integral nonlinearity (INL) errors are within −0.206 least significant bit (LSB) and 0.206 LSB, respectively. The proposed current-mode flash analog-to-digital converter (ADC) core dissipates 3.34-mW analog power from a 1.2 V supply while operating at 1.48 GHz. The core area of the ADC including the biasing circuitry is 0.0276 $\mathrm{mm}^{\mathrm {\mathbf {2}}}$ .

Algorithmic ADC operating with a single reference voltage for PLL-based chemical sensing applications

This paper deals with the design of an algorithmic switched-capacitor analog-to-digital converter (ADC), operating with a single reference voltage, a single-ended amplifier, a single-ended comparator, and presenting a small input capacitance. The ADC requires two clock phases per conversion bit and N clock cycles to resolve the N-bits. The ADC achieves a measured peak signal-to-noise-ratio (SNR) of 49.9 dB and a peak signal-to-noise-and-distortion-ratio (SNDR) of 46.7 dB at Pin = ?6dBFS with a sampling rate of 0.25 MS/s. The measured differential-non-linearity and integral-non-linearity are within +0.6/?0.5 and +0.2/?0.5 LSB, respectively. The ADC power consumption is 300 μW and it is implemented in 90 nm CMOS technology with a single power supply of 1.2 V. The ADC saves power at system-level by requiring only a single reference voltage. At system level, this solution is therefore not only robust but competitive as well.

마이크로 전력의 축차근사형 아날로그-디지털 변환기를 위한 시간 도메인 비교기

본 논문에서는 저전압 고해상도 축차근사형 아날로그-디지털 변환기를 위한 시간-도메인 비교기를 제안한다. 제안하는 시간-도메인 비교기는 클럭 피드-스루 보상회로를 포함한 전압제어지연 변환기, 시간 증폭기, 그리고 바이너리 위상 검출기로 구성된다. 제안하는 시간-도메인 비교기는 작은 입력 부하 캐패시턴스를 가지며, 클럭 피드-스루 노이즈를 보상한다. 시간-도메인 비교기의 특성을 분석하기 위해 다른 시간-도메인 비교기를 가지는 두 개의 1V 10-bit 200-kS/s 축차근사형 아날로그-디지털 변환기가 0.18-<TEX>${\mu}m$</TEX> 1-poly 6-metal CMOS 공정에서 구현된다. 11.1kHz의 아날로그 입력신호에 대해 측정된 SNDR은 56.27 dB이며, 제안된 시간-도메인 비교기의 클럭 피드-스루 보상회로와 시간 증폭기가 약 6 dB의 SNDR을 향상시킨다. 구현된 10-bit 200-kS/s 축차근사형 아날로그-디지털 변환기의 전력소모와 면적은 각각 10.39 <TEX>${\mu}W$</TEX>와 0.126 mm2 이다. In this paper, a time-domain comparator is proposed for a successive approximation (SA) analog-to-digital converter (ADC) with a low power and high resolution. The proposed time-domain comparator consists of a voltage-controlled delay converter with a clock feed-through compensation circuit, a time amplifier, and binary phase detector. It has a small input capacitance and compensates the clock feed-through noise. To analyze the performance of the proposed time-domain comparator, two 1V 10-bit 200-kS/s SA ADCs with a different time-domain comparator are implemented by using 0.18-<TEX>${\mu}m$</TEX> 1-poly 6-metal CMOS process. The measured SNDR of the implemented SA ADC is 56.27 dB for the analog input signal of 11.1 kHz, and the clock feed-through compensation circuit and time amplifier of the proposed time-domain comparator enhance the SNDR of about 6 dB. The power consumption and area of the implemented SA ADC are 10.39 <TEX>${\mu}W$</TEX> and 0.126 mm2, respectively.

Design and Analysis of a $W$-band Divide-by-Three Injection-Locked Frequency Divider Using Second Harmonic Enhancement Technique

In this paper, we present design and analysis of a <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> -band divide-by-three injection-locked frequency divider (ILFD) in 90 nm CMOS process. Based on the proposed topology, the locking range can be enhanced without additional dc power consumption due to the boost of the second harmonic in the ILFD, and the small input capacitance is more feasible for <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">W</i> -Band PLL integration. The locking range of the ILFD is investigated to obtain a theoretical model. From the analysis, the locking range is proportional to the device size of the injectors and the amplitude of the injection signal. In addition, the locking range can be enhanced with a proper gate dc bias of the injectors. The measured locking range of the proposed ILFD is from 91.4 to 93.5 GHz without varactor tuning, and the output power is higher than -15 dBm. The core dc power consumption is 1.5 mW with a supply voltage of 0.7 V.

A DCVSL Delay Cell for Fast Low Power Frequency Synthesis Applications

In this paper, a low-cost, power efficient and fast Differential Cascode Voltage-Switch-Logic (DCVSL) based delay cell (named DCVSL-R) is proposed. We use the DCVSL-R cell to implement high frequency and power-critical delay cells and flip-flops of ring oscillators and frequency dividers. When compared to TSPC, DCVSL circuits offer small input and clock capacitance and a symmetric differential loading for previous RF stages. When compared to CML, they offer low transistor count, no headroom limitation, rail-to-rail swing and no static current consumption. However, DCVSL circuits suffer from a large low-to-high propagation delay, which limits their speed and results in asymmetrical output waveforms. The proposed DCVSL-R circuit embodies the benefits of DCVSL while reducing the total propagation delay, achieving faster operation. DCVSL-R also generates symmetrical output waveforms which are critical for differential circuits. Another contribution of this work is a closed-form delay model that predicts the speed of DCVSL circuits with 8% worst case accuracy. We implement two ring-oscillator-based VCOs in 0.13 μm technology with DCVSL and DCVSL-R delay cells. Measurements show that the proposed DCVSL-R based VCO consumes 30% less power than the DCVSL VCO for the same oscillation frequency (2.4 GHz) and same phase noise (-113 dBc/Hz at 10 MHz). DCVSL-R circuits are also used to implement the high frequency dual modulus prescaler (DMP) of a 2.4 GHz frequency synthesizer in 0.18 μm technology. The DMP consumes only 0.8 mW at 2.48 GHz, a 40% reduction in power when compared to other reported DMPs with similar division ratios and operating frequencies. The RF buffer that drives the DMP consumes only 0.27 mW, demonstrating the lowest combined DMP and buffer power consumption among similar synthesizers in literature.

A system for characterization of DEPFET silicon pixel matrices and test beam results

The DEPFET pixel detector offers first stage in-pixel amplification by incorporating a field effect transistor in the high resistivity silicon substrate. In this concept, a very small input capacitance can be realized thus allowing for low noise measurements. This makes DEPFET sensors a favorable technology for tracking in particle physics. Therefore a system with a DEPFET pixel matrix was developed to test DEPFET performance for an application as a vertex detector for the Belle II experiment. The system features a current based, row-wise readout of a DEPFET pixel matrix with a designated readout chip, steering chips for matrix control, a FPGA based data acquisition board, and a dedicated software package. The system was successfully operated in both test beam and lab environment. In 2009 new DEPFET matrices have been characterized in a 120 GeV pion beam at the CERN SPS. The current status of the DEPFET system and test beam results are presented.

A 9-bit 100-MS/s 1.46-mW Tri-Level SAR ADC in 65 nm CMOS

A 9-bit 100-MS/s successive approximation register (SAR) ADC with low power and small area has been implemented in 65-nm CMOS technology. A tri-level charge redistribution technique is proposed to reduce DAC switching energy and settling time. By connecting bottom plates of differential capacitor arrays for charge sharing, extra reference voltage is avoided. Two reference voltages charging and discharging the capacitors are chosen to be supply voltage and ground in order to save energy and achieve a rail-to-rail input range. Split capacitor arrays with mismatch calibration are implemented for small area and small input capacitance without linearity degradation. The ADC achieves a peak SNDR of 53.1 dB and consumes 1.46 mW from a 1.2-V supply, resulting in a figure of merit (FOM) of 39 fJ/conversion-step. The total active area is 0.012 mm2 and the input capacitance is 180 fF.

A sub-2.0 V BiCMOS logic circuit with a BiCMOS charge pump

A BiCMOS logic circuit with very small input capacitance has been developed, which operates at low supply voltages. A High-beta BiCMOS (H/spl beta/-BiCMOS) gate circuit which fully utilizes the bipolar transistor features achieves 10 times the speed of a CMOS gate circuit with the same input capacitance and operating at 3.3 V supply voltage. In order to lower the minimum supply voltage of H/spl beta/-BiCMOS, a BiCMOS circuit configuration using a charge pump to pull up the output high level of the BiCMOS gate circuit is proposed. By introducing a BiCMOS charge pump, H/spl beta/-BiCMOS achieves very high speed operation at sub-2.0 V supply voltage. It has also been demonstrated that only a very small number of charge pump circuits are required to drive a large number of H/spl beta/-BiCMOS gate circuits.

A 10-b 300-MHz interpolated-parallel A/D converter

A monolithic 10-b A/D converter that realized a maximum conversion frequency of 300 MHz is described. Through the development of the interpolated-parallel scheme, the severe requirement for the transistor V/sub be/ matching can be alleviated drastically, which improves differential nonlinearity (DNL) significantly to within +or-0.4 LSB. Furthermore, an extremely small input capacitance of 8 pF can be attained, which translates into better dynamic performance such as SNR of 56 dB and THD of -59 dB for an input frequency of 10 MHz. Additionally, the folded differential logic circuit has been developed to reduce the number of elements, power dissipation, and die area drastically. Consequently, the A/D converter has been implemented as a 9.0-mm*4.2-mm chip integrating 36 K elements, which consumes 4.0 W using a 1.0- mu m-rule, 25-GHz f/sub t/, double-polysilicon self-aligned bipolar technology. >