Single-precision Floating-point Numbers Research Articles

Numerical Solution of Linear Second-Kind Convolution Volterra Integral Equations Using the First-Order Recursive Filters Method

A new numerical method for solving Volterra linear convolution integral equations (CVIEs) of the second kind is presented in this work. This new approach uses first-order infinite impulse response digital filters method (IIRFM). Three convolutive kernels were analyzed, the unit kernel and two singular kernels: the logarithmic and generalized Abel kernels. The IIRFM is based on the combined use of the Laplace transformation, a first-order decomposition, and a bilinear transformation. This approach often leads to simple analytical expressions of the approximate solutions, enabling efficient numerical calculation, even using single-precision floating-point numbers. When compared with the method of homotopic perturbations with Laplace transformation (HPM-L), the IIRFM approach does not present, in linear cases, the convergence difficulties inherent to iterative approaches. Unlike most solution methods based on the Laplace transform, the IIRFM has the dual advantage of not requiring the calculation of the Laplace transform of the source function, and of not requiring the systematic calculation of inverse Laplace transforms.

Enhancing computational efficiency in 3-D seismic modelling with half-precision floating-point numbers based on the curvilinear grid finite-difference method

SUMMARY Large-scale and high-resolution seismic modelling are very significant to simulating seismic waves, evaluating earthquake hazards and advancing exploration seismology. However, achieving high-resolution seismic modelling requires substantial computing and storage resources, resulting in a considerable computational cost. To enhance computational efficiency and performance, recent heterogeneous computing platforms, such as Nvidia Graphics Processing Units (GPUs), natively support half-precision floating-point numbers (FP16). FP16 operations can provide faster calculation speed, lower storage requirements and greater performance enhancement over single-precision floating-point numbers (FP32), thus providing significant benefits for seismic modelling. Nevertheless, the inherent limitation of fewer 16-bit representations in FP16 may lead to severe numerical overflow, underflow and floating-point errors during computation. In this study, to ensure stable wave equation solutions and minimize the floating-point errors, we use a scaling strategy to adjust the computation of FP16 arithmetic operations. For optimal GPU floating-point performance, we implement a 2-way single instruction multiple data (SIMD) within the floating-point units (FPUs) of CUDA cores. Moreover, we implement an earthquake simulation solver for FP16 operations based on curvilinear grid finite-difference method (CGFDM) and perform several earthquake simulations. Comparing the results of wavefield data with the standard CGFDM using FP32, the errors introduced by FP16 are minimal, demonstrating excellent consistency with the FP32 results. Performance analysis indicates that FP16 seismic modelling exhibits a remarkable improvement in computational efficiency, achieving a speedup of approximately 1.75 and reducing memory usage by half compared to the FP32 version.

A Hardware Implementation of the PID Algorithm Using Floating-Point Arithmetic

The purpose of the paper is to propose a new implementation of the PID (proportional–integral–derivative) algorithm in digital hardware. The proposed structure is optimized for cost. It follows a serialized, rather than parallel, scheme. It uses only one arithmetic block, performing the multiply-and-add operation. The calculations are carried out in a sequentially cyclic manner. The proposed circuit operates on standard single-precision (32-bit) floating-point numbers. It implements an extended PID formula, containing a non-ideal derivative component, and weighting coefficients, which enable reducing the influence of setpoint changes in the proportional and derivative components. The circuit was implemented in a Cyclone V FPGA (Field-Programmable Gate Array) device from Intel, Santa Clara, CA, USA. The proper operation of the circuit was verified in a simulation. For the specific implementation, which is reported in the paper, the sampling period of 516 ns was obtained, which means that the proposed solution is comparable in terms of speed with other hardware implementations of the PID algorithm operating on single-precision floating-point numbers. However, the presented solution is much more efficient in terms of cost. It uses 1173 LUT (Look-up Table) blocks, 1026 registers, and 1 DSP (Digital Signal Processing) block, i.e., about 30% of logic resources required by comparable solutions.

Rationalized diffraction calculations for high accuracy and high speed with few bits.

Diffraction calculations in few-bit formats, such as single-precision floating-point and fixed-point numbers, are important because they yield faster calculations and lower memory usage. However, these methods suffer from low accuracy owing to the loss of trailing digits. Fresnel diffraction is widely known to prevent the loss of trailing digits. However, it can only be used when the paraxial approximation is valid. In this study, a few-bit diffraction calculation method that achieves high accuracy without using any approximation is proposed. The proposed method is derived only by rationalizing the numerator of conventional formulas. Even for scenarios requiring double-precision floating-point numbers using conventional methods, the proposed method exhibits higher accuracy and faster computation time using single-precision floating-point numbers.

A GPU-based DEM model for the pebble flow study in packed bed: Simulation scheme and validation

This study developed a GPU-based DEM (GPU-DEM) model for the pebble flow in the packed bed. The details of the GPU-DEM scheme have been illustrated. The uniform mesh neighbor-search method, unified memory addressing (UMA), and special boundary conditions were incorporated in the GPU-DEM model. Cases of the direct impact of two identical particles, the angle of repose of particles drained from a lifted hopper, and the circulating hopper to mimic a pebble flow in High-Temperature Gas-cooled Reactor (HTGR) reactors were carried out to systematically verify the applicability, computational efficiency, and accuracy of the GPU-DEM model. Related results, like the unloading speed, porosity, and velocity distribution, obtained by the GPU-DEM model have been validated too. In addition, the effects of single-precision floating-point number computation on GPU were discussed. The results demonstrated that the GPU-DEM can achieve 18– 20 times acceleration while maintaining accuracy, even when single-precision floating-point numbers were used for calculation. Therefore, it is a powerful tool to explore the particle flows in chemical engineering applications.

Uphill resampling for particle filter and its implementation on graphics processing unit

We introduce a new resampling method, named Uphill, that is free from numerical instability and suitable for parallel implementation on graphics processing unit (GPU). Common resampling algorithms such as Systematic suffer from numerical instability when single precision floating point numbers are used. This is due to cumulative summation over the weights of particles when the weights differ widely or the number of particles is large. The Metropolis and Rejection resampling algorithms do not suffer from numerical instability as they only calculate the ratios of weights pairwise rather than perform collective operations over the weights. They are more suitable for the GPU implementation of the particle filter. However, they undergo non-coalesced global memory access patterns which cause their speed deteriorate rapidly as the number of particles gets large. Uphill also does not suffer from numerical instability but, experiences the same non-coalesced global memory access problem with Metropolis and Rejection. We introduce its faster version named Uphill-Fast which eliminates this problem. We make comparisons of Uphill and Uphill-Fast with the Systematic, Metropolis, Metropolis-C2 and Rejection resampling methods with respect to quality and speed. We also compare them on a highly non-linear system. Uphill-Fast runs faster and attains similar quality, in terms of RMSE, in comparison with Metropolis and Rejection when the number of particles is very large. Uphill-Fast runs with roughly same speed as Metropolis-C2 with better variance and MSE when the number of particles is very large.

High-Throughput Low-Latency Pipelined Divider for Single-Precision Floating-Point Numbers

In this brief, we propose a fully pipelined divider for single-precision floating-point numbers based on a universal piecewise linear (PWL) approximation method and a modified Goldschmidt algorithm. The state-of-the-art universal PWL method uses a suitable number of segments and fractional bit widths to meet the requirement of the predefined maximum absolute error. Small multipliers are employed in the modified Goldschmidt algorithm. In the hardware implementation, the multipliers are optimized with the radix-4 and radix-8 booth encoding methods to reduce the number of partial products. In addition, the sum of the partial products and other data are calculated by a compressor and an adder to shorten the critical path. Synthesized results show that the maximum achievable frequency of our design is better than those of the existing methods. In addition, our design shows overwhelming superiority in terms of latency and throughput compared with existing methods.

Reliability analysis ofN-equationsN-unknowns method for the solution of the finite-difference time-domain (FDTD) problems

AbstractFinite-difference time-domain (FDTD) solution of electromagnetic problems at high-frequency (HF) range is a challenging task. This is due to two requirements of accurate geometrical modeling for small objects/antennas and proper modeling of skin-depth effect. Generally, the fine meshes are used to overcome these problems. However, this leads to a large number of time iterations because of the small unit time step. To decrease the computational time,N-equationsN-unknowns (NE-NU) method is developed for multi-frequency sources. Therefore, utilizing wideband nature of the FDTD method, NE-NU method is valuable. However, the reliability analysis of the NE-NU method has not been investigated in the literature. This study is the first numerical application of the NE-NU method that the reliability analysis of the NE-NU method is performed by using condition number calculation and it is validated by time-domain signals of an illustrative numerical example of a HF radar problem. A successful case and a failing case of the NE-NU method are clearly revealed. The effect of using a double-precision floating-point number and a single-precision floating-point number is also discussed. It is proved that a crucial value of the condition number can be found for the reliable NE-NU results.

Speeding up Statistical Tolerance Analysis to Real Time

Statistical tolerance analysis based on Monte Carlo simulation can be applied to obtain a cost-optimized tolerance specification that satisfies both the cost and quality requirements associated with manufacturing. However, this process requires time-consuming computations. We found that an implementation that uses the graphics processing unit (GPU) for vector-chain-based statistical tolerance analysis scales better with increasing sample size than a similar implementation on the central processing unit (CPU). Furthermore, we identified a significant potential for reducing runtime by using array vectorization with NumPy, the proper selection of row- and column- major order, and the use of single precision floating-point numbers for the GPU implementation. In conclusion, we present open source statistical tolerance analysis and statistical tolerance synthesis approaches with Python that can be used to improve existing workflows to real time on regular desktop computers.

Fast Calculation of Cube and Inverse Cube Roots Using a Magic Constant and Its Implementation on Microcontrollers

We develop a bit manipulation technique for single precision floating point numbers which leads to new algorithms for fast computation of the cube root and inverse cube root. It uses the modified iterative Newton–Raphson method (the first order of convergence) and Householder method (the second order of convergence) to increase the accuracy of the results. The proposed algorithms demonstrate high efficiency and reduce error several times in the first iteration in comparison with known algorithms. After two iterations 22.84 correct bits were obtained for single precision. Experimental tests showed that our novel algorithm is faster and more accurate than library functions for microcontrollers.

Low Complexity VLSI Architecture Design Methodology for Wigner Ville Distribution

In this brief, we propose a low complexity VLSI architecture design Methodology for Wigner Ville Distribution (WVD) computation. The proposed methodology performs both auto and cross WVD computations using only the half number of Fast Fourier transform (FFT) computations as opposed to the state of the art methodologies. The FPGA implementation for proposed methodology was performed for 16 bit fixed point and 32 bit single precision floating point numbers on the Xilinx Virtex-7 FPGA (XC7vx485tffg). The proposed methodology saves 49% energy consumption when compared with the state of the art methodology. However it can be noted that the proposed methodology is independent of the VLSI implementation platform and technology node.

GH CORDIC-Based Architecture for Computing $N$ th Root of Single-Precision Floating-Point Number

This article presents hardware implementation for computing arbitrary roots of a single-precision floating-point number. The proposed architecture is based on Generalized Hyperbolic COordinate Rotation Digital Computer (GH CORDIC) algorithm. Benefiting from the wide range of floating-point numbers, our design is able to compute the ${N}$ th root ( ${N} {\ge 2}$ ) of a single-precision floating-point number. After implementation, a series of tests have been carried out, including accuracy, power consumption, performance comparison, and so on. Simulation results indicate that our proposed method is capable of calculating the ${N}$ th root of a positive single-precision floating-point number with a relative error of 10−7 approximately and promises an error-flatten performance. Synthesized results from a design compiler under TSMC-40-nm CMOS technology show that our design can achieve the highest frequency of 2.38 GHz with the area consumption of ${{{140894.44 ~\mu \text {m}}}}^{2}$ and power consumption of 86.9573 mW.

A Modification of the Fast Inverse Square Root Algorithm

We present a new algorithm for the approximate evaluation of the inverse square root for single-precision floating-point numbers. This is a modification of the famous fast inverse square root code. We use the same “magic constant” to compute the seed solution, but then, we apply Newton–Raphson corrections with modified coefficients. As compared to the original fast inverse square root code, the new algorithm is two-times more accurate in the case of one Newton–Raphson correction and almost seven-times more accurate in the case of two corrections. We discuss relative errors within our analytical approach and perform numerical tests of our algorithm for all numbers of the type float.

Noise Reduction Using Modified Wiener Filter in Digital Hearing Aid for Speech Signal Enhancement

Abstract Speech signals are usually affected by noises during the communication process. For suppressing the noise signal that is combined with the speech signal, a Wiener filter is adapted in digital hearing aids. Weiner filter plays an important role in noise suppression and enhancement by estimating the relation between the power spectra of the noise-affected speech signal and the noise signal. Power consumption and the hardware requirement are the important problems in adapting Weiner filter for major communication systems. In this work, we implemented an efficient Wiener filter and applied it for noise suppression along with a real-valued fast Fourier transform (FFT)/real-valued inverse FFT processor in digital hearing aids. The pipelined process was adopted for increasing the performance of the system. The proposed Wiener filter was designed to remove the iteration problems in the conventional Wiener filter. The division operation was replaced by an efficient inverse and multiplication operation in the proposed design. A modified architecture for matrix inversion with low computation complexity was implemented. The complete design computation was based on IEEE-754 standard single-precision floating-point numbers. The Wiener filter and the whole system architecture was implemented and designed on a Field Programmable Gate Array platform and simulated to validate the results in Xilinx ISE tools. An efficient reduction in power and area was obtained by adapting the proposed method for speech signal noise degradation. The performance of the proposed design was found to be 50.01% more efficient than that of existing designs.

Agomelatine and other antidepressants and the risk of acute liver injury (ALI), a post authorisation safety study (PASS) in four European countries

We present a mathematical analysis of transformations used in fast calculation of inverse square root for single-precision floating-point numbers. Optimal values of the so called magic constants are derived in a systematic way, minimizing either relative or absolute errors. We show that the value of the magic constant can depend on the number of Newton–Raphson iterations. We present results for one and two iterations.

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

In floating point arithmetic operations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques . Further , the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator.

Resource Efficient Single Precision Floating Point Multiplier Using Karatsuba Algorithm

In floating point arithmetic operations, multiplication is the most required operation for many signal processing and scientific applications. 24-bit length mantissa multiplication is involved to obtain the floating point multiplication final result for two given single precision floating point numbers. This mantissa multiplication plays the major role in the performance evaluation in respect of occupied area and propagation delay. This paper presents the design and analysis of single precision floating point multiplication using karatsuba algorithm with vedic multiplier with the considering of modified 2x1 multiplexers and modified 4:2 compressors in order to overcome the drawbacks in the existing techniques . Further , the performance analysis of single precision floating point multiplier is analyzed in terms of area and delay using Karatsuba Algorithm with different existing techniques such as 4x1 multiplexers and 3:2 compressors and modified techniques such as 2x1 multiplexers, 4:2 compressors. From the simulation results, it is observed that single precision floating point multiplication with karatsuba algorithm using modified 4:2 compressor with XOR-MUX logic provides better performance with efficient usage of resources such as area and delay than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx ISE Simulator.

OPTIMAL UNIFORM QUANTIZATION OF PARAMETERS OF CONVOLUTIONAL NEURAL NETWORKS

State of the art convolutional neural networks provide high accuracy in solving a wide range of problems. Usually it is achieved by a significant increasing their computational complexity and the representation of the network parameters in single-precision floating point numbers. However, due to the limited resources, the application of networks in embedded systems and mobile applications in real time is problematic. One of the methods to solve this problem is to reduce the bit depth of data and use integer arithmetic. For this purpose, the network parameters are quantized. Performing quantization, it is necessary to ensure a minimum loss of recognition accuracy. The article proposes to use an optimal uniform quantizer with an adaptive step. The quantizer step depends on the distribution function of the quantized parameters. It reduces the effect of the quantization error on the recognition accuracy. There are also described approaches to improving the quality of quantization. The proposed quantization method is estimated on the CIFAR-10 database. It is shown that the optimal uniform quantizer for CIFAR-10 database with 8-bit representation of network parameters allows to achieve the accuracy of the initial trained network.

Interval stabbing on the Automata Processor

The Automata Processor (AP) was designed for string-pattern matching. In this paper, we showcase its use to execute integer and floating-point comparisons and apply the same to accelerate interval stabbing queries. An interval stabbing query determines which of the intervals in a set overlap a query point. Such queries are often used in computational geometry, pattern matching, database management systems, and geographic information systems. The check for each interval is programmed as a single automaton and multiple automata are executed in parallel to provide significant performance gains. While handling 32-bit integers or single-precision floating-point numbers, up to 2.75 trillion comparisons can be executed per second, whereas 0.79 trillion comparisons per second can be completed for 64-bit integers or double-precision floating-point numbers. Additionally, our solution leaves the intervals in the set unordered allowing addition or deletion of an interval in constant time. This is not possible for contemporary solutions wherein the intervals are ordered, making update of intervals complex. Our automata designs are modular allowing them to become constituent parts of larger automata, where the numerical comparisons are part of the overall pattern matching operation. We have validated the designs on the hardware, and the routines to generate the necessary automata and execute them on the AP will be made available as software libraries shortly.

Prototyping of Nonlinear Time-Stepped Finite Element Simulation for Linear Induction Machines on Parallel Reconfigurable Hardware

The finite element method (FEM) is widely used for accurate design and analysis of electric machines; however, it suffers from long execution time. In this paper, for the first time hardware acceleration of two-dimensional FEM for a single-sided linear induction motor on the field programmable gate array (FPGA) is proposed. The nonlinearity of the iron core as well as the movement are taken into consideration. A new sparse solver is proposed based on left-looking Gilbert–Peierls algorithm for the system of linear equations of FEM that need to be solved in different iterations and time steps. Implementation of the model is performed in a massively paralleled and deeply pipelined hardware architecture using VHDL coding with single precision floating-point number representation. The proposed emulation was performed at various time steps resulting in significant average speedup of 9.73 times in comparison with JMAG-Designer as a commercial finite element software, and the overall hardware latency of each time step for the emulation was 49.2 ms in average with minimum achievable FPGA clock of 5.59 ns.