Single-phase Phase-locked Loop Research Articles

Hybrid Feedforward Single-Phase Phase-Locked Loop for Accurate Measurement Offset Rejection and Frequency–Ramp Tracking

Hybrid Feedforward Single-Phase Phase-Locked Loop for Accurate Measurement Offset Rejection and Frequency–Ramp Tracking

Advanced Single-Phase PLL-Based Transfer Delay Operators: A Comprehensive Review and Optimal Loop Filter Design

In recent years, several research works have addressed and developed the phase-locked loop (PLL) in single-phase grid-connected converters with different structures and properties. Each has merits and demerits, such as a complex structure, high computational burden, and slow transient response. This paper aims to comprehensively review advanced single-phase PLLs based on transport delay operators to realize signal orthogonality. A deep insight into the PLLs’ small-signal modeling, main characteristics, stability analysis, and loop filter design are provided in this paper. The main advantages and drawbacks are explained for each type of PLL in terms of different performance indexes, such as settling time, estimation error, and ripples in the estimated grid information. This paper also aims to provide optimal tuning and design of the loop filter gains from the large-signal model point of view, including all the nonlinearities, adopting the stochastic optimization method. All simulations are implemented using the MATLAB/Simulink 2018b environment to validate all theoretical analyses of this paper. The sampling and nominal frequencies are set to be 100 kHz and 50 Hz throughout all the simulation studies.

Digitalized Control Algorithm of Bridgeless Totem-Pole PFC with a Simple Control Structure Based on the Phase Angle

Compared to the conventional boost power factor correction (PFC) converter, a totem-pole bridgeless PFC has high efficiency because it does not have an input diode rectifier stage, but a current spike may occur when the polarity of the grid voltage changes. This paper proposes a digital control algorithm for bridgeless totem-pole PFC with a simple control structure based on the phase angle of grid voltage. The proposed algorithm has a PI-based double-loop control structure and performs DC-link voltage and input inductor current control. Rectifying switches operate based on the proposed rectification algorithm using phase angle information calculated through a single-phase phase-locked loop (PLL) to prevent current spikes. The feed-forward duty ratio value is calculated according to the polarity of the grid voltage and added to the double-loop controller to perform appropriate power factor control. The performance and feasibility of the proposed control algorithm are verified through a 3 kW hardware prototype.

Improved Single-phase PLL Based on All-Pass Filter

The detection accuracy of a conventional phase-locked loop for a single phase is affected by the interference of the DC component and harmonic component when the grid has a lot of problems such as harmonic interference and DC offset, and It will be unable to accurately track the grid voltage frequency and phase. The traditional APF-PLL is improved to address this problem. An improved phase-locking algorithm is proposed, combining a CSOGI and a FLL with the conventional single-phase phase-locked loop. The method incorporates CSOGI into the APF-PLL pre-stage to reduce interference from DC and harmonic components, while FLL achieves the frequency tracking of the input signal and improves the adaptivity and dynamic response speed of the phase-locked loop. Through simulation verification, the proposed new phase-locked loop can improve the frequency tracking capability, dynamic performance, and precision of the locking phase of the PLL.

A synchronization technique for single-phase grid applications

The utility grid disturbances like dc offset and harmonic components can severely affect the estimated variables from the phase-locked loop (PLL), resulting in poor performance of the system relying on it. Therefore, there is an emerging need for well-designed PLL algorithms ensuring robust response against different operating conditions. This paper proposes a simple single-phase PLL algorithm with inherent dc offset and specific harmonic orders rejection capability. Utilizing adaptive time-delay fictitious signal generation. A full mathematical model of the proposed PLL has been provided. The proposed PLL is compared with other filter-based single-phase PLLs, to validate its simplicity and excellent performance.

Accurate LTP Model and Stability Analysis of the Second-Order Generalized Integrator-Based Single-Phase Phase-Locked Loop

This article focuses on the modeling and stability analysis of the typical single-phase phase-locked loop (PLL) based on second-order generalized integrator (SOGI). Traditionally, SOGI-based PLL (SOGI-PLL) is linearized as the linear time-invariant (LTI) model for the stability analysis and parameter design. Yet, the PLL has periodical nature due to the periodical variation of the grid voltage. The traditional LTI model for PLL thereby reduces the precision of stability analysis. For addressing this problem, an accurate linear time-periodic (LTP) model of the single-phase SOGI-PLL is proposed in this article. The proposed model can precisely characterize the coupling nature of phase, frequency, and amplitude estimated by SOGI-PLL. A precise stability region of SOGI-PLL, thereby, can be derived from the proposed LTP model. The effectiveness of the proposed LTP model for SOGI-PLL is verified by simulation and experimental tests.

Development of Frequency-Fixed All-Pass Filter-Based Single-Phase Phase-Locked Loop

Phase-locked loops (PLL) are widely used in the synchronization of grid interfaced power converters. One solution is based on orthogonal signal generation (OSG), which requires the grid frequency information for their appropriate operation. This article developed a new solution to achieve the PLL function for single-phase grid interconnection but eradicate additional frequency feedback loops in the traditional architecture of all-pass filter PLL (APF-PLL). Four new topologies are developed along with their small-signal modeling and dynamic analysis. A thorough comparison among them on their dynamic response, steady-state accuracy, implementation, and disturbance rejection capability is carried out. Finally, the best approach of frequency-fixed (FF) APF-PLL is experimentally evaluated with frequency adaptive APF-PLL and FF PLLs belonging to time delay (TD) and second-order generalized integrator (SOGI) families.

DC offset rejection in a frequency-fixed second-order generalized integrator-based phase-locked loop for single-phase grid-connected applications

Fast and accurate monitoring of the phase, amplitude, and frequency of the grid voltage is essential for single-phase grid-connected converters. The presence of DC offset in the grid voltage is detrimental to not only grid synchronization but also the closed-loop stability of the grid-connected converters. In this paper, a new synchronization method to mitigate the effect of DC offset is presented using arbitrarily delayed signal cancelation (ADSC) in a second-order generalized integrator (SOGI) phase-locked loop (PLL). A frequency-fixed SOGI-based PLL (FFSOGI-PLL) is adopted to ensure better stability and to reduce the complexity compared with other SOGI-based PLLs. A small-signal model of the proposed PLL is derived for the systematic design of proportional-integral (PI) controller gains. The effects of frequency variation and ADSC on the proposed PLL are considered, and correction methods are adopted to accurately estimate grid information. The simulation results are presented, along with comparisons to other single-phase PLLs in terms of settling time, peak frequency, and phase error to validate the proposed PLL. The dynamic performance of the proposed PLL is also experimentally validated. Overall, the proposed PLL has the fastest transient response and better dynamic performance than the other PLLs for almost all performance indices, offering an improved solution for precise grid synchronization in single-phase applications.

Enhanced Single-Phase Phase Locked Loop Based on Complex-Coefficient Filter

Complex coefficient filters (CCFs) are widely used for phase-locked loop (PLL) in three-phase power systems, while its usage is largely sparse in the single-phase domain. Single-phase CCF-PLLs so far reported in the literature do not yield satisfactory performances at off-nominal frequency conditions, which is a crucial PLL attribute. Whether they are a suitable filtering technique of choice for single-phase PLL is yet to be formally documented in a methodological way. In this regard, this article derives an enhanced version of the single-phase CCF-PLL (ECCF-PLL), which is able to provide accurate estimation of grid parameters in dynamically changing grid frequency environment. The proposed ECCF-PLL is then numerically and experimentally compared with few other single-phase PLLs to gauge its efficacy and suitability. The test shows the advantage of harmonic robustness from ECCF-PLL, which is specifically useful in a weak grid.

Control system design of a low‐frequency‐switchingsingle‐phase four‐quadrant PWMconverter

This work is focused on the control of low-frequency-switching single-phase four-quadrant pulse width modulation (PWM) converters used in grid-connected modern power electronics applications. The switching frequency is chosen to be lower than that used in industrial applications in order to use the designed control system in high-power applications such as railway electrical traction systems. The control system is designed under three main headings: grid synchronization, input current control, and voltage control, where grid synchronization is achieved by a single-phase phase-locked loop (PLL). The current loop is designed by using a proportional-resonant (PR) controller, and the classical proportional-integral (PI) controller is employed in the voltage control loop. The parameters of the PI controller are determined by using the coefficient diagram method (CDM). The control system is modelled as a discrete-time system to get the response closest to the actual system and to be easily implemented on the TMS320F28335 DSP platform. The performance of designed control system is tested on a 30-kW single-phase PWM converter test set-up, and experimental results show that bidirectional power flow, sinusoidal input current, power factor correction, and constant output voltage are achieved. This study is aimed to be a guide for the designers, from the selection of converter passive elements to controller design and experimental verification.

An Enhanced Discrete-Time Oscillator-Based PLL-Less Estimation of Single-Phase Grid Voltage Parameters

This article presents a robust single-phase phase-locked loop (PLL)-less frequency, phase, and amplitude estimation technique. The proposed scheme, unlike PLL approaches, does not require a rigorous design and tuning process in order to attain a better stability margin. It is important to note that an improved discrete-time oscillator is obtained by involving a comb filter, which helps improve the dc-offset rejection capability and transient response time. Moreover, the notch-filter-like behavior and the introduction of imaginary zeros ensure better harmonic removal ability when compared to a known nonadaptive discrete-time oscillator. The proposed scheme relies on an open-loop frequency estimation technique that does not involve an inverse trigonometric function for the estimation of fundamental frequency deviation. The feedbackless architecture of the scheme and the avoidance of inverse trigonometric function, therefore, assist in reducing the real-time implementation complexity. However, under off-nominal grid frequency deviations, the amplitude and the phase of the output of the prefilter will suffer from errors. These errors are compensated by employing a mathematical regression approach. The results are experimentally validated and compared in order to prove the robustness and usefulness of the proposed scheme for single-phase applications.

A Single-Phase Synchronization Technique for Grid-Connected Energy Storage System Under Faulty Grid Conditions

The control of a single-phase grid-connected energy storage system (ESS) requires a very fast and accurate estimation of grid voltage frequency and phase angle. A phase-locked loop (PLL) based synchronization algorithm usually extracts this information. The operation and control of the entire system are directly affected by the performance of PLL. In this article, a novel advanced single-phase PLL (ASϕPLL) technique with reduced complexity is proposed for the fast and accurate extraction of grid information in an ESS under distorted and abnormal grid conditions, including harmonics, interharmonics, dc offset, and grid faults. The proposed method provides a faster dynamic response, lower frequency overshoot, and accurate estimation under off-nominal grid frequencies with reduced computational complexity in comparison with the existing method. The advanced performance of the proposed ASϕPLL is verified through the simulation and experimental results.

Comparative Analysis of Lattice-based All-Pass Filter and Second Order Generalized Integrator as Orthogonal System Generator of a PLL

This paper presents a steady-state comparison of two methods that generate an orthogonal voltage system for a single-phase Phase-Locked Loop (PLL) structure: a widely accepted one based on a Second Order Generalized Integrator (SOGI) and a new one based on a All-Pass Filter (APF) with Lattice structure. Both methods are very attractive because of their simple digital implementation, low computational load and good performance under harmonically distorted grid conditions and variable frequency, so they are a good alternative to other known methods. The paper derives and analyzes the full state space models of the two methods.It is shown that these two methods are equivalent in the most common operation conditions of distributed energy resources, although the APF structure is clearly better than the SOGI one because it maintains its orthogonal generation ability for any higher notch frequencies and any lower sampling frequencies. The comparative analysis were validated by simulation with MATLAB/Simulink and experimental results using a fixed-point DSP.

Phase-locked loop with DC[sbnd]offset removal for single-phase grid-connected converters

DC-offset in the input of the phase-locked loop (PLL) is an emerging problem that causes oscillations in the estimated fundamental grid phase, frequency, and voltage amplitude. The DC-offset rejection in grid synchronization is a difficult task due to its low-frequency nature. This paper proposes a method to remove the DC-offset in the single-phase grid synchronization utilizing delay signal cancellation (DSC) and a variable-length time delay (VLTD) based PLL. The small-signal model, stability analysis, and controller gains selection are discussed. The proposed PLL is compared with other single-phase PLLs in terms of the phase settling time, the phase percent maximum overshoot, and the peak of the estimated frequency, to show its advantages.

Development of Frequency Fixed Sliding Discrete Fourier Transform Filter Based Single-Phase Phase-Locked Loop

The single-phase phase-locked loop (PLL) is essential for the stable operation and control of single-phase grid-connected converters. However, in practical applications, the grid voltage is usually affected by harmonics and dc offset, which will cause errors in the output of the PLL. Therefore, using sliding discrete Fourier transform filter (SDFT) as a prefilter, this paper proposes an improved single-phase synchronous reference frame PLL with a fixed sampling frequency, which can accurately and quickly obtain the grid parameters under distorted grid conditions. Most importantly, the paper theoretically analyzes phase and amplitude errors generated by SDFT for the first time and a quantitative compensation method is proposed, which is straightforward to be used by a reader. Finally, the proposed PLL is compared with other PLLs through simulation and experiments. The experimental results show the effectiveness and practicability of the proposed method.

Analysis and improvement of fourth‐order generalised integrator based phase‐locked loop

The fourth-order generalised integrator is very suitable for single-phase phase-locked loop because it can provide orthogonal signal conveniently and block harmonic voltages effectively. In the conventional fourth-order generalised integrator based phase-locked loop, the resonance frequency of fourth-order generalised integrator needs to be adjusted according to the grid frequency. To improve the phase-locked loop performance, a non-adaptive fourth-order generalised integrator is suggested for single-phase system, and this paper presents a correction method. According to the estimated grid frequency, the amplitude imbalance and phase error caused by non-adaptive fourth-order generalised integrator can be calculated, and two adaptive units are added to deal with the problems. Moreover, the small-signal model of the proposed phase-locked loop is carried out, and the control parameters are tuned. Compared to conventional fourth-order generalised integrator based phase-locked loop, the proposed phase-locked loop shows a better performance, which is verified through simulation and experimental results.

Single-Phase Phase-Locked Loop Based on Tracking Differentiator

To better capture the phase information of single-phase power grids, a novel single-phase phase-locked loop method is proposed in this paper. The method uses a tracking differentiator as an orthogonal signal generator. Because the generator is sensitive to the input signal’s frequency, the amplitudes of the tracking and differential signals may not be equivalent, causing a failed phase tracking. Therefore, the amplitude correction of the differential signal needs to be done. Then, the corrected differential signal and the tracking signal are both input to the phase detector. To further verify the practical feasibility of the method, the voltage sampling and phase tracking experiments were performed on a digital signal processor-based inverter experimental platform, which is aimed to simulate the grid. The experimental results show that the proposed algorithm has strong dynamic performance and steady-state performance under different states of the power grid, and the phase-locked method has a practical feasibility in single-phase grid-connected applications.

All-Pass-Filter-Based PLL for Single-Phase Grid-Connected Converters Under Distorted Grid Conditions

All-pass-filter-based single-phase phase-locked loop (APF-PLL) is a widely used grid synchronization method in grid-connected power converters. However, the performance of APF-PLL degrades under distorted grid conditions and the estimated phase and frequency will contain low-frequency oscillation terms, which is not conducive to practical application. To deal with this problem, this paper proposes two advanced APF-PLLs, which have good ability to suppress harmonics and dc offset interference without sacrificing the dynamic response of the system. In the first one, a band-pass filter (BPF) is used as the prefilter of APF-PLL to process the input voltage signal, and in the second one, the APF-PLL input signal is processed by using a harmonic decoupling network (HDN) and multiple prefilters. In addition, their parameter design procedure is also described in detail and is easy to follow. The experimental results presented in this paper finally verify the superiority and effectiveness of the two proposed methods.

Comparative study of single-phase phase-locked loops for grid-connected inverters under non-ideal grid conditions

In the renewable power generation systems, ensuring the synchronization of the inverter and the power grid is crucial for the stable operation of grid-connected inverters. Nowadays, the phase-locked loop (PLL) technology has become a widely used grid synchronization method because of its simple implementation and robustness under various grid conditions. Even though a lot of PLLs have been proposed, the overview and comparative analysis of multiple PLLs can be helpful for the practical applications. In addition, the weak grid condition is a great challenge for the system. Therefore, this study firstly presents an overview of the existing PLLs together with their general structures and basic working principles. Depending on the implementation of the phase detector, the PLL can be divided into three categories: power-based PLL (pPLL), orthogonal-signal-generator-based PLL (OSG-PLL) and adaptive-filter-based PLL (AF-PLL). Then, from the above classification, seven typical single-phase PLLs are selected for further study. Finally, some test results are given, and a comprehensive evaluation of the selected PLLs under different grid conditions is conducted.

Small-Signal Modeling and Design of Phase-Locked Loops Using Harmonic Signal-Flow Graphs

This article introduces signal-flow graphs for linear time-periodic systems to streamline and visually describe the frequency-domain modeling of complex phase-locked loop (PLL) systems used in grid-connected converters. Small-signal modeling using the proposed graphs is demonstrated for two commonly used single-phase PLL structures: SOGI-PLL and Park-PLL. Loop-gain models are developed for these PLLs to evaluate how an orthogonal signal generator (OSG), which is required in single-phase PLLs using the synchronous reference frame (SRF) architecture, modifies the PLL loop gain compared to that of a three-phase SRF-PLL, which does not require an OSG. It is shown that the OSG in the SOGI-PLL and Park-PLL introduces a significant phase lag in the PLL loop gain, limiting the maximum bandwidth for which either PLL can be designed. Slow-frequency adaptation (SFA) of OSG is proposed to mitigate the influence of the OSG dynamics on the PLL loop gain. Experimental results are presented to validate the developed loop-gain models and show that the proposed SFA-SOGI-PLL and SFA-Park-PLL have better transient performance, they do not suffer from the bandwidth limit, and they preserve the steady-state performance of the standard SOGI-PLL and Park-PLL.