Single-level Cell Research Articles

Enhancing Lifetime and Performance of MLC NVM Caches Using Embedded Trace Buffers

Large volumes of on-chip and off-chip memory are required by contemporary applications. Emerging non-volatile memory technologies including STT-RAM, PCM, and ReRAM are becoming popular for on-chip and off-chip memories as a result of their desirable properties. Compared to traditional memory technologies such as SRAM and DRAM, they have minimal leakage current and high packing density. Non Volatile Memories (NVM), however, have a low write endurance, a high write latency, and high write energy. Non-volatile Single Level Cell (SLC) memories can store a single bit of data in each memory cell, whereas Multi Level Cells (MLC) can store two or more bits in each memory cell. Although MLC NVMs have substantially higher packing density than SLCs, their lifetime and access speed are key concerns. For a given cache size, MLC caches consume 1.84× less space and 2.62× less leakage power than SLC caches. We propose Trace buffer Assisted Non-volatile Memory Cache (TANC), an approach that increases the lifespan and performance of MLC-based last-level caches using the underutilized Embedded Trace Buffers (ETB). TANC improves the lifetime of MLC LLCs up to 4.36× and decreases average memory access time by 4% compared to SLC NVM LLCs and by 6.41× and 11%, respectively, compared to baseline MLC LLCs.

Co-design of SLC/MLC FeFET-based highly error-tolerant low-power CiM and strong lottery ticket hypothesis-based algorithm

This study co-designs single-level cell (SLC) mask and multilevel cell (MLC) weight twin FeFET devices and a strong lottery ticket hypothesis (SLTH)-based neural network (NN) algorithm to achieve highly error-tolerant low-power Computation-in-Memory (CiM). The SLC mask FeFET masks or transfers the NN weight stored in the MLC weight FeFET, and the masked NN weight reduces the CiM power consumption. The proposed SLC mask FeFETs, which are trained, and MLC weight FeFETs, in which V TH are uniformly randomized, achieve 87% inference accuracy against 10-year data retention and read disturb. The SLC mask FeFETs show 86% inference accuracy even at 2000 endurance cycles. In addition, shared-bottom-select-gate (BSG) SLTH CiM and common-mask SLTH CiM for the NN convolutional layer are proposed to reduce the CiM area by sharing BSG and mask FeFET. Moreover, NN weight mapping schemes for SLTH CiM are proposed. The proposed mapping schemes show a tradeoff between inference accuracy and CiM area. One of the schemes reduces the CiM area by 45% with a 9.1% accuracy loss.

Data Placement Using a Classifier for SLC/QLC Hybrid SSDs

In hybrid SSDs (solid-state drives) consisting of SLC (single-level cell) and QLC (quad-level cell), efficiently using the limited SLC cache space is crucial. In this paper, we present a practical data placement scheme, which determines the placement location of incoming write requests using a lightweight machine-learning model. It leverages information about I/O workload characteristics and SSD status to identify cold data that does not need to be stored in the SLC cache with high accuracy. By strategically bypassing the SLC cache for cold data, our scheme significantly reduces unnecessary data movements between the SLC and QLC regions, improving the overall efficiency of the SSD. Through simulation-based studies using real-world workloads, we demonstrate that our scheme outperforms existing approaches by up to 44%.

Nonvolatile flash memory device with ferroelectric blocking layer via in situ ALD process

To improve performances of nonvolatile charge trap flash memory devices, we propose an in situ Hf0.5Zr0.5O2 (HZO)/HfO2/Al2O3 stacked structure, which is compatible for Si with the metal–oxide–semiconductor (MOS) process based on all atomic layer deposition. Since the appropriate bandgap difference between Al2O3 and HfO2, stable charge trap operation is achieved. High-quality ferroelectric HZO film characteristics were showed by minimizing defects and Si diffusion through the sub-layer of Al2O3/HfO2. Therefore, HZO as a blocking layer enhances the memory performance of the charge trap structure due to its specific polarization effect. The proposed device has the high polarization characteristics of HZO (2Pr > 20 μ C/cm2) along with a MOS-cap window (>4 V), good retention capability (>10 years), fast program/erase response operation times (<200 μs), and strong durability (>105 cycles) while operating as a form of single level cell. By comparing Al2O3 and ferroelectric HZO as a blocking layer of the charge trap device, we confirmed that the HZO/HfO2/Al2O3 multi-layer structure had excellent characteristics according to various memory performance indicators. Our proposed high-performance charge trap flash memory can be employed in various applications, including Si-based three-dimensional structures with artificial intelligence systems.

Performance and reliability optimization for high-density flash-based hybrid SSDs

Hybrid SSDs that integrate both large-capacity flash and high-performance flash have become the mainstream of the existing SSD architectures. Two or more flash modes have been supported to satisfy the complex and changeable application requirements, such as single-level-cell (SLC) mode and quad-level-cell (QLC) mode, which can be adaptively switched. However, our empirical studies show that the combination is not well-designed in existing hybrid architectures. We conduct experiments on different scenarios to study the performance and reliability of real hybrid SSDs. Three interesting findings about performance collapse, performance fluctuation, and read disturb of QLC region can be obtained. To solve these problems, this paper proposed HyFlex, including three novel schemes. First, a velocity-based I/O scheduling (VIS) scheme is a novel data placement scheme to avoid performance corrupt. Second, a garbage collection aware capacity tuning (GCT) scheme is a novel flash-mode management scheme to avoid burst performance degradation. Third, a read disturb-aware data migration (DAM) scheme is a novel data migration scheme to alleviate the read disturb of the QLC region. The experiments are conducted on an existing simulator with hybrid SSD extensions. Experimental results show that HyFlex achieves encouraging performance and reliability optimization.

A Robust Time-Based Multi-Level Sensing Circuit for Resistive Memory

Resistive random access memory (RRAM) is a promising emerging nonvolatile memory (NVM) due to its large resistance ratio in different switching states. To improve memory density and reduce cost-per-bit, multi-level cell (MLC) RRAM stores multiple bits in a single cell, compared to a single-level cell (SLC). However, random mismatch, process variation, and resistance shift lead to reliability issues, degrade the probability of correct read, and increase the bit error rate (BER). This paper presents a time-based sensing scheme for robust read operation and extends to multi-level sensing for SLC and MLC RRAM arrays. Bit line (BL) voltage is converted into time delay by a voltage-to-time converter (VTC) and compared with the implicit timing reference generated by a delay line. By detecting different states in the time domain, the proposed time-mode sense amplifier (TSA) requires no analog reference voltage or current, which is used in the conventional voltage-mode sense amplifiers (VSA) or current-mode sense amplifiers (CSA). Power gating is employed to enable the time sampling only at the sensing points to suppress the short-circuit current. A charge sharing-induced error compensation (CSEC) circuit is used to eliminate the charge sharing-induced voltage drop and expand the sense margin by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.56\times $ </tex-math></inline-formula> . Monte Carlo simulations in 40nm technology show that the proposed TSA improves read reliability and reduces BER by 3–4 orders of magnitude compared to conventional VSA and CSA. The proposed time-based sensing scheme operates from 0.7-1.2 V supply and consumes 49 fJ/bit for read operation under a nominal 1.2 V supply.

고집적 낸드 플래시 SSD의 수명 및 쓰기 성능 향상을 위한 BER 기반 하이브리드 파티션 기법

낸드 플래시 기반 SSD (solid-state drive)는 제한된 P/E (program/erase) 사이클 횟수로 인한 내구성 문제로 TLC (triple-level cell)에서 QLC (quad-level cell)로 전환하는데 어려움이 있다. FTL (flash translation layer) 수준에서 내구성 문제를 해결하기 위해서는 블록의 수명을 예측하여 불량 블록 발생을 최소화하는 것이 중요하며, 이를 위해 비트 오류율 (bit error rate, BER)을 내구성 지표로 사용하여 수명을 균등하게 유지하는 방법이 사용되고 있다. 하지만 다중 레벨 셀 (MLC, TLC, QLC) 낸드 플래시의 일부를 SLC (single-level cell) 모드로 사용하는 하이브리드 SSD에서는 여전히 P/E 사이클을 기준으로 SLC 영역을 선정하고 있기 때문에 실제 SSD 수명과 불일치 가능성이 높아 효과적이지 않다. 본 논문에서는 하이브리드 SSD 파티션을 위해 내구성 지표로 BER을 사용하는 BDQS (BER Disparity based QLC to SLC mode programming) 기법을 제안한다. 동일한 수준의 BER을 가지는 QLC 블록들을 선별해 SLC 영역으로 전환하고 추가적으로 전환된 SLC 영역 블록의 BER을 보다 세분화해 콜드 (cold) 데이터 쓰기 버퍼, 핫 (hot) 데이터 저장 공간으로 활용함으로써 수명을 보다 개선시킬 수 있도록 한다. BDQS 기법은 쓰기 버퍼가 없는 기존 하이브리드 SSD 구조 대비 약 9.6%의 용량 감소가 발생하지만, SLC 저장 공간의 불량 블록 발생 시간이 최대 69.0%, 시스템 수명은 40.3% 연장되었고 그리고 baseline 대비 평균 쓰기 응답 시간도 22.0%까지 개선됨을 확인하였다.

Adaptive Mode Transformation for Wear Leveling in Nonvolatile FPGAs

Nowadays, field programmable gate arrays (FPGAs) have been widely adopted to serve as accelerators in artificial intelligence and big data related applications. Since the static random access memory (SRAM)-based FPGA is suffering from limited density and high leakage power, nonvolatile FPGAs have been proposed, where SRAM is replaced with emerging nonvolatile memories (NVMs). Multilevel cell (MLC), which can store multiple bits within one memory cell, further improves the density of nonvolatile FPGAs and shows great potential to enable large on-chip memory. However, it suffers from limited lifetime. In this article, we propose a wear leveling scheme to improve lifetime of MLC-based nonvolatile FPGAs. Instead of generating a series of configuration files for runtime reconfiguration, we propose to identify write-heavy MLC regions and dynamically transform them to durable single-level cell (SLC) mode. Specifically, we propose three modules: 1) pertaining to write behavior monitor; 2) approximate cost calculator; and 3) mode transformation manager to achieve adaptive mode transformations. We consider FPGA features to design these modules, which is different from implementations for MLC-SLC transformation in CPU architecture. Evaluation shows that the proposed scheme can improve lifetime for MLC nonvolatile FPGAs by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$6.03\times $ </tex-math></inline-formula> , at cost of 12.5% storage overhead.

Design space exploration for balanced MLC-PCM programming

Multi-Level Cell Phase Change Memory (MLC PCM) is a non-volatile memory technology that promises high-density data storage. However, MLC PCM suffers from long write latency because changing the state of each memory cell takes a long time and the number of cells that can be written concurrently is limited due to the relatively large size and power consumption of the write drivers. MLC PCM typically divides the write data into multiple cell groups to program cells in batches. The group mapping has a significant impact on the overall latency of write requests. Prior work proposed a group mapping technique for single-level cell (SLC) PCM based on the data pattern of a set of applications. In this work, a larger design space of group mapping is explored for MLC PCM. The specific group mapping for each benchmark is dynamically customized. Our technique leads to a 13.14% reduction in write latency compared to the state-of-the-art method (Du et al., 2013) and shows good temporal consistence in different benchmarks.

A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References

Resistive random access memory (RRAM)-based compute-in-memory (CIM) has shown great potential for accelerating deep neural network (DNN) inference. However, device characteristics, such as low-resistance values, susceptibility to drift, and single-level cells, may limit the capabilities of RRAM-based CIM. In addition, prior works generally used the off-chip write-verify scheme to tighten RRAM resistance distributions and used off-chip analog-to-digital converter (ADC) references for fine-tuning partial sum quantization. Although off-chip techniques are viable for testing purposes, they may be unsuitable for practical applications. In this work, we present an RRAM-CIM macro to accelerate DNN inference. The chip features: 1) multi-level cell (MLC) RRAM for improving compute performance and density; 2) sparsity-aware input control to leverage the high activation sparsity in DNN models; 3) on-chip write-verify to speed up initial weight programming and periodically refresh cells to compensate for resistance drift under stress; and 4) on-chip ADC reference generation that provides column-wise tunability and stability with varying temperatures to guarantee the CIFAR-10 accuracy of 85.8% at 120 °C. The design is fabricated in TSMC 40-nm process with embedded RRAM technology and achieves a macro-level peak performance of 97.8 GOPS/mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and 44.5 TOPS/W for multiply-and-accumulate (MAC) operations on VGG-8 network with ternary weights.

New Total-Ionizing-Dose Resistant Data Storing Technique for NAND Flash Memory

This paper describes a new non-charge-based data storing technique in NAND flash memory called watermark that encodes read-only data in the form of physical properties of flash memory cells. Unlike traditional charge-based data storing method in flash memory, the proposed technique is resistant to total ionizing dose (TID) effects. To evaluate its resistance to irradiation effects, we analyze data stored in several commercial single-level-cell (SLC) flash memory chips from different vendors and technology nodes. These chips are irradiated using a Co-60 gamma-ray source array for up to 100 krad(Si) at Sandia National Laboratories. Experimental evaluation performed on a flash chip from Samsung shows that the intrinsic bit error rate (BER) of watermark increases from <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\sim }0.8$ </tex-math></inline-formula> % for TID = 0 krad(Si) to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf {\mathrm {\sim }}1$ </tex-math></inline-formula> % for TID = 100 krad(Si). Conversely, the BER of charge-based data stored on the same chip increases from 0% at TID = 0 krad(Si) to 1.5% at TID = 100 krad(Si). The results imply that the proposed technique may potentially offer significant improvements in data integrity relative to traditional charge-based data storage for very high radiation (TID <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mathbf { &gt; } 100$ </tex-math></inline-formula> krad(Si)) environments. These gains in data integrity relative to the charge-based data storage are useful in radiation-prone environments, but they come at the cost of increased write times and higher BERs before irradiation.

Leveraging Write Heterogeneity of Phase Change Memory on Supporting Self-Balancing Binary Tree

With the increasing demand of massive/big data applications, non-volatile memory (NVM), such as phase change memory (PCM), has become a promising candidate to replace DRAM because of its low leakage power, non-volatility, and high density. However, most of the existing memory read/write intensive algorithms and data structures are not aware of the PCM write heterogeneity in terms of both energy consumption and latency. In particular, self-balancing binary search trees, which are widely used to manage massive data in the big-data era, were designed without the consideration of PCM characteristics. Thus, the multiple rotations of the tree balancing process would degrade the memory performance. This work explores the relations among nodes and analyzes tree operations, and the node indexing and address mapping are redesigned to reduce the tree management overhead on single-level cell (SLC) PCM by decreasing the number of bit flips of tree rotations. When multi-level cell (MLC) PCM is included, our address mapping algorithm is developed to reduce the total energy consumption and latency with considerations of the heterogeneous write operations of different cell states. Experimental results show that our solution significantly outperforms the original implementation of a self-balancing binary search tree when the amount of data is large.

Optimizing data placement and size configuration for morphable NVM based SPM in embedded multicore systems

Embedded multicore systems are widely designed to meet the high-performance requirement. Meanwhile, many embedded multicore systems are equipped with multiple scratchpad memories (SPM) because of their advantages in power efficiency and small area. Whereas, the traditional SRAM-based SPM is limited by its leakage power and capacity. Compared with SRAM, emerging non-volatile memory (NVM) has lower power consumption. Moreover, some morphable NVMs like resistive memory can build a “morphable NVM” to get a balance between capacity and performance, in which a memory cell can be converted between high-density MLC (multi-level cell) and low-latency SLC (single-level cell).Considering the features of NVM, this paper proposes a dynamic data placement and size configuration technique to fully utilize the benefits from morphable NVM based SPM in embedded multicore systems. The core idea is to dynamically convert the memory mode of NVM in each SPM with different workloads, and store the associated data into an optimal storage location for minimizing the total cost of memory access. Therefore, combining with the access pattern of embedded systems, an Integer Linear Programming (ILP) model is first explored for obtaining the optimal data placement and size configuration of SLC/MLC of SPMs. Then, our polynomial-time algorithm (CDA) is provided to obtain a near-optimal result. Finally, our experiments based on the gem5 simulator exhibit the proposed techniques can achieve the performance improvement and the reduction of energy consumption compared with the baseline scheme.

A Dynamic Huffman Coding Method for Reliable TLC NAND Flash Memory

With the progress of the manufacturing process, NAND flash memory has evolved from the single-level cell and multi-level cell into the triple-level cell (TLC). NAND flash memory has physical problems such as the characteristic of erase-before-write and the limitation of program/erase cycles. Moreover, TLC NAND flash memory has low reliability and short lifetime. Thus, we propose a dynamic Huffman coding method that can apply to the write operations of NAND flash memory. The proposed method exploits observations from a Huffman tree and machine learning from data patterns to dynamically select a suitable Huffman coding. According to the experimental results, the proposed method can improve the reliability of TLC NAND flash memory and also consider the compression performance for those applications that require the Huffman coding.

High-Performance Computing-in-Memory Architecture Based on Single-Level and Multilevel Cell Differential Spin Hall MRAM

Computing-in-memory (CiM) architectures have experienced faster growth with the emergence of nanoscale magnetic tunnel junction (MTJ) spintronic devices due to their nonvolatile and CMOS compatible architectures. Recently, spin-transfer torque (STT) and spin Hall effect (SHE)-based several CiM designs have been published. The majority of these designs employ a single-level cell (SLC) memory array and require high write energy to perform logic computations. To mitigate these problems, we propose novel SLC and multilevel cell (MLC) differential spin Hall (DSH) magnetic random access memory (MRAM)-based CiM designs that employed MTJs with field-free switching technique using the in-plane magnetic (IPM) layer. Initially, SLC DSH-MRAM-based magnetic full adder (MFA) is proposed. Furthermore, DSH-MRAM series MLC (sMLC)-based CiM implementations of AND/OR/XOR gates and 1 bit MFA are presented in this work. This DSH-sMLC-based CiM structure exploits a reconfigurable precharge sense amplifier (RPCSA) and innovative MTJ reference mechanism to perform each of the logic operations within a single evaluation cycle and provides complementary logic outputs useful for further computations. The comparative performance analysis of the proposed CiM MFA with SHE-based and voltage-controlled SHE-sMLC-based CiM designs reveals 52% and 33% improvement in write energy, respectively. The proposed design saves 34% area compared to the SHE-based counterpart.

Non-volatile memory system design of edge server and cloud centralized server for multiple-tier 5G network

This paper co-designs a network and non-volatile memory system for a fifth generation (5G) multiple-tier network. Because a 5G network has shorter latency and wider bandwidth compared with a 4G network, the non-volatile memory system becomes a bottleneck. From the bottom to the top of the multiple-tier network, edge devices/machines, edge servers, and cloud centralized servers play different types of roles and handle different types of data. Thus, different types of non-volatile memory are required for cloud centralized servers, edge servers, and edge devices/machines. This work employs three-dimensional single-level cell (3D-SLC) NAND flash memory for edge servers and resistive RAM (ReRAM) for cloud centralized servers. To achieve short latency and low cost of the non-volatile memory system, distributed multiple write for 3D-SLC NAND flash memory and hierarchical multiple-deck ReRAM are proposed. By using an evaluation platform of the network and non-volatile memory co-design system, the proposed non-volatile memory system is defined as a network bottleneck or memory bottleneck.

Observation of Low-Energy Proton Direct Ionization in a 72-Layer 3-D NAND Flash Memory

Single-event upsets are observed in a 72-layer 3-D NAND flash memory operated in a single-level cell mode after low-energy proton (500 keV-1.2 MeV) and heavy-ion irradiation. The layer-by-layer error count is analyzed to visualize the stopping of low-energy protons within the memory stack, and Monte Carlo simulations are correlated with the experimental data. Direct ionization by low-energy protons is identified by 3-D data analysis and the energy dependence of device-sensitive cross section. Heavy-ion data is also presented for comparison.

Hercules: Intelligent Coupling of Dual-Mode Flash Memory and Hard Disk Drive

Abstract The write performance of multi-level cell (MLC) is several times slower than single-level cell (SLC); however, the cost per bit of MLC is much lower than SLC. Dual-mode flash (the medium can be partially switched to SLC mode by programming only 1 bit in some cells) can combine SLC and MLC to provide trading density opportunity for performance. In this paper, we present Hercules—a hybrid storage system that couples dual-mode flash memory and hard drive disk (HDD)—based on the content locality principle for high storage performance. The data are divided into two types: the reference data for read operation and the delta data for write operation. The reference data are stored in SLC and the delta data in MLC or HDD in sequential orders. Hercules organizes the metadata for the mapping of the physical locations of the reference blocks and the delta data of the original blocks, intelligently identifies hot/cold data and performs the data migration between MLC and disk for performance improvements. To validate our findings, we implemented Hercules and made evaluation to show that Hercules can effectively improve the data access speed and reduce the response time, compared with the Flashcache storage structure, and in particular, with Hercules, we can achieve 10% performance improvement over the system in absence of hot delta data caching.

A CMOS-integrated compute-in-memory macro based on resistive random-access memory for AI edge devices

The development of small, energy-efficient artificial intelligence edge devices is limited in conventional computing architectures by the need to transfer data between the processor and memory. Non-volatile compute-in-memory (nvCIM) architectures have the potential to overcome such issues, but the development of high-bit-precision configurations required for dot-product operations remains challenging. In particular, input–output parallelism and cell-area limitations, as well as signal margin degradation, computing latency in multibit analogue readout operations and manufacturing challenges, still need to be addressed. Here we report a 2 Mb nvCIM macro (which combines memory cells and related peripheral circuitry) that is based on single-level cell resistive random-access memory devices and is fabricated in a 22 nm complementary metal–oxide–semiconductor foundry process. Compared with previous nvCIM schemes, our macro can perform multibit dot-product operations with increased input–output parallelism, reduced cell-array area, improved accuracy, and reduced computing latency and energy consumption. The macro can, in particular, achieve latencies between 9.2 and 18.3 ns, and energy efficiencies between 146.21 and 36.61 tera-operations per second per watt, for binary and multibit input–weight–output configurations, respectively. Commercial complementary metal–oxide–semiconductor and resistive random-access memory technologies can be used to create multibit compute-in-memory circuits capable of fast and energy-efficient inference for use in small artificial intelligence edge devices.

Managing Device Lifecycle: Reconfigurable Constrained Codes for M/T/Q/P-LC Flash Memories

Flash memory devices are winning the competition for storage density against magnetic recording devices. This outcome results from advances in physics that allow storage of more than one bit per cell, coupled with advances in signal processing that reduce the effect of physical instabilities. Constrained codes are used in storage to avoid problematic patterns. Recently, we introduced binary symmetric lexicographically-ordered constrained codes (LOCO codes) for data storage and data transmission. This paper introduces simple constrained codes that support non-binary physical substrates; multi, triple, quad, and the currently-in-development penta-level cell (M/T/Q/P-LC) Flash memories. The new codes can be easily modified if problematic patterns change with time. These codes are designed to mitigate inter-cell interference, which is a critical source of error in Flash devices. The occurrence of errors is a consequence of parasitic capacitances in and across floating gate transistors, resulting in charge propagation from cells being programmed to the highest charge level to neighboring cells being programmed to lower levels. The new codes are called $q$-ary asymmetric LOCO codes (QA-LOCO codes), and the construction subsumes codes previously designed for single-level cell (SLC) Flash devices (A-LOCO codes). QA-LOCO codes work for a Flash device with any number, $q$, of levels per cell. For $q \geq 4$, we show that QA-LOCO codes can achieve rates greater than $0.95 \log_2 q$ information bits per coded symbol. The complexity of encoding and decoding is modest, and reconfiguring a code is as easy as reprogramming an adder. Capacity-achieving rates, affordable encoding-decoding complexity, and ease of reconfigurability support the growing development of M/T/Q/P-LC Flash memory devices, as well as lifecycle management as the characteristics of these devices change with time.