Single-gate Mode Research Articles

Impact of Dual-Gate Configuration on the Endurance of Ferroelectric Thin-Film Transistors With Nanosheet Polycrystalline-Silicon Channel Film

This work explores the characteristics of ferroelectric thin-film transistors (FeTFTs) utilizing an asymmetric dual-gate (DG) structure in both single-gate (SG) and DG operation modes. In the transfer characteristics, DG mode exhibits a memory window (MW) of 1.075 V, smaller than SG mode’s MW of 1.402 V, attributed to the back-gate bias effect causing a reduction in the device’s threshold voltage. However, DG mode demonstrates superior endurance characteristics with 106 cycles compared to SG mode’s 105 cycles. Additionally, the increase in erase pulse voltage (VERS) exacerbates the polycrystalline-silicon channel lattice damage of FeTFT, resulting in subthreshold swing (SS) degradation. Nevertheless, the extent of SS degradation from DG mode operation is significantly lower than that of SG mode, contributing to the superior endurance of DG mode. The elevation of program pulse voltage (VPRG) induces imprint and charge-trapping effects in the top-gate ferroelectric dielectric, leading to reduced endurance. Due to the use of SiO2 as the back-gate dielectric in FeTFT, DG mode exhibits lower impacts of charge-trapping effects from the top-gate ferroelectric dielectric layer, resulting in better endurance compared to SG mode. The asymmetric DG structure provides greater tolerance in the selection of VPRG and VERS.

Double-gate structure enabling remote Coulomb scattering-free transport in atomic-layer-deposited IGO thin-film transistors with HfO2 gate dielectric through insertion of SiO2 interlayer

In this paper, high-performance indium gallium oxide (IGO) thin-film transistor (TFT) with a double-gate (DG) structure was developed using an atomic layer deposition route. The device consisting of 10-nm-thick IGO channel and 2/48-nm-thick SiO2/HfO2 dielectric was designed to be suitable for a display backplane in augmented and virtual reality applications. The fabricated DG TFTs exhibit outstanding device performances with field-effect mobility (μFE) of 65.1 ± 2.3 cm2V−1 s−1, subthreshold swing of 65 ± 1 mVdec−1, and threshold voltage (VTH) of 0.42 ± 0.05 V. Both the (μFE) and SS are considerably improved by more than two-fold in the DG IGO TFTs compared to single-gate (SG) IGO TFTs. Important finding was that the DG mode of IGO TFTs exhibits the nearly temperature independent μFE variations in contrast to the SG mode which suffers from the severe remote Coulomb scattering. The rationale for this disparity is discussed in detail based on the potential distribution along the vertical direction using technology computer-aided design simulation. Furthermore, the DG IGO TFTs exhibit a greatly improved reliability with negligible VTH shift of − 0.22 V under a harsh negative bias thermal and illumination stress condition with an electric field of − 2 MVcm−1 and blue light illumination at 80 °C for 3600 s. It could be attributed to the increased electrostatic potential that results in fast re-trapping of the electrons generated by the light-induced ionization of deep level oxygen vacancy defects.

Results and model for single-gate ratchet charge pumping

We show experimentally that, in the same Si devices, we can demonstrate multiple two-gate pumping modes but not single-gate mode. We contrast this with GaAs devices, which do show single-gate pumping at a high yield. We propose four mechanisms to explain the lack of plateaus in the Si devices in single-gate ratchet mode: operating the dot with a large number of electrons, a large ratio between the change in electrochemical potential energy and the change in the energy of the barrier (plunger-to-barrier ratio, Δptb) compared to the charging energy (Δptb/EC), nonlinear tunnel barriers, and phase offset leading to nonequilibrium heating. Our analysis shows that each of these could contribute to the lack of plateaus in single-gate ratchet pumping on Si devices but allow two-gate pumping methods to work with robust plateaus. It is easier for GaAs pumps to avoid these failure mechanisms due to their different architectures and cleaner gate turnoff curves. We propose several methods to reduce these sources of error, including reducing cross capacitances between gates. These recommendations may prove useful to other researchers in producing more robust, higher yield single-gate ratchet pumps.

Triple Gate Polycrystalline-Silicon-Based Ion-Sensitive Field-Effect Transistor for High-Performance Aqueous Chemical Application

In this paper, we developed a polycrystalline-silicon (poly-Si) thin-film transistor (TFT)-based high-performance ion-sensitive field-effect transistor (ISFET) pH sensor that far surpasses the sensitivity of dual-gate (DG) pH sensors. A triple gate (TG) structure on the same plane as the channel of the ISFET has been proposed to enhance the pH sensitivity. In a poly-Si TFT-based ISFET, a TG is more advantageous than a bottom-gate for increasing the capacitive coupling with the top-gate. As a result, the pH sensitivity by TG mode detection using the TG is much greater than the single-gate (SG) mode detection using the top-gate, or the DG mode detection using the bottom-gate. The sensitivity of the TG mode increased greatly compared with the sensitivity of the conventional SG mode or DG mode. The measured pH sensitivity was 57.75 ± 0.77 mV/pH in the SG mode and 467.08 ± 9.92 mV/pH in the DG mode. In particular, the TG mode gives a maximum sensitivity of 1283.56 ± 45.54 mV/pH for sensing membranes having a theoretical Nernstian pH response (59.15 mV/pH at 25 °C). Furthermore, we measured the hysteresis and drift characteristics, and found that the TG mode has improved non-ideal behavior compared with the SG and DG modes. Therefore, the poly-Si TFT-based TG ISFET pH sensor has the potential to become a promising biosensor application platform, with excellent sensitivity and stability.

Fin-Width Effects on Characteristics of InGaAs-Based Independent Double-Gate FinFETs

We report the characteristics of InGaAs-based independent double-gate FinFETs with Al2O3/LaAlO3 as gate dielectric. The device can be operated in three different modes ( i.e., single-, double-, and independent double-gate) made possible by the physically separated two sidewall gates. When the device is operated in the double-gate mode, it exhibits better performance in terms of the On/Off current ratio, subthreshold swing, Off current, and channel mobility than in the single-gate mode. In addition, independent double-gate operation makes it possible to modulate channel properties by applying a bias at the opposite gate via gate coupling effects. Our systematic measurements reveal that gate control and coupling effects are enhanced with reduced fin width.

Highly sensitive ion-sensitive field-effect transistor sensor using fully transparent amorphous In–Ga–Zn–O thin-film transistors

In this study, a highly sensitive ion-sensitive field-effect transistor (ISFET) sensor was developed using fully transparent amorphous In–Ga–Zn–O thin-film transistors fabricated on a glass substrate. To overcome the issues associated with conventional ISFETs, such as low sensitivity and poor reliability, a dual-gate (DG) operating mode was employed, which is able to significantly amplify the sensitivity through capacitive coupling between the front and back gate dielectrics. As a result, when compared to the sensitivity in the single-gate mode, the DG mode exhibited a high sensitivity of 269.3 mV/pH, which is beyond the Nernst response limit.

Dual Gate Charge Trap Flash Memory for Highly Reliable Triple Level Cell using Capacitive Coupling Effects

In this letter, the triple level cell (TLC) NAND flash memory with excellent properties was implemented by a thin film charge trap flash memory with a dual-gate structure by using the capacitive coupling effect between the front gate and back gate. As compared with the single-gate (SG) mode operation, a large memory window at low program and erase (P/E) voltages was obtained from the dual-gate (DG) mode operation owing to the capacitive coupled self-amplifying effect. The TLC was implemented by using the DG-mode operation with highly stable eight levels: a large threshold voltage difference >9 V per level was obtained under low operating voltages at $100~\mu \text{s}$ . In contrast, the conventional SG mode was unfavorable to TLC. Furthermore, the DG mode showed a much smaller charge loss than the SG mode, resulting in stable retention and endurance characteristics at room temperature and high temperature.

Self-Amplified Dual Gate Charge Trap Flash Memory for Low-Voltage Operation

We propose a self-amplified charge trap Flash memory using the dual-gate (DG) mode operation based on the capacitive coupling between the front-gate and back-gate as a promising next-generation nonvolatile memory. It is found that the coupling ratio and memory window strongly depend on the thickness of the buried oxide (BOX) layer in the silicon-on-insulator (SOI) substrate. As the BOX thickness of the SOI substrate increases, the coupling ratio and memory window of Flash memory cells increase. The DG mode can obtain a larger memory window, reduced operation voltage, and improved reliability compared with the conventional single-gate mode operation.

Quasi-double gate regime to boost UTBB SOI MOSFET performance in analog and sleep transistor applications

This paper investigates both electrostatic control improvement and performance enhancement of UTBB SOI MOSFETs obtained in quasi-double-gate (QDG) regime (i.e. simultaneously biasing top- and back-gate (substrate or ground plane) as Vbg=k·Vg) as a strong function of k-multiplication factor, when compared to a standard single-gate mode. Improved performance (in terms of transconductance, drive current and early voltage) in QDG mode combined with lowered DIBL and enhanced gain are of interest for high-precision low-frequency analog applications. QDG mode is demonstrated to allow threshold voltage tuning, subthreshold swing reduction and on-current enhancement without off-state current degradation, thus of interest for digital applications. The unique feature of QDG mode is finally exploited to boost the performances of the sleep transistor in the practical use case of a power-gated processor. About 30% reduction of the leakage in stand-by mode is achieved at nominal Vg with a Vbg of 3V, which can be generated at marginal area/power overheads with an on-chip charge pump with an architecture proposed in this paper.

Design and Analysis of Robust Tunneling FET SRAM

With a steep subthreshold slope, tunneling FETs (TFETs) are promising candidates for ultralow-voltage operation compared with conventional MOSFETs. However, the delayed saturation characteristic and the broad soft transition region result in a large crossover region/current in an inverter, thus degrading the hold/read static noise margin (H/RSNM) of TFET SRAM cells. The write-ability and write static noise margin (WSNM) of TFET SRAM cells are constrained by the unidirectional conduction characteristics and large crossover contention of the write access transistor and the holding transistor. In this paper, we present a detailed analysis of TFET circuit switching/output characteristics/performance and the underlying physics. The stability/performance of several TFET SRAM cells are then analyzed/compared using atomistic technology computer-aided design mixed-mode simulations. Finally, a robust 7T driverless (DL) TFET SRAM cell is proposed. The proposed 7T DL TFET SRAM cell, with better output characteristics in single-gate mode, and decoupled read current path from cell storage node and push-pull write action with asymmetrical raised-cell-virtual-ground write-assist, provides a significant improvement in hold, read, and write stability and performance.

Study on dual-lateral-gate suspended-body single-walled carbon nanotube field-effect transistors

Self-aligned suspended-body single-walled (SW) carbon nanotube field-effect transistors (CNFETs) with dual lateral gates have been demonstrated. Two independent lateral gates are symmetrically placed less than 100nm away from the CNT channel. The operations of the suspended-body SWCNFETs in single-gate (SG) mode and dual-gate (DG) mode are analyzed in detail. In SG mode, strong controllability of the primary gate and the tuning effect of the second gate have been observed. Tunable threshold voltage and transconductance with constant subthreshold swings are the typical effects in the suspended-body CNFETs. Compared to SG mode, superior characteristics have been obtained in DG mode: remarkably improved subthreshold slope (from 130mV/decade to 86mV/decade), three time larger on-current and four times larger transconductance. The dual-lateral-gate suspended-body CNFETs are of great interest for complementary metal–oxide–semiconductor (CMOS) and nano-electro-mechanical-systems (NEMS) devices, such as tunable/switchable resonators for sensing and radio-frequency applications.

Origins of Performance Enhancement in Independent Double-Gated Poly-Si Nanowire Devices

In this paper, we characterize and compare the characteristics of a poly-Si nanowire (NW) device with independent double-gated configuration under different operation modes. In the device, the tiny NW channels are surrounded by an inverted-T-shaped gate and a top gate. It is found that the device under double-gate (DG) mode exhibits significantly better performance with respect to the two single-gate (SG) modes, as indicated by a higher current drive than the combined sum of the two SG modes and a smaller subthreshold swing of less than 100 mV/dec. Origins of such improvement have been identified to be due to the elimination of the back-gate effect as well as an enhancement in the effective mobility with the DG operation.

Hole mobility enhancement by double-gate mode in ultrathin-body silicon-on-insulator p-type metal-oxide-semiconductor field-effect transistors

Hole mobility enhancement in double-gate (DG) ultrathin-body (UTB) silicon-on-insulator (SOI) p-type metal-oxide-semiconductor field-effect transistors (MOSFETs) is investigated systematically in comparison with single-gate (SG) UTB MOSFETs for various SOI thicknesses (TSOI) ranging from 2 to 30 nm. It is found that mobility in DG mode (μDG) is higher than that in SG mode (μSG) in all the measured ranges of TSOI and the surface carrier concentrations (Ns). In particular, enhancement of mobility of the sub-10-nm-thick TSOI devices is greater at higher Ns. As a result, it is demonstrated that μDG of the 8.1-nm-thick TSOI device is 12.9% greater than the universal mobility when Ns is 6×1012 cm−2. Higher μDG is attributed to the average effective mass reduction in DG mode because of the increased population in the light hole (LH) bands. Careful investigation also clarifies that mobility in the sub-10-nm-thick TSOI devices is enhanced greatly at higher Ns, since the DG mode-induced increase in the hole population in LH bands is enhanced at higher Ns; the reduction in the hole population in LH bands due to the high-Ns-enhanced carrier confinement in the normal direction is larger in SG mode than in DG mode.

Experimental evidence of mobility enhancement in short-channel ultra-thin body double-gate MOSFETs by magnetoresistance technique

Double-gate transistor with ultra-thin body (UTB) has proved to offer advantages over bulk device for high-speed, low-power applications. There is thus a strong need to obtain an accurate understanding of carrier transport and mobility in such device. In this work, we report for the first time an experimental evidence of mobility enhancement in UTB double-gate (DG) MOSFETs using magnetoresistance mobility extraction technique. Mobility in planar DG transistor operating in single- and double-gate mode is compared. The influence of different scattering mechanisms in the channel is also investigated by obtaining mobility values at low temperatures. The results show a clear mobility improvement in double-gate mode compared to single-gate mode mobility at the same inversion charge density. This is explained by the role of volume inversion in ultra-thin body transistor operating in DG mode. Volume inversion is found to be especially beneficial in terms of mobility gain at low-inversion densities.

Low Temperature Properties of Multi-Independent-Gate FET (MIGFET) Operating in Single-Gate and Double-Gate Modes

We investigated the temperature dependence of the electrical properties of the MIGFETs, such as the drain current, the transconductance, the threshold voltage, the subthreshold slope and the field effect mobility. Devices with a gate length of 30 nm, a gate width of 30 nm and a silicon fin height of 100 nm were characterized at a temperature range between 77 K and room temperature. The MIGFETs were operated and compared in double- gate (DG) and single-gate (SG) modes in order to reveal the coupling effects between the various gates. The subthreshold slope in SG mode improves with decreasing temperature, but remains far from the ideal value measured in DG mode. The variations of the transconductance and mobility as a function of temperature are explained by strong coupling and series resistance effects. In DG mode, the mobility is highly improved due to volume inversion and reduced surface roughness scattering.

Short-Channel Effects in Independent-Gate FinFETs

A physics-based model is used to examine short-channel effects (SCEs) in undoped nanoscale independent-gate FinFETs, e.g., the MIGFET (L. Mathew, , Proc. IEEE Internat. SOI Conf., p. 187, 2004). Predicted current-voltage characteristics of MIGFETs in the single-gate mode show that the SCEs (threshold-voltage rolloff, subthreshold-swing degradation, and drain-induced barrier lowering) are actually less severe than those of the device in the double-gate mode. Insightful explanations of the results are given

Total dose effects on double gate fully depleted SOI MOSFETs

Total ionizing dose effects on fully-depleted (FD) silicon-on-insulator (SOI) transistors are studied when the devices are operated in single gate (SG) and double gate (DG) mode. The devices exhibit superiority in mobility and drain current when operated in DG mode compared to SG mode. Moreover, the dc characteristics of DG operated device are less vulnerable to total dose radiation induced damage. In particular, radiation-induced interface traps have less electrical effect in DG mode operation.

An experimental study of mobility enhancement in ultrathin SOI transistors operated in double-gate mode

In this paper, we report an experimental investigation of electron mobility in ultrathin SOI MOSFETs operated in double-gate mode. Mobility is measured for silicon thickness down to approximately 5 nm and for different temperatures. Mobility data in single- and double-gate mode are then compared according to two different criteria imposing either the same total inversion charge density or the same effective field in the two operating modes. Our results demonstrate that for silicon films around 10 nm or thinner and at small inversion densities, a modest but unambiguous mobility improvement for double-gate mode operation is observed even if the same effective field as in the single-gate mode is kept. Furthermore, we also document that the mobility in double-gate mode can improve markedly above single-gate mobility when the comparison is made at the same total inversion density. This latter feature of the double-gate operating mode can be very beneficial in the perspective of very-low voltage operation.

Ultimately thin double-gate SOI MOSFETs

The operation of 1-3 nm thick SOI MOSFETs, in double-gate (DG) mode and single-gate (SG) mode (for either front or back channel), is systematically analyzed. Strong interface coupling and threshold voltage variation, a large influence of substrate depletion underneath the buried oxide, the absence of drain current transients, and degradation in electron mobility are typical effects in these ultra-thin MOSFETs. The comparison of SG and DG configurations demonstrates the superiority of DG-MOSFETs: ideal subthreshold swing and remarkably improved transconductance (consistently higher than twice the value in SG-MOSFETs). The experimental data and the difference between SG and DG modes is explained by combining classical models with quantum calculations. The key effect in ultimately thin DG-MOSFETs is volume inversion, which primarily leads to an improvement in mobility, whereas the total inversion charge is only marginally modified.

Single-charge tunnelling in n- and p-type strained silicon germanium on silicon-on-insulator

Dual-gate quantum dot transistors have been fabricated in n- and p-type strained SiGe on silicon-on-insulator. In single-gate modes, the narrow and wide gates on opposing sides modulate the single-charge tunnelling events in the quantum dot. When both gates are coupled together, the resultant modulation implies that capacitive coupling via the substrate controls the tunnelling. The coupling causes constructive-destructive effects in lifting-restoring the Coulomb blockade condition in the SiGe quantum dots.