Single Flux Quantum Technology Research Articles

Harnessing stochasticity for superconductive multi-layer spike-rate-coded neuromorphic networks

Conventional semiconductor-based integrated circuits are gradually approaching fundamental scaling limits. Many prospective solutions have recently emerged to supplement or replace both the technology on which basic devices are built and the architecture of data processing. Neuromorphic circuits are a promising approach to computing where techniques used by the brain to achieve high efficiency are exploited. Many existing neuromorphic circuits rely on unconventional and useful properties of novel technologies to better mimic the operation of the brain. One such technology is single flux quantum (SFQ) logic—a cryogenic superconductive technology in which the data are represented by quanta of magnetic flux (fluxons) produced and processed by Josephson junctions embedded within inductive loops. The movement of a fluxon within a circuit produces a quantized voltage pulse (SFQ pulse), resembling a neuronal spiking event. These circuits routinely operate at clock frequencies of tens to hundreds of gigahertz, making SFQ a natural technology for processing high frequency pulse trains. This work harnesses thermal stochasticity in superconducting synapses to emulate stochasticity in biological synapses in which the synapse probabilistically propagates or blocks incoming spikes. The authors also present neuronal, fan-in, and fan-out circuitry inspired by the literature that seamlessly cascade with the synapses for deep neural network construction. Synapse weights and neuron biases are set with bias current, and the authors propose multiple mechanisms for training the network and storing weights. The network primitives are successfully demonstrated in simulation in the context of a rate-coded multi-layer XOR neural network which achieves a wide classification margin. The proposed methodology is based solely on existing SFQ technology and does not employ unconventional superconductive devices or semiconductor transistors, making this proposed system an effective approach for scalable cryogenic neuromorphic computing.

Side-Channel Leakage in SFQ Circuits and Related Attacks on Qubit Control and Readout Systems

Single flux quantum (SFQ) technology is currently used as a cryogenic control and readout circuitry of superconducting quantum computers. The low power operation and high switching frequency of SFQ technology are instrumental to efficiently scale a quantum computer. With the growing interest in the hardware security of SFQ circuits, a novel side-channel leakage mechanism in SFQ-to-DC converters is uncovered in this paper. The leakage mechanism is investigated for two logic styles, namely rapid SFQ (RSFQ) and energy-efficient RSFQ (ERSFQ). By observing the fluctuations in the power supply provided by the room temperature electronics, a malicious adversary can extract critical information about the applied input signals. This type of side-channel leakage can lead to serious security vulnerabilities for superconducting electronics and quantum computers. Two potential side-channel attacks that exploit this vulnerability and target SFQ-based qubit control and readout systems are proposed.

An RTL-to-GDSII Flow for Single Flux Quantum Circuits Based on an Industrial EDA Toolchain

Josephson Junction-based superconducting circuits are promising candidates for high-speed digital electronics with dramatically lower power consumption than CMOS, as well as a potential enabler towards the implementation of large-scale quantum computing. In this paper, we will describe an automated flow for the creation of microcontrollers and other digital systems in the single flux quantum (SFQ) technology. Starting with a register-transfer level (RTL) description of the circuit, the flow integrates logic synthesis, technology mapping, timing and logic verification, library cell placement and routing, and completes with a candidate physical design for fabrication. The flow makes use of the same tools employed in leading-edge CMOS. We will examine the challenges specific to the SFQ technology at the different stages in this flow. We will also report on metrics to qualify the resulting physical layout, such as circuit density and timing results.

Majorana bound state manipulation by current pulses

Majorana bound states (MBSs) can occur in Josephson junctions of conventional s-wave superconductors coupled via a strong topological insulator. In configurations of multiple line junctions meeting at a point, the criterion for the MBS to exist coincides with the presence of a fractional Josephson vortex with 2π phase winding. We investigate the dynamic stability of such vortices in arrays of tri- and quad-junctions. The existence of fractional vortices in arrays is demonstrated, but the dynamic stability is found to depend critically on the current-phase relation and the inductance. We propose the idea, and study the feasibility, of manipulating the location of the vortices in arrays by using current pulses, compatible with rapid single flux quantum technology. It is shown theoretically, using a modified resistively shunted junction model, that braiding operations can be achieved using current pulses injected from the edge of the array. It is necessary to use vortex sites with elevated critical current as traps.

Globally Asynchronous, Locally Synchronous Clocking and Shared Interconnect for Large-Scale SFQ Systems

A globally asynchronous, locally synchronous clocking scheme for large-scale single flux quantum (SFQ) systems is proposed. In this scheme, the width of each data bus is extended to carry the corresponding clock signal. This signal activates the distribution of the clock signals within the receiving block. Based on this approach for intra-chip interconnect within SFQ systems, a configurable shared bus is also proposed. The data are attached to a tag, and a resulting data packet is sent to the shared bus. This packet is received by each block, but only processed if the tag matches the block identifier. By avoiding expensive comparators and multiplexers, the overhead of the global bus connection is reduced. The proposed approaches exploit the pulse-based nature and ambiguity of clock and data in SFQ technology – the data packet propagating through the interconnect carries a local clock signal.

Design and test of component circuits of an integrated quantum voltage noise source for Johnson noise thermometry

We present design and testing of a pseudo-random number generator (PRNG) and a variable pulse number multiplier (VPNM) which are digital circuit subsystems in an integrated quantum voltage noise source for Jonson noise thermometry. Well-defined, calculable pseudo-random patterns of single flux quantum pulses are synthesized with the PRNG and multiplied digitally with the VPNM. The circuit implementation on rapid single flux quantum technology required practical circuit scales and bias currents, 279 junctions and 33mA for the PRNG, and 1677 junctions and 218mA for the VPNM. We confirmed the circuit operation with sufficiently wide margins, 80–120%, with respect to the designed bias currents.

A Reconfigurable Data-Path Accelerator Based on Single Flux Quantum Circuits

The single flux quantum (SFQ) is expected to be a nextgeneration high-speed and low-power technology in the field of logic circuits. CMOS as the dominant technology for conventional processors cannot be replaced with SFQ technology due to the difficulty of implementing feedback loops and conditional branches using SFQ circuits. This paper investigates the applicability of a reconfigurable data-path (RDP) accelerator based on SFQ circuits. The authors introduce detailed specifications of the SFQ-RDP architecture and compare its performance and power/performance ratio with those of a graphics-processing unit (GPU). The results show at most 1600 times higher efficiency in terms of Flops/W (floating-point operations per second/Watt) for some high-performance computing application programs. key words: single flux quantum, reconfigurable data-path, accelerator

A Statistical Approach to Delay, Jitter and Timing of Signals of RSFQ Wiring Cells and Clocked Gates

Rapid single flux quantum technology is one of the most promising developments for future high-speed microprocessors, network routers, and analog-to-digital converters. This technology is based on well-timed signals and fast signal transmission. However, as the complexity of the circuits or the operating frequency of these signals increase, it becomes harder to achieve a successful timing scheme. Another case that prevents successful timing is thermal noise, which becomes more significant with the increase of the number of cells. Earlier studies on noise analysis show that the timing variations of the delay on a cascaded path vary up to 10% compared with the delay of the same type of single cell. On the other hand, circuit parameters may change during the fabrication process, and as a result, timing of the cell differs from the design value. For these reasons, we define a statistical model for the wiring cells, such as Josephson transmission lines, splitters, and mergers that can be used to calculate the timing delay and jitter instead of time-consuming simulations. We also discuss a possible method to identify the sensitive paths to the delay fluctuations among different alternatives. In this study, we analyze the delay and the jitter of cascaded combinations of the most common wiring cells to determine the correlation effect on delay and jitter between the consecutive gates. Then, we propose a statistical method to analyze these timings faster and easier. Finally, we discussed how to estimate the output probability of the clocked gates without performing an actual simulation.

Direct Measurement of Jitter in a JTL

A direct technique for the measurement of jitter in a Josephson transmission line (JTL), which is similar to an approach used to measure complementary metal-oxide-semiconductor latch metastability, is presented. The experiment yields a one-sigma jitter value of 74 fs per JTL stage in 1 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> rapid single flux quantum technology. The experimental configuration has been modeled with JSIM, and the result agrees with the experimental data. Additionally, an analytical model has been developed to assess the scaling of the jitter-to-stage delay ratio with critical current density of the Josephson junctions comprising the JTL. Finally, we compare the measured upper bound jitter per stage of a 65-nm complementary metal-oxide-semiconductor inverter chain with that of a 1 kA/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> JTL.

Reading out the state of a flux qubit by Josephson transmission line solitons

We describe the readout process of the state of a Josephson flux qubit via solitons in Josephson transmission lines (JTLs) as they are in use in the standard rapid single flux quantum technology. We consider the situation where the information about the state of the qubit is stored in the time delay of the soliton. We analyze dissipative underdamped JTLs, take into account their jitter, and provide estimates of the measuring time and efficiency of the measurement for relevant experimental parameters.

Single-flux-quantum integer multiplier with systolic array structure

We propose an integer multiplier with systolic array structure for single-flux-quantum (SFQ) technology. Since SFQ logic circuits work by pulse logic, suitable circuit structure for SFQ logic circuits is different from one for semiconductor logic circuits. The systolic array is a circuit structure for VLSIs and consists of regularly arranged simple processing elements. All signals of the proposed systolic multiplier flow from input to output unidirectionally. This feature matches concurrent-flow clocking well. For evaluating the proposed systolic multiplier, we have designed a 4-bit systolic multiplier, as well as a 4-bit array multiplier which is one of the most typical parallel multipliers, and have compared them with each other. From the results of the design and the digital simulation, the number of Josephson junctions (JJs) of the 4-bit systolic multiplier is almost the half of that of the 4-bit array multiplier, and the latency of the former is about 1.5 times longer than that of the latter. Our estimation of the performance of larger-scale multipliers shows that the proposed systolic multiplier achieves comparable latency to the array multiplier, using extremely smaller number of JJs when the bit-width of input becomes large. We have fabricated a 1-bit cell of the systolic multiplier using NEC standard Nb process and have successfully tested it at low speed. The proposed systolic integer multiplier is attractive for SFQ technology.

Vision for single flux quantum very large scale integrated technology**This technology was exported from the United States in accordance with the USDepartment of Commerce Export Administration Regulations (EAR) for ultimatedestination in the United Kingdom. Diversion contrary to US law prohibited.

Single flux quantum (SFQ) electronics is extremely fast and has very low on-chip powerdissipation. SFQ VLSI is an excellent candidate for high-performance computing and otherapplications requiring extremely high-speed signal processing. Despite this, SFQ technologyhas generally not been accepted for system implementation. We argue that this is due, atleast in part, to the use of outdated tools to produce SFQ circuits and chips. Assuming theuse of tools equivalent to those employed in the semiconductor industry, we estimate thedensity of Josephson junctions, circuit speed, and power dissipation that could be achievedwith SFQ technology. Today, CMOS lithography is at 90–65 nm with about 20 layers.Assuming equivalent technology, aggressively increasing the current density above100 kA cm−2 to achieve junction speeds approximately 1000 GHz, and reducing device footprints by convertingdevice profiles from planar to vertical, one could expect to integrate about 250 M Josephson junctionscm−2 into SFQ digital circuits. This should enable circuit operation with clock frequencies above200 GHz and place approximately 20 K gates within a radius of one clock period. As aresult, complete microprocessors, including integrated memory registers, could befabricated on a single chip.

Progress of Single Flux Quantum Packet Switch Technology

With regard to sustaining future capacity of network traffic, the current hardware technology has a big bottleneck in terms of power consumption and insufficient operation speed. To overcome this bottleneck, we have developed a single flux quantum (SFQ) packet-switching circuit. We report recent progress in developing the SFQ packet-switching application. First, we demonstrate a 40 GHz, 160 Gb/s, 4 /spl times/ 4 packet switching circuit, which is currently the fastest clock frequency reported packet switch. Then, we describe a currently possible switching module using SFQ technology. Finally, we consider how SFQ technology can be used to scale the packet-switching capacity up to 100 Tbps.

High-Speed Demonstration of Single-Flux-Quantum Cross–Bar Switch up to 50 GHz

We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.

Application of single flux quantum technology to a next-generation photonic packet switch core

Internet traffic is still growing rapidly. Link capacity is easily increased by bundling optical fibers, but the packet switching capacity at a node is limited by the performance of a semiconductor switch facing problems of packaging density, operation speed, and power consumption. Photonic technology is therefore emerging from the link technology into the packet switch technology. A photonic packet switch can analyze the packet label optically and control optical switches, but packet scheduling must be done in the non-optical domain because photonic technology lacks arithmetic characteristics. Increases in the line speed and the number of ports will make this scheduling a bottleneck. Because single flux quantum (SFQ) circuits can operate at several tens of gigahertz, a speed comparable to optical link speed, they will be able to eliminate this bottleneck. To improve the performance of the nodes in the photonic network, we propose an SFQ-circuit-controlled optical packet switch core. Here we describe and discuss two photonic packet switch architectures using SFQ-circuit-controlled photonic switches.

Development of superconductor electronics technology for high-end computing

This paper describes our programme to develop and demonstrate ultra-high performance single flux quantum (SFQ) VLSI technology that will enable superconducting digital processors for petaFLOPS-scale computing. In the hybrid technology, multi-threaded architecture, the computational engine to power a petaFLOPS machine at affordable power will consist of 4096 SFQ multi-chip processors, with 50 to 100 GHz clock frequency and associated cryogenic RAM. We present the superconducting technology requirements, progress to date and our plan to meet these requirements. We improved SFQ Nb VLSI by two generations, to a 8 kA cm−2, 1.25 µm junction process, incorporated new CAD tools into our methodology, demonstrated methods for recycling the bias current and data communication at speeds up to 60 Gb s−1, both on and between chips through passive transmission lines. FLUX-1 is the most ambitious project implemented in SFQ technology to date, a prototype general-purpose 8 bit microprocessor chip. We are testing the FLUX-1 chip (5K gates, 20 GHz clock) and designing a 32 bit floating-point SFQ multiplier with vector-register memory. We report correct operation of the complete stripline-connected gate library with large bias margins, as well as several larger functional units used in FLUX-1. The next stage will be an SFQ multi-processor machine. Important challenges include further reducing chip supply current and on-chip power dissipation, developing at least 64 kbit, sub-nanosecond cryogenic RAM chips, developing thermally and electrically efficient high data rate cryogenic-to-ambient input/output technology and improving Nb VLSI to increase gate density.

Single flux quantum circuit technology innovation for backbone router applications

The performance of high-end routers will soon reach the limits of conventional technology. Single flux quantum (SFQ) digital technology is a key technology for achieving a breakthrough. We have already proposed a high-end router using SFQ technology. In this paper, we report on the latest innovation of SFQ router technology. First we describe a design methodology development. We have developed a new SFQ logic cell library for cell-based top-down circuit design. To expand the circuit scale further, a novel pseudo-automatic Josephson transmission line (JTL) routing technique has also been developed. And then, we discuss issues of passive interconnection, and show the operation of a passive transmission line interconnected circuit up to 40-Gbps throughput. Second we describe a packet switch circuit demonstration. We designed a 2 × 2 crossbar packet switch circuit, which is a key element in the packet switch. We successfully tested the circuit up to a clock frequency of 35 GHz. Finally we discuss an SFQ circuit application in the optical router as an alternative application strategy.

Rapid single flux quantum technology for SQUID applications

The rapid single flux quantum (RSFQ) mixed-signal technology offers a way to enhance performance and reduce complexity and cost of SQUID systems. Ultra-sensitive analog SQUID front ends can be combined with low-power and ultra-fast RSFQ digital circuits on a single chip to form mixed-signal circuits combining the sensitivity and noise level of an “analog SQUID” and the increased slew-rate, dynamic range, linearity, and simple multi-channel readout electronics of digital RSFQ circuits. We have developed several RSFQ-based circuits to perform sensing, digitization, and timing of various weak signals including outputs of detector arrays. The key enabling factor for the implementation of all these SQUID-RSFQ circuits is the availability of a high-yield, low-noise fabrication process.

A Large-Scale Packet Switch System and 60-Gbps Pulse Arbitration Circuit Operation Using Single Flux Quantum Technology

We evaluate the performance of a single flux quantum (SFQ) circuit and discuss its possible system-level application. First, we describe an optical-electrical-SFQ hybrid router system that is divided into three functions: an SFQ packet-routing function, a control function, and an optical transmission function. For the packet-switching core, we have developed a packet-switching architecture based on an internal speedup time-shifted Batcher Banyan approach. Our simulated results show that this architecture should provide good scalability and a low packet-loss rate. Additionally, we have fabricated an asynchronous pulse arbitration circuit. This circuit is a key component in our packet-switching system. The circuit synchronizes two asynchronous incoming signals without any global clock signals. It consists of a clock generator based on a ring oscillator and data latches. By measuring the average output voltage of the Josephson junction, we confirmed the output signal control by the clock at over 60 Gbps throughput.

A prospect for high-end information infrastruchture using single flux quantum technology

A prospect for high-end information infrastruchture using single flux quantum technology