Single-ended Signal Research Articles

A 30-60 GHz Broadband Low LO-Drive Down-Conversion Mixer with Active IF Balun in 65 nm CMOS Technology.

A 30~60 GHz broadband down-conversion mixer driven by low local oscillator (LO) power is presented. The down-conversion mixer utilizes an input signal coupling technique based on the Marchand balun to achieve broadband operation and achieves low LO power drive and low DC power consumption through the use of a weak inversion bias with Gilbert switching devices. The broadband conversion of single-ended to differential signals is achieved using the Marchand balun with compensation lines, and an equivalent circuit analysis is performed. For the intermediate frequency (IF) output, a self-biased IF trans-impedance amplifier with current reusing and an active IF balun structure are used to achieve signal amplification and single-ended signal output. Test results show that the proposed mixer achieves a conversion gain of -1.2 to 6.4 dB in an IF output bandwidth of 0.1 to 5 GHz at radio frequency (RF) input frequencies of 30 to 60 GHz and LO driving power of -10 dBm. The DC power consumption of the core mixing unit of the proposed mixer is 4.8 mW, and the DC power consumption including the IF amplifier is 28.3 mW. The proposed mixer uses a 65 nm CMOS technology with a chip area of 0.26 mm2.

Fault location in high-voltage direct-current grids based on panoramic voltage features and vision transformers

This paper presents a novel fault location method designed for high-voltage direct-current (HVDC) grids equipped with quick-action protections and circuit breakers. The method relies on a very short data window of single-ended voltage signals, which allows the acquisition of necessary measurements before the ultra-fast fault-isolation stage. Through fault analysis of the simulated four-terminal HVDC grid, it is observed that the fault distance induces a unique transient response in the voltage signal. However, due to the complex mathematical representation of loop components and the multiple fault factors involved, a data-driven strategy is adopted for fault distance estimation. Based on this strategy, four signal processing techniques, including Gramian angular field, recurrence plot, Markov transition field, and continuous wavelet transform, are used to extract panoramic voltage features. Additionally, four advanced lightweight variants of vision transformers (ViT), including MobileViT, EfficientFormer, Efficient-Model, and EdgeViT, are considered for constructing the regression model. The optimal combination of panoramic voltage features and regression models for configuring the locator is determined by statistical evaluation. The results of semi-physical experiments based on real-time digital simulators demonstrate that the proposed method, first, can accurately estimate the fault distance, second, possesses robustness against high transition resistance, low sampling frequency, and strong noise interference, and third, is practically feasible.

A 93.4-dB SNDR single-ended SAR ADC with a hybrid R–C DAC

In highly-integrated automatic test equipment (ATE) systems, the quantization process of single-ended analog signals demands high-precision ADCs. This paper presents a high precision single-ended SAR ADC with a hybrid R–C DAC. The proposed SAR ADC is demonstrated through sequential modeling in MATLAB, pre-layout and post-layout simulation. Designed in 0.18 μm BCD process, the post-layout simulation results show that it achieves a peak SNDR of 93.4-dB, a peak SFDR of 98.6-dB with a 250 kHz bandwidth. The power consumption of this SAR ADC is 5.96 mW with 5V supply. The Schreier Figure-of Merit (FoMSNDR) is 169.6-dB. The presented ADC is suitable for low-speed, high-precision ATE systems.

Electromagnetic Time Reversal Fault Location Method Based on Characteristic Frequency of Traveling Waves

In its application to locate ground faults, the electromagnetic time reversal (EMTR) method uses voltage from only a single point. However, when a high-impedance fault (HIF) occurs, the reflected signal from the fault point is weak, leading to an error between the simulated and actual fault location results. This paper proposes a new EMTR method based on the characteristic frequency of the traveling wave reflecting from the fault point. First, the transient signal spectrum under different fault resistances was analyzed, and the reasons for the inapplicability of the existing EMTR method under HIF conditions were discussed. Subsequently, a single-end signal expression with fault resistance was deduced, and the applicability of the EMTR method, which involves calculating only the energy of the fault current at the characteristic frequency, was verified. A reduced-scale experiment and a simulation in PSCAD were performed, and the EMTR method and proposed method were compared. The results showed that the proposed method can be applied to different complex lines, and it outperforms the conventional EMTR method in the event of HIFs.

A 0.85-pJ/b 16-Gb/s/Pin Single-Ended Transmitter With Integrated Voltage Modulation for Low-Power Memory Interfaces

A single-ended transmitter achieves low power consumption with an integrated voltage modulation (IVM) scheme for memory interfaces. The transmitter preserves the power advantages of the ground (VSS)-terminated single-ended signaling by consuming no static power when transmitting logic-0s before the last bit of consecutive logic-0s (CLZs). All the intersymbol interference (ISI) accumulated during CLZs is compensated at once by the proposed IVM, which provides the unit interval (UI) spaced compensation voltage during the period of the last logic-0. The equalization, combining four-tap IVM and two-tap pull-up feed-forward equalization (FFE), allows the transmitter to be energy efficient without degrading the compensation effect. Per-UI basis IVM also has better immunity to noise and process, supply voltage, and temperature (PVT) variations than conventional phase equalization and pulsewidth modulation. The compensation effect and power consumption of IVM are also mathematically analyzed and compared with other conventional equalizations. A prototype chip fabricated in 65-nm CMOS has an area of 0.0168 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$^{2}$</tex-math> </inline-formula> and achieves a data rate of 16 Gb/s/pin over a transmission channel with <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$-$</tex-math> </inline-formula> 12.6 dB loss, with an energy efficiency of 0.85 pJ/bit.

A 16-Gb/s/Wire 4-Wire Short-Haul Transceiver With Balanced Single-Ended Signaling (BASES) in 28-nm CMOS

This paper presents a 4-wire, 3-level, and 16-Gb/s/wire transceiver array for short-reach interconnects. The proposed transceiver adopts the balanced single-ended signaling (BASES) to reduce the simultaneous switching noise (SSN) and the electro-magnetic interference (EMI). The four transmit encoders and voltage-mode drivers produce three-level, common-mode-balanced, and multi-lane signals. The receive terminations and equalizers utilize the CM-balancing property of the BASES coding to recover the transmitted signals with a high noise rejection capability. The 4-wire transceiver was fabricated in a 28-nm CMOS technology and achieved a 64-Gb/s aggregate data rate with 3.15-pJ/bit energy efficiency.

A 0.38 V Fully Differential K-Band LNA with Transformer-Based Matching Networks

The implementation of a 0.38 V K-band low-power fully differential low-noise amplifier (LNA) in a 45 nm silicon-on-insulator (SOI) process is presented. The proposed architecture employs a two-stage approach with transformer-based interstage matching networks to minimize circuit area. The proposed LNA covers the frequency range from 20.3 to 24.1 GHz, it achieves a noise figure (NF) as low as 2.2 dB, and a gain of 12.9 dB, with a power consumption of 11.7 mW from a 0.38 V DC supply in a very compact area (0.15 mm2) excluding pads. Non-linearity simulations show the proposed circuit achieves a Po1dB of −7.3 dBm, and an OIP3 (Output Third Order Intercept) of 7 dBm. The transformers allow improved area use since they are simultaneously used as matching networks, RF chokes to bias the active devices, baluns at the input and output terminals to convert the single-ended signal into differential mode, and vice versa, and facilitates the interconnection with the upcoming stages. We used a state-of-the-art tool that generates the desired inductances to perform impedance matching for a given frequency and coupling factor value. A comparison with similar works proves the proposed LNA achieves a very low NF and the lowest power consumption reported in a differential circuit.

An 8b9b 77.44-Gb/s Noise-Immune Spatial-Delta Coded Transceiver for Short-Reach Memory Interfaces in 28-nm CMOS

A noise-immune spatial-delta coding (SDC) scheme is proposed for single-ended multi-lane links. The SDC technique allows differential sensing of single-ended PAM2 signals for high signal integrity while still achieving the same pin efficiency as the 8b9b data bus (DBI) scheme, providing high compatibility with conventional DDR interfaces. The SDC encoding/decoding functions are implemented with simple XOR gates to minimize power and latency overhead. Continuous-time linear equalizers in the receiver compensate for distortions in incoming pseudodifferential signals with high tolerance on dynamic common-mode switching associated with the SDC operation. An 8b9b SDC transceiver prototype array composed of nine data channels and a differential clock channel has been fabricated in 28-nm CMOS technology for demonstration. The transceiver array achieves a 77.44 Gb/s aggregate data rate with 9 wires at 9.68 Gbaud/s. The bit error rate is measured to be less than 1e-12 while consuming 4.9 pJ/b from a 1.25-V supply.

Suzuki Stack Circuit With Differential Output

Suzuki stack circuits, a type of latching high-voltage driver circuit, are widely used in Josephson–CMOS hybrid memories. The existing Suzuki stack designs utilize only single-ended signaling when connected to a CMOS amplifier. In this article, a Suzuki stack circuit with a differential output is proposed by producing both the positive and negative output voltages. The negative output voltage is produced by using a negative biasing network and a negative single-flux quantum (SFQ) input pulse, which is generated by the proposed positive-to-negative SFQ converter. As compared to a conventional single-ended Suzuki stack circuit, the proposed differential design can provide two times higher output voltage swing and better immunity to noise without degrading the operating margins. Potential advantages and drawbacks of the proposed circuit are explored in this article.

Overview of Common-Mode Noise Suppression Techniques: From Reflection to Absorption

Today’s fast-growing wireless communication technology has greatly increased the demand for the transmission of high-quality signals with high data rates. Because of its intrinsic advantages of high immunity to external noise, lower electromagnetic interference, harmonic suppression, and better linearity, differential signaling is preferable to single-ended signaling for many applications, including high-speed digital circuits, RF systems, and integrated circuits based on CMOS technology <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> <xref ref-type="bibr" rid="ref2" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[2]</xref> , <xref ref-type="bibr" rid="ref3" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[3]</xref> , <xref ref-type="bibr" rid="ref4" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[4]</xref> . However, in real-world circuit applications, differential signals are usually accompanied by destructive common-mode (CM) noise, which may be induced by asymmetric differential transmission paths with bending or length mismatch. On the other hand, imbalance of the differential signal channels, including amplitude swings and differences between rising and falling times, could also contribute to CM noise. In addition, the radiation emission caused by CM noise is much stronger than the differential signals, leading to a reduced system reliability <xref ref-type="bibr" rid="ref5" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[5]</xref> . Therefore, CM suppression has been an inevitable challenge for differential circuits and systems.

A 0.0022 mm² 10 bit 20 MS/s SAR ADC With Passive Single-Ended-to-Differential-Converter

This paper proposes a passive switched-capacitor single-ended-to-differential-converter (SDC) as a front-end of a differential SAR ADC, such that it can convert single-ended input signals. As the SDC is passive, the overall solution is power-efficient compared to active SDC solutions, and is especially suitable for lower/medium resolutions. As opposed to active SDC solutions with a static bias current, the proposed switched-capacitor network only consumes dynamic power, such that its consumption scales linearly with the sampling frequency. This paper discusses the basic concept of the proposed scheme, and analyzes the impact of noise and other imperfections, describes the trade-offs for power and area, and discusses the consequences for the input driver. A prototype implementation in 65nm CMOS achieves a figure-of-merit of 6.1fJ/conversion-step at 20MS/s, while reaching an SNDR of 54.7dB up to Nyquist and occupying a chip area of only <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$60~\mu \text{m}\,\,\times 36~\mu \text{m}$ </tex-math></inline-formula> .

Large Power Division Ratio Branch-Line Coupler With Differential Through and Differential to Single-Ended Coupling

This article presents a large power division ratio (PDR) branch-line coupler. The proposed coupler can realize the differential signal pass-through from the balanced-to-balanced ports and the single-ended signal coupling from the balanced to unbalanced ports. The authors demonstrate the proposed coupler using a microstrip circuit prototype with a PDR of 10 dB.

A Compact, Ultra-Wideband, Transformer-Based Quadrature Signal Generation Network in 45 nm CMOS SOI for 5G Applications

In this article, we present an ultra-wideband, fully-differential quadrature signal generation network for 5G applications. The ultra-wideband network is composed of a passive balun and cascaded transformer-based quadrature hybrid. Passive balun converts a single-ended signal to differential with minimum insertion loss, and transformer-based quadrature hybrids are cascaded to suppress I/Q imbalance over an ultra-wide bandwidth. The coupling coefficient of the transformer-based quadrature hybrid is enhanced by adopting vertically stacked multiturn transformer topology to extend operation bandwidth and reduce passive loss and chip area. A novel layout and signal routings are proposed to reduce passive loss, undesired magnetic coupling and I/Q imbalance, making meander lines for phase matching unnecessary. The proposed ultra-wideband quadrature signal generation network is designed in GlobalFoundries 45 nm CMOS SOI process with a core area of 845 μm × 495 μm. The output I/Q magnitude mismatch is less than 0.5 dB from 16 to 60 GHz, and phase mismatch is less than 2° from 16.5 to 54.7 GHz. The input return loss is lower than −10 dB from 22 to 45 GHz, and signal loss varies from 5.74 to 7.4 dB (including 1:2 power splitting and loss from passive balun). The effective image rejection ratio (IRR) is calculated based on I/Q mismatch and is higher than 40 dB from 21.5 to 53.5 GHz.

Fully Differential Current-Mode Configuration for the Realization of First-Order Filters with Ease of Cascadability

It is well known that fully differential signal processing is more advantageous than single-ended signal processing in a noisy environment, and is widely used in audio, video and other signal processing applications. This paper introduces a new fully differential configuration that contains a first-order low-pass (LP) filter, high-pass (HP) filter, and all-pass (AP) filter, all present within the same circuit design. The proposed fully differential configuration is simple and employs only one multiple-output current differencing transconductance amplifier and one grounded capacitor. The circuit has a wide operating frequency range (up to 73 MHz). The additional features offered by the proposed circuit include use of the lowest number of active and passive components, suitability of the integrated circuit chip, support of cascadability, electronic tunability, no passive component-matching restrictions, availability of all first-order responses, i.e., LP, HP, and AP, and low-level operating supply voltages. Non-ideal and parasitic analyses are investigated for the proposed circuit, and PSPICE simulation results are presented to verify the proposed theory. Additionally, the proposed fully differential LP filter circuit is experimentally verified using off-the-shelf ICs. Moreover, the cascading feasibility is demonstrated by realizing a fully differential nth-order LP filter.

Design and Performance Analysis of X-ray Photoelectric Collector for Logistics Transportation

The strong conveyor belt has been widely used in mines, ports, wharves, power plants, steel mills, and other fields. It is one of the main transportation equipment in modern production. In coal mine production, the logistics conveyor belt is essential equipment. The increased load can scratch and age the conveyor belt. Then, coupled with the elongation of joints, the equipment fails. This work designs an X-ray Photoelectric (XP) collector for logistics transportation and puts forward the design scheme. This work expounds on the hardware circuit of the XP collector, mainly based on the Image Capture Card (ICC) of the S8865 module and the serial/parallel data acquisition board based on the AD7667 chip. In the test, the Field Programmable Gate Array (FPGA) development tool ISE of Xilinx company is used to design the software of the XP collector to collect logistics X-ray signals. The oscilloscope analyzes the ICC control signal RESET, which repeatedly appears in a certain period. The S8865 module is controlled to collect X-ray signals continuously; the analog output signal of the S8865 module is observed. Under the control of a 1 MHz clock, the S8865 module outputs a stable analog signal. Similarly, observing the differential signal output of the differential processing circuit on the ICC through the oscilloscope finds that the differential signal is consistent with the original signal. Further positive input/output of the signal conditioning circuit of the serial/parallel data acquisition board is observed after the differential signal is switched. The single-ended signal after switching is consistent with the differential signal’s positive input signal.

A Cable Harness Routing Method Based on the Expected Maximum Crosstalk

With the increasing number of interconnected cables in electronic systems, the crosstalk between interconnected cables has played an important role in the intrasystem interference performance. However, the traditional routing method based on the shortest path cannot solve the problem of cable crosstalk. In this article, a novel cable harness routing method based on the expected maximum crosstalk is proposed. First, the closed-form expression for crosstalk based on the electrically small assumption is derived from the multiconductor transmission line (MTL) equation. According to this expression, the concept of maximum overlap length corresponding to the desired maximum crosstalk is developed. In addition, a conservative strategy is proposed to deal with higher frequency cable routing. The proposed routing method consists of the escape graph and the routing algorithm based on the maximum overlap length. A Dijkstra’s algorithm variant with the maximum overlap length as the constraint condition is proposed. The proposed method is applied to two single-ended and differential signals cable harness routing cases and compared with the traditional method to show that the routing results of the proposed method would keep the crosstalk between cable harness branches below the expected maximum crosstalk.

Design and Analysis of High-Gain and Compact Single-Input Differential-Output Low Noise Amplifier for 5G Applications

This letter describes the design, analysis, and testing of a 28-GHz single-input differential-output (SIDO) low-noise amplifier (LNA) with a noise figure of 2.5 dB, compact size (0.25 mm²), and high gain (22.3 dB). The proposed LNA was fabricated using the Taiwan Semiconductor Manufacturing Company (TSMC) 65-nm CMOS process. This amplifier contains a two-stage common-source (CS) buffer amplifier for a low-noise design and combines CS and common-gate transistors for converting single-ended signal into differential signal. A novel method of common-mode rejection ratio optimization is used to determine the optimal phase compensation transmission line and transistor size to reduce gain and phase imbalances simultaneously. The gain and phase imbalances were 0.042 dB and 2.6° at 28 GHz, respectively. Compared with published LNAs, this SIDO LNA achieved the high figure of merits (FoMs) of 7.17 and 2.27, respectively. Therefore, this LNA can be used for 5G NR band of n257 (26.5-29.5 GHz), n258 (24.25-27.5 GHz), and n261 (27.5-28.35 GHz).

Simultaneous switching noise mitigation in high speed pcb using novel planar EBG structure

ABSTRACT Electronic circuits must address electromagnetic interference due to high-speed transmissions and simultaneous switching actions. This paper proposes a design of novel planar EBG structure L Bridge with embedded slit type with 3 × 3 array fashion, which can be used in a plane layer of a printed circuit board to reduce simultaneous switching noise (SSN). Two sets of pattern such as alternate structure and entire embedded pattern are considered and measured the cut-off frequencies. The performance of the structure is simulated, experimentally verified using R&S®ZVH Vector Network Analyser for the frequency range 0.1 to 10 GHz and compared the outcomes. It is observed that for the −50 dB of noise depth, proposed structure is achieved 1.6 GHz to 10 GHz as lower and upper cut-off frequency. In addition, this concluded the noise suppression using equivalent circuit model and parallel plate wave guide theory. Signal integrity on this structure is also analysed with single-ended and differential mode signal transition. Eye pattern is generated and compared for measuring and validating the signal quality while using this EBG structure.

Single-Ended-to-Balanced Rat-Race Coupler With Wideband Common-Mode Suppression

This brief presents a novel design methodology for a single-ended-to-balanced (SETB) rat-race coupler. The proposed coupler relies on the slotted-microstrip star-junction; it exploits the characteristics of the slotline to form differential ports with high common-mode rejection ratio (CMRR), and wide common-mode (CM) and mode conversion rejection fractional bandwidths (FBWs), it benefits from the junction to realize miniaturized transmission lines (TLs), and, finally, it provides the single-ended signal through the microstrip ports. The proposed rat-race coupler has 32.5% and 31% 15-dB return loss (RL)/isolation and 3-dB FBWs, respectively, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.45\boldsymbol{\lambda } _{g} \mathbf {\times } 0.5\boldsymbol{\lambda } _{g}$ </tex-math></inline-formula> size, and 0.6 dB insertion loss (IL). The CMRR exceeds 40 dB at the operating frequency, while the CM as well as the mode conversion rejection FBWs exceed 375%. Measurements, which are in good agreement with EM and circuit simulations, confirm the theoretical predictions.

Research on RP-EDF amplification characteristics based on φ-OTDR system

Extending the sensing distance is of great significance for expanding the application of phase-sensitive optical time-domain reflectometry (φ-OTDR) in remote perimeter monitoring. Due to the inevitable fiber loss, the optical signal intensity decays exponentially with the length of the sensing fiber, and the sensing distance is greatly limited. In this study, a remote-pumped single-ended incident optical signal amplification scheme using erbium-doped fiber (EDF) is reported, and the factors affecting the amplification effect are comprehensively investigated. The experimental results show that the optimal amplification effect can be achieved when the input signal optical power is − 20 dB, the input signal optical wavelength is 1550 nm, the pump power is 100 mW and the erbium-doped fiber length is 10 m.