Single-core Processors Research Articles

High Level Model of Time Predictable Multitask Control Unit

The paper describes the high level abstract SystemC model of the multitask real time system. The authors put their main effort to obtain the highly time predictable system, The time predictability of real time embedded, electronic systems is identified and a concise survey of various approaches to the problem are given. The architecture of a single pipeline processor core with thread interleaving mechanism is emphasized. The scheduling algorithms that enable optimal utilization of the processing units are illustrated on examples. The main memory access control unit and the original memory system organization are described. Many simulation experiments conducted with single and multi-core system architecture implementation, allow obtaining results that prove advantages of the presented model.

Massive Image Treatment System Based on Cloud Computing Platform

Massive image processing technology requires high requirements of processor and memory, and it needs to adopt high performance of processor and the large capacity memory. While the single or single core processing and traditional memory can’t satisfy the need of image processing. This paper introduces the cloud computing function into the massive image processing system. Through the cloud computing function it expands the virtual space of the system, saves computer resources and improves the efficiency of image processing. The system processor uses multi-core DSP parallel processor, and develops visualization parameter setting window and output results using VC software settings. Through simulation calculation we get the image processing speed curve and the system image adaptive curve. It provides the technical reference for the design of large-scale image processing system.

Timing Verification of Fault-Tolerant Chips for Safety-Critical Applications in Harsh Environments

Critical real-time embedded systems (CRTES), which are deployed in cars, planes, and satellites, among other domains, feature increasingly complex safety-related, performance-demanding functionality. Realistically, such functionality can be provided by means of advanced (high-performance) hardware and software. This will inevitably shift CRTES from using simple control software running on in-order, single-core processors with no caches to complex multisensor and multiactuator software running on aggressive processors implemented in nanoscale technology deploying several computing cores and a cache hierarchy. However, the use of aggressive technologies and architectures challenges time predictability and reliability, which are mandatory features in CRTES. The authors present a processor design that reconciles all three goals--namely, predictability, reliability, and high performance. Their design obtains trustworthy and tight worst-case execution time (WCET) estimates for safety-critical applications running on high-performance hardware facing hard and soft errors by means of a smart use of timing-analysis techniques in combination with minor hardware modifications.

Parallelization Strategies for the GPS Radio Occultation Data Assimilation with a Nonlocal Operator in the Weather Research and Forecasting Model

Abstract The nonlocal excess phase observation operator for assimilating the global positioning system (GPS) radio occultation (RO) sounding data has been proven by some research papers to produce significantly better analyses for numerical weather prediction (NWP) compared to the local refractivity observation operator. However, the high computational cost and the difficulties in parallelization associated with the nonlocal GPS RO operator deter its application in research and operational NWP practices. In this article, two strategies are designed and implemented in the data assimilation system for the Weather Research and Forecasting Model to demonstrate the capability of parallel assimilation of GPS RO profiles with the nonlocal excess phase observation operator. In particular, to solve the parallel load imbalance problem due to the uneven geographic distribution of the GPS RO observations, round-robin scheduling is adopted to distribute GPS RO observations among the processing cores to balance the workload. The wall clock time required to complete a five-iteration minimization on a demonstration Antarctic case with 106 GPS RO observations is reduced from more than 3.5 h with a single processing core to 2.5 min with 106 processing cores. These strategies present the possibility of application of the nonlocal GPS RO excess phase observation operator in operational data assimilation systems with a cutoff time limit.

The Status and Challenges of Multi-Processor System-on-Chip’s Formal Verification

With the continuous advancement of processor manufacturing process as well as the exposed limitations of single-core Processors, Multi-Processor System-on-Chip (MPSoC) has become the inevitable outcome of the technological development and practical application needs. It is used to meet the requirements of multitasking, multifunctional and high performance computing. With the improvement of chip complexity, verification module also increases exponentially. Verification of MPSoC is becoming Bottleneck in the process of chip’s design. So this paper first introduces the origin of MPSoC, and analyzes developing tendency of its verification. And then, the theory and main challenges to the formal verification of MPSoC are discussed. This paper will provide support for building the verified theory method and technology that can meet the demand of MPSoC design, and Developing MPSoC high-level architecture design verification technology.

RCSoS: An IEC 61508 Compatible Server Model for Reliable Communication

In most cases of safety-related systems, the network is an indispensable part. At this point, the system reliability is as important as the system communication quality. With the emergence of multi-core architectures, the first generation usually aims to provide reliable and deterministic computing resources. Therefore, with the boost requirement of reliability and throughput that cannot be satisfied by general single-core processors, the deployment of safety-related systems is transferred and processed in multi-core environments. This paper proposes Reliable Communication Server on SPU (RCSoS), which is a server model for reliable communication utilizing SPU (Synergistic Processor Unit) in Cell/B.E. (Cell Broadband Engine). It simulates SPU as a communication server and guarantees the reliability and determinacy by the isolation mode of SPU and contract model. RCSoS has been implemented in PlayStation 3. It could dynamically adjust parameters, and inform applications on contract violations. The building process conforms IEC 61508, which guarantees the reliability of the life cycle. Besides, experiments show that the performance of this model is acceptable for the application requirements of network communication. And also the formal verification on the model theoretically guarantees the functional safety of the system.

Comparative Study of Parallel Programming Models to Compute Complex Algorithm

The main goal of this research is to use OpenMP, Posix Threads and Microsoft Parallel Patterns libraries to design an algorithm to compute Matrix Multiplication effectively. By using the libraries of OpenMP, Posix Threads and Microsoft Parallel Patterns Libraries, one can optimize the speedup of the algorithm. First step is to write simple program which calculates a predetermined Matrix and gives the results, after compilation and execution of the code. In this stage only single core processor is used to calculate the Matrix multiplication. Later on, in this research OpenMP, Posix Threads and Microsoft Parallel Patterns libraries are added separately and use some functions in the code to parallelize the computation, by using those functions multi-cores of a processor are allowed. Then execute the program and check its run time, then a timer function is added to the code which periodically checks the time it took for the computer to do the parallelization. First the program is run without the Parallel libraries, and then with the OpenMP, Posix Threads and with Microsoft Parallel Patterns libraries code. Then program is executed for each input Matrix size and result is collected. Maximum 5 trials for each input size are conducted and record the time it took for the computer to parallelize the Matrix multiplication. Finally comparison of the performance in terms of execution time and speed up for OpenMP, Posix Threads and Microsoft Parallel Patterns libraries is done using different Matrix Dimensions and different number of processors.

Cholesky-decomposed density MP2 with density fitting: accurate MP2 and double-hybrid DFT energies for large systems.

Our recently developed QQR-type integral screening is introduced in our Cholesky-decomposed pseudo-densities Møller-Plesset perturbation theory of second order (CDD-MP2) method. We use the resolution-of-the-identity (RI) approximation in combination with efficient integral transformations employing sparse matrix multiplications. The RI-CDD-MP2 method shows an asymptotic cubic scaling behavior with system size and a small prefactor that results in an early crossover to conventional methods for both small and large basis sets. We also explore the use of local fitting approximations which allow to further reduce the scaling behavior for very large systems. The reliability of our method is demonstrated on test sets for interaction and reaction energies of medium sized systems and on a diverse selection from our own benchmark set for total energies of larger systems. Timings on DNA systems show that fast calculations for systems with more than 500 atoms are feasible using a single processor core. Parallelization extends the range of accessible system sizes on one computing node with multiple cores to more than 1000 atoms in a double-zeta basis and more than 500 atoms in a triple-zeta basis.

Emulation and Analytical Model of PIM Supplemental Computing Element via HDL

Abstract This article presents and describes the simulation and emulation of single processing core, designed for new heterogeneous multiprocessor computer architectures with supplemental computing elements in the operating memory. We study the emulated results over the simulated model to confirm it’s usability in the overall simulation of complete system. The simulated models are developed based on existing data, comparing time markers, measuring the output performance against the results from the emulation. Using additional computing elements in the memory will allows us to improve the current limitations of the conventional architectures.

TH‐A‐19A‐04: Latent Uncertainties and Performance of a GPU‐Implemented Pre‐Calculated Track Monte Carlo Method

Purpose:Assessing the performance and uncertainty of a pre‐calculated Monte Carlo (PMC) algorithm for proton and electron transport running on graphics processing units (GPU). While PMC methods have been described in the past, an explicit quantification of the latent uncertainty arising from recycling a limited number of tracks in the pre‐generated track bank is missing from the literature. With a proper uncertainty analysis, an optimal pre‐generated track bank size can be selected for a desired dose calculation uncertainty.Methods:Particle tracks were pre‐generated for electrons and protons using EGSnrc and GEANT4, respectively. The PMC algorithm for track transport was implemented on the CUDA programming framework. GPU‐PMC dose distributions were compared to benchmark dose distributions simulated using general‐purpose MC codes in the same conditions. A latent uncertainty analysis was performed by comparing GPUPMC dose values to a “ground truth” benchmark while varying the track bank size and primary particle histories.Results:GPU‐PMC dose distributions and benchmark doses were within 1% of each other in voxels with dose greater than 50% of Dmax. In proton calculations, a submillimeter distance‐to‐agreement error was observed at the Bragg Peak. Latent uncertainty followed a Poisson distribution with the number of tracks per energy (TPE) and a track bank of 20,000 TPE produced a latent uncertainty of approximately 1%. Efficiency analysis showed a 937× and 508× gain over a single processor core running DOSXYZnrc for 16 MeV electrons in water and bone, respectively.Conclusion:The GPU‐PMC method can calculate dose distributions for electrons and protons to a statistical uncertainty below 1%. The track bank size necessary to achieve an optimal efficiency can be tuned based on the desired uncertainty. Coupled with a model to calculate dose contributions from uncharged particles, GPU‐PMC is a candidate for inverse planning of modulated electron radiotherapy and scanned proton beams.This work was supported in part by FRSQ‐MSSS (Grant No. 22090), NSERC RG (Grant No. 432290) and CIHR MOP (Grant No. MOP‐211360).

Improved cache utilization and preconditioner efficiency through use of a space-filling curve mesh element- and vertex-reordering technique

Solving partial differential equations using finite element (FE) methods for unstructured meshes that contain billions of elements is computationally a very challenging task. While parallel implementations can deliver a solution in a reasonable amount of time, they suffer from low cache utilization due to unstructured data access patterns. In this work, we reorder the way the mesh vertices and elements are stored in memory using Hilbert space-filling curves to improve cache utilization in FE methods for unstructured meshes. This reordering technique enumerates the mesh elements such that parallel threads access shared vertices at different time intervals, reducing the time wasted waiting to acquire locks guarding atomic regions. Further, when the linear system resulting from the FE analysis is solved using the preconditioned conjugate gradient method, the performance of the block-Jacobi preconditioner also improves, as more nonzeros are present near the stiffness matrix diagonal. Our results show that our reordering reduces the L1 and L2 cache miss-rates in the stiffness matrix assembly step by about 50 and 10 %, respectively, on a single-core processor. We also reduce the number of iterations required to solve the linear system by about 5 %. Overall, our reordering reduces the time to assemble the stiffness matrix and to solve the linear system on a 4-socket, 48-core multi-processor by about 20 %.

Design of Multi-core Processor Software with Pipelining Strategy

At present, in the field of application of numerous IT, multi-core processors are widely used, the hardware development is much faster than the speed of software development. Multi-core processor software is using the design concept of single-core processor software, so this software is not high-performance and the performance processor is not fully played. This paper firstly introduces the traditional software design method based on multiple cores, and then points out two problems existing in it.To improve its efficiency, I propose a method called pipeline which can improve processor utilization and the throughput of a processor, at the same time, reduce the cost of the system. This method has been verified in the network packet processing. DOI : http://dx.doi.org/10.11591/telkomnika.v12i4.4811

Pre-treatment radiotherapy dose verification using Monte Carlo doselet modulation in a spherical phantom

Due to the increasing complexity of radiotherapy delivery, accurate dose verification has become an essential part of the clinical treatment process. The purpose of this work was to develop a pre-treatment verification technique capable of quickly reconstructing 3D dose distributions from both coplanar and non-coplanar treatments. For each treatment field, electronic portal images were taken in non-transmission mode (with no patient in the beam) allowing the derivation of the delivered fluence maps. The dose reconstruction was then performed in a spherical water phantom by modulating and summing the Monte Carlo (MC) doselets, defined on a spherical co-ordinate system, and pre-calculated from azimuthally symmetric fluence above the jaws. The technique, called the spherical doselet modulation (SDM) method, essentially eliminates the statistical uncertainty of the MC dose calculations by exploiting the azimuthal symmetry in both a patient-independent phase-space and in a virtual spherical water phantom. For example, this symmetry allowed the number of doselets necessary for dose reconstruction to be reduced by a factor of ∼250. In this work, only 51 radially binned doselets were used (each generated from all particles in a given annulus of the phase-space, azimuthally redistributed into a small cylindrical sector). The SDM method mitigates the most computationally intensive part of this type of dose reconstruction-–reading, weighting and summing dose matrices. The accuracy of the system was tested against MC calculations as well as our previously reported phase-space modulation method, using a series of open field and IMRT cases. The mean chi- and gamma-test 3%/3 mm success rates of the SDM method were 98.6% and 99.5%, respectively, when compared to full MC simulation. The total calculation time was 96 s per treatment field on a single processor core.

An Architecture for Measuring Network Performance in Multi-Core Multi-Cluster Architecture (MCMCA)

The aim of this research is to design a new architecture for large-scale clusters to improve the communication within the interconnection network to gain higher performance. The new architecture will be based on clusters built using workstations containing multi cored processors in a multi-cluster architecture in the presence of uniform traffic. Multi-core technology is proposed to achieve higher performance without driving up power consumption and heat, which is the main concern in a single-core processor. The architecture will avoid congestion and deadlocks in the network to guarantee faster message transmission. The architecture performance will be validated through simulation, experimental and measurements under various working conditions.

LaBonte's method revisited: An effective steepest descent method for micromagnetic energy minimization

We present a steepest descent energy minimization scheme for micromagnetics. The method searches on a curve that lies on the sphere which keeps the magnitude of the magnetization vector constant. The step size is selected according to a modified Barzilai-Borwein method. Standard linear tetrahedral finite elements are used for space discretization. For the computation of quasistatic hysteresis loops, the steepest descent minimizer is faster than a Landau-Lifshitz micromagnetic solver by more than a factor of two. The speed up on a graphic processor is 4.8 as compared to the fastest single-core central processing unit (CPU) implementation.

Parallel Implementation of Color Based Image Retrieval Using CUDA on the GPU

Most image processing algorithms are inherently parallel, so multithreading processors are suitable in such applications. In huge image databases, image processing takes very long time for run on a single core processor because of single thread execution of algorithms. Graphical Processors Units (GPU) is more common in most image processing applications due to multithread execution of algorithms, programmability and low cost. In this paper we implement color based image retrieval system in parallel using Compute Unified Device Architecture (CUDA) programming model to run on GPU. The main goal of this research work is to parallelize the process of color based image retrieval through color moments; also whole process is much faster than normal. Our work uses extensive usage of highly multithreaded architecture of multi-cored GPU. An efficient use of shared memory is needed to optimize parallel reduction in CUDA. We evaluated the retrieval of the proposed technique using Recall, Precision, and Average Precision measures. Experimental results showed that parallel implementation led to an average speed up of 6.305×over the serial implementation when running on a NVIDIA GPU GeForce 610M. The average Precision and the average Recall of presented method are 53.84% and 55.00% respectively.

Analysis of dependence tracking algorithms for task dataflow execution

Processor architectures has taken a turn toward many-core processors, which integrate multiple processing cores on a single chip to increase overall performance, and there are no signs that this trend will stop in the near future. Many-core processors are harder to program than multicore and single-core processors due to the need for writing parallel or concurrent programs with high degrees of parallelism. Moreover, many-cores have to operate in a mode of strong scaling because of memory bandwidth constraints. In strong scaling, increasingly finer-grain parallelism must be extracted in order to keep all processing cores busy. Task dataflow programming models have a high potential to simplify parallel programming because they alleviate the programmer from identifying precisely all intertask dependences when writing programs. Instead, the task dataflow runtime system detects and enforces intertask dependences during execution based on the description of memory accessed by each task. The runtime constructs a task dataflow graph that captures all tasks and their dependences. Tasks are scheduled to execute in parallel, taking into account dependences specified in the task graph. Several papers report important overheads for task dataflow systems, which severely limits the scalability and usability of such systems. In this article, we study efficient schemes to manage task graphs and analyze their scalability. We assume a programming model that supports input, output, and in/out annotations on task arguments, as well as commutative in/out and reductions. We analyze the structure of task graphs and identify versions and generations as key concepts for efficient management of task graphs. Then, we present three schemes to manage task graphs building on graph representations, hypergraphs , and lists . We also consider a fourth edgeless scheme that synchronizes tasks using integers. Analysis using microbenchmarks shows that the graph representation is not always scalable and that the edgeless scheme introduces least overhead in nearly all situations.

Analysis of dependence tracking algorithms for task dataflow execution

Processor architectures has taken a turn toward many-core processors, which integrate multiple processing cores on a single chip to increase overall performance, and there are no signs that this trend will stop in the near future. Many-core processors are harder to program than multicore and single-core processors due to the need for writing parallel or concurrent programs with high degrees of parallelism. Moreover, many-cores have to operate in a mode of strong scaling because of memory bandwidth constraints. In strong scaling, increasingly finer-grain parallelism must be extracted in order to keep all processing cores busy.

A DSP-Based HEVC decoder implementation using an actor language dataflow model

During the last decades, new video compression standards arose every few years with always higher compression gains and considerable increases on the computational cost. Single core processors have reached their limit and multicore processors are there to overcome this issue to give more processing power. In order to accelerate the implementation of new video coding standards, MPEG has standardized an alternative framework to describe video decoders. It is based on reference decoders written in the RVC CAL dataflow actor language. From these descriptions, a compiler - Open RVC CAL compiler (Orcc) - allows the automatic generation of C code dedicated to the target processor. In this paper, a DSP based decoder compliant with the new High Efficiency Video Coding (HEVC) standard has been implemented using a CAL RVC model as a starting point. This is the first implementation of an HEVC decoder with DSP technology based on a HEVC RVC CAL model. The decoder has been compared in performance with a GPP implementation, also based on the RVC CAL model, and outperforms it by more than 50%. Additionally, the performance of this decoder is compared with that of other DSP-based HEVC decoders implemented without using the Orcc infrastructure1.

Methods to explore design space for MPEG RMC codec specifications

The recent MPEG Reconfigurable Media Coding (RMC) standard aims at defining media processing specifications (e.g. video codecs) in a form that abstracts from the implementation platform, but at the same time is an appropriate starting point for implementation on specific targets. To this end, the RMC framework has standardized both an asynchronous dataflow model of computation and an associated specification language. Either are providing the formalism and the theoretical foundation for multimedia specifications. Even though these specifications are abstract and platform-independent the new approach of developing implementations from such initial specifications presents obvious advantages over the approaches based on classical sequential specifications. The advantages appear particularly appealing when targeting the current and emerging homogeneous and heterogeneous manycore or multicore processing platforms. These highly parallel computing machines are gradually replacing single-core processors, particularly when the system design aims at reducing power dissipation or at increasing throughput. However, a straightforward mapping of an abstract dataflow specification onto a concurrent and heterogeneous platform does often not produce an efficient result. Before an abstract specification can be translated into an efficient implementation in software and hardware, the dataflow networks need to be partitioned and then mapped to individual processing elements. Moreover, system performance requirements need to be accounted for in the design optimization process. This paper discusses the state of the art of the combinatorial problems that need to be faced at this design space exploration step. Some recent developments and experimental results for image and video coding applications are illustrated. Both well-known and novel heuristics for problems such as mapping, scheduling and buffer minimization are investigated in the specific context of exploring the design space of dataflow program implementations.