Single-chip Transceiver Research Articles

Space Environment Evaluation and Low-Earth-Orbit Demonstration of a Communication Component with a Commercial Transceiver Integrated Circuit

A software-controllable, consumer-grade, single-chip transceiver integrated circuit (IC) has multiple applications because it can generate a continuous-wave beacon while providing the basic functions of frequency shift keying digital communication as well. In addition, such ICs are low-cost. The above characteristics are advantageous for CubeSats with limited space and for university satellites with development cost constraints. In this study, we conduct radiation tolerance evaluation and Doppler shift tolerance tests to evaluate the feasibility of a single-chip consumer transceiver IC for space applications. In the radiation tolerance evaluation test, we compare the IC radiation tolerance to that of a single-chip microcomputer implemented in space and confirm the good resistance of the former based on the predictive analysis of the single-event upset incidence. Through the Doppler frequency shift tolerance test, we confirm suitable receiving sensitivity. Furthermore, we develop a transceiver IC as a CubeSat-class satellite component and successfully establish communication in an in-orbit demonstration, where the transceiver IC is employed as a CubeSat communication module released from the International Space Station. Thus, the feasability of space utilization of the consumer communication IC is demonstrated, which has implications for the development of more flexible and challenging system designs using newly introduced consumer devices.

A 24-GHz Fully Integrated CMOS Transceiver for FMCW Radar Applications

A 24-GHz fully integrated frequency-modulated continuous wave (FMCW) direct conversion transceiver, implemented in a 55-nm low-power CMOS technology with a maximum <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$f_{\mathrm {T}}$ </tex-math></inline-formula> of 190 GHz in typical operating conditions and packaged in a 5-mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times $ </tex-math></inline-formula> 5-mm 32-lead quad-flat no-leads (QFN) package, is presented in this article. The single-chip transceiver uses a single 2.5-V supply while all the core circuits are powered by integrated regulators. The complex low-noise transductor in the receiver uses a quadrature hybrid to generate quadrature signals in the receiving front-end. The analog signal processing circuits including high-pass filters, low-pass filters, and programmable amplifiers are implemented following the receiver front-end circuitry. The FMCW signals are generated by an on-chip 24-GHz fractional-N frequency synthesizer. The synthesizer is completely integrated with the transceiver and provides built-in digital frequency modulation to generate chirping signals for the down-conversion local oscillator (LO) and the transmitted signals. The transmitter is composed of a balanced class-AB power amplifier driven by the FMCW signals from the frequency synthesizer.

A Sub-6-GHz 5G New Radio RF Transceiver Supporting EN-DC With 3.15-Gb/s DL and 1.27-Gb/s UL in 14-nm FinFET CMOS

The world’s first single-chip RF transceiver to support 5G sub-6-GHz new radio (NR) and long-term evolution (LTE) E-UTRA New Radio-Dual Connectivity (EN-DC) in 14-nm FinFET CMOS technology is presented. The single-chip transceiver integrates identical primary and diversity receivers (RXs) with seven pipelines for supporting four inter-band carrier aggregation (CA) with three 4 $\times $ 4 MIMO, two independent transmitter (TX) chains, eight frequency synthesizers for RX and TX, and on-chip digitally controlled crystal oscillator (DCXO) to reduce the phase noise and bill of material (BOM) cost. The receiver features 12 single-ended low-noise amplifiers (LNAs) with wideband characteristics. With the help of the proposed pipeline structure and frequency-band switchable transformer, the die size can be reduced despite covering the whole frequency range from 2G to sub-6-GHz 5G NR. It achieves the noise figure (NF) from 6.5 to 9.3 dB, +3-dBm out-of-band (OOB) IIP3, more than +70-dBm OOB IIP2 after calibration. For the transmitter, low RX-band noise and harmonic suppression technique are applied to support surface acoustic wave (SAW)-less architecture, and the bandwidth control of the baseband filter is implemented for the digital pre-distortion (DPD) operation of 100-MHz BW in NR transmit data. The measured error vector magnitudes (EVMs) in 4G and 5G bands of n79 are −39.5 dB at +4-dBm output power and −33.9 dB at +3.06-dBm output power, respectively, and the measured RX-band noise of 2G is −163 dBc at 20-MHz offset. The RX consumes 18 mW at LTE 1-CA mode and the TX consumes 350 mW at n79.

The analysis of the single-crystal transceivers work in the range of ISM for IoT systems

The article discusses the features of transceivers for IoT systems. IoT systems are used in areas such as medicine, security, industrial automation, intelligent networks, remote control facilities, engineering and security systems of buildings. These applications require highly integrated transmission and reception components that can provide low power consumption for longer life, high probability data transfer, ability to operate in the unlicensed frequency range, simplicity and reliability of operation, scalability without significant additional costs and compliance with international standards. Analog Devices ADIsimSRD Design Studio is a very powerful tool allowing real-time simulation and optimization of many of the parameters in a typical wireless system using the ADF7xxx family of transceivers and transmitters. By modeling in the ADIsimSRD Design Studio software, the operation of the single-chip transceiver ADF7023 was analyzed. The ADF7023 is a very low power, high performance, highly integrated transceiver designed for operation in the 862 MHz to 928 MHz and 431 MHz to 464 MHz frequency bands, which cover the worldwide license-free ISM bands at 433 MHz, 868 MHz, and 915 MHz. It is suitable for circuit applications that operate under the European ETSI EN300-220, the North American FCC, the Chinese short-range wireless regulatory standards, or other similar regional standards. Data rates from 1 kbps to 300 kbps are supported. The range of subsystems to be considered in the development process include RF filtering/matching, modulation type and demodulation process, packet data formatting, and average power consumption. Until now, system designers relied on a combination of spreadsheet-based tools and iterative lab work to help with the optimization of these parameters. Based on the analysis, recommendations were made on the choice of transmitter parameters for the implementation of IoT systems using Analog Devices chips. Due to low energy consumption, high integration, ability to operate in the unlicensed ISM frequency range, high probability and speed data transfer capabilities, module programming capabilities, compliance with international standards, Analog Devices transceivers can be used in wireless IoT communications systems. To ensure a good communication range and a high probability of information transfer, it is advisable to use the most noise-resistant GFSK modulation method, which provides the most energy-efficient narrow signal spectrum.

A power detector based on GaN high-electron-mobility transistors for a gigabit on–off keying demodulator at 90 GHz

This study analyzes the mechanism behind signal demodulation in GaN high-electron-mobility transistors, finding the relationship between gate bias voltage and relative amplitude of the output voltage. The optimal gate bias for maximum responsivity has been analytically found. The responsivity of the GaN demodulator at different biases has been characterized using an on–off keying signal with a 90 GHz carrier. Furthermore, from the measured eye diagram it is observed that the GaN demodulator can demodulate a signal with a maximum data rate up to a 1.28 gigabits per second. This study presents a promising method for integrating a GaN demodulator into a single-chip GaN transceiver.

A single-chip integrated transceiver for high field NMR magnetometry.

We present the design and performance of a broad-band single-chip integrated transceiver specifically conceived for nuclear magnetic resonance magnetometry. The single-chip transceiver is realized using a standard silicon complementary metal-oxide-semiconductor integrated circuit technology. A radio-frequency (RF) transmit amplifier, a transmit/receive switch, a low noise RF receive amplifier, a quadrature (IQ)-mixer, and two intermediate frequency amplifiers are integrated on a single silicon chip of 1.8 mm2. The advantages and problematic aspects with respect to conventional discrete electronic approaches are discussed. We show the results of magnetic field measurements performed at 1.4 and 7.05 T, using solid and liquid samples having volumes from 40 μl down to 100 pl. Particular attention is devoted to the comparison of the experimentally measured magnetic field standard deviation with respect to the Cramer-Rao lower bound value. With a sample of distilled water (T1 ≅ T2 ≅ 3 s, T2 *≅ 20 ms) having a volume of 40 μl, a standard deviation of 2.5 nT at 7.05 T (i.e., 0.5 ppb) in 1 s of averaging time is achieved, with a projected Cramer-Rao lower bond of 8 pT (i.e., 1.1 ppt).

A Portable Phase-Domain Magnetic Induction Tomography Transceiver with Phase-Band Auto-Tracking and Frequency-Sweep Capabilities.

This paper presents a portable magnetic induction tomography (MIT) transceiver integrated circuit to miniaturize conventional equipment-based MIT systems. The miniaturized MIT function is enabled through single-chip transceiver implementation. The proposed MIT transceiver utilizes a phase-locked loop (PLL) for frequency sweeping and a phase-domain sigma–delta modulator with phase-band auto-tracking for a full-range fine-phase resolution. The designed transceiver is fabricated and verified to achieve the measured signal to noise and distortion ratio (SNDR) of 101.7 dB. Its system-level prototype including in-house magnetic sensor coils is manufactured and functionally verified for four different material types.

Fully Integrated Single-Chip 305–375-GHz Transceiver With On-Chip Antennas in SiGe BiCMOS

A fully integrated single-chip transceiver (TRX) with on-chip antennas for transmitting and receiving signals within a continues frequency range from 305 to 375 GHz is presented. The radio-frequency (RF) and local oscillator signals are generated using a wideband push–push voltage-controlled oscillator, a three-stage power amplifier, and a frequency doubler. A heterodyne receiver using a fundamental mixer converts the received RF signal to an intermediate frequency (IF) signal, which drives an IF amplifier. Additionally, a divide-by-64 frequency divider is integrated to provide a low-frequency output for measurement purposes and to enable later the addition of a phase-locked loop for frequency stabilization and synthesis. A 130-nm silicon–germanium BiCMOS process with $f_t/f_{\max}$ = 250 GHz/370 GHz is used. The TRX chip is wire bonded to a printed circuit board and a TPX (Polymethylpentene) lens is placed on top of the chip for focusing the radiation. At a frequency of 343 GHz, the measurements show an effective isotropic radiated power of 18.4 dBm, a phase noise of $-$ 79 dBc/Hz@1 MHz, and an IF conversion gain of 28 dB. The obtained tuning bandwidth of 70 GHz is the highest reported so far for fully integrated TRXs.

A Fully Integrated 300-MHz Channel Bandwidth 256 QAM Transceiver With Self-Interference Suppression in Closely Spaced Channels at 6.5-GHz Band

We present a fully-integrated 256 QAM single-chip transceiver (TRX) with 300-MHz channel bandwidth at the 6.5-GHz band. A novel architecture for self-interference suppression (SIS) is proposed. A noise-canceling low-noise amplifier with the embedded programmable source degeneration network based on the bond wires, manifesting the notch filtering characteristics of the self-interference signal, has been utilized to facilitate the SIS, and LC -tuned tanks further improve the interference filtering in a receiver (RX) and considerable adjacent channel leakage power ratio in a transmitter (TX). The SAW-less /duplexer-less TRX allows TDD/FDD co-operation in closely spaced channels. The RX achieves a noise figure (NF) as low as 3 dB with +17.5-dBm out-of-band IIP3. The EVM is 2.02% and 2.72% for the RX and TX, respectively, in 160-MHz bandwidth OFDM 256 QAM. In the SIS mode, the blocker P1dB is −8 dBm, and the NF of the RX degrades only 2.1 dB (from 3.0 to 5.1 dB), withstanding 0-dBm interference at 150-MHz offset. The TRX exhibits a slight EVM degradation (from 2.02% to 2.98%) when receiving a −40-dBm 160-MHz bandwidth 256 QAM desired signal, in the presence of a −15-dBm 80-MHz bandwidth self-interference signal at 300-MHz offset. The TRX has been implemented in 0.13- $\mu \text{m}$ CMOS with superior overall performances.

A 2.4-GHz Ternary Sequence Spread Spectrum OOK Transceiver for Reliable and Ultra-Low Power Sensor Network Applications

The ON/OFF keying (OOK) transmitter is re-investigated to utilize its structural simplicity and low power features for the reliable, ultra-low power sensor network applications. A novel architecture of 2.4-GHz ternary sequence spread spectrum (TSSS) OOK transceiver with spreading gain, spur suppression, and dual-mode detection techniques is presented. A random bi-phase operation of a power amplifier rejects the intrinsic spur of spread spectrum OOK transmitter by 22 dB. A proposed TSSS-OOK transmitter supports a variable spread spectrum, such as 1 b to 4 chips (1/4), 3/8, and 5/32 and a dual reception of the coherent as well as non-coherent mode, achieving 12-dB SNR gain. For the power optimized frequency synthesis, both a phase locked loop (PLL) and a frequency locked loop (FLL) are merged with a single voltage controlled oscillator as a dual-precision frequency synthesizer, where the high-precision PLL is activated for the coherent reception and the low power, moderate precision FLL is activated for the non-coherent reception. The single-chip transceiver in 90-nm CMOS occupies an active area of 2.4 mm2 and measures 1Mb/s, 22-dB spur-suppressed output spectrum, 5.5% EVM, and a sensitivity of −81 dBm at non-coherent mode and −93 dBm at coherent mode, dissipating 2.17 mW at TX and 0.614 mW at RX.

A Single-Chip Wireless Powered RFID Antenna and Transceiver

Design, post-processing, and characterization of a dust-size (0.46 mm2) single-chip wireless transceiver suitable for RFID and sensing applications are presented. The fully integrated system is fabricated in GlobalFoundries 45-nm CMOS SOI technology and integrates a miniature on-chip slot antenna, a power harvesting and management module, a modem with backscattering transmission, a clock generator and a digital control and memory unit. The chip consumes on average only 68 ${\mu }\text{W}$ of power under 0.9-V supply voltage (114 ${ \mu }\text{W}$ under 1 V) provided by a horn antenna radiating 1 W RF power at 950 MHz at a distance below 16 cm. A novel post-CMOS fabrication technique is used to release the system from its handle silicon substrate for ultimate miniaturization leading to the smallest volume (<0.005 mm3) wireless transceiver reported to date with relatively low power.

3D package-integrated artificial magnetic conductor antenna arrays for 60 GHz transceivers

We present a low-profile design of dipole antenna arrays integrated on a planar artificial magnetic conductor (AMC) based on spiral unit cells. The whole system is designed and manufactured on a multi-layer organic laminate packaging technology and can be integrated with a single-chip 60-GHz radio transceiver die. We analyze two fabricated arrays of different total area both of which contain 16 elements fed through a combiner network exciting the array elements either in phase or for 45° scan angle. The integrated antenna-AMC array element presented has twice the impedance bandwidth necessary to cover all international 60-GHz radio bands, small form factor suitable for on-package integration, and 5 dBi gain including all losses. The larger 16-element array, occupying 11 × 11 mm2 package area, has a measured gain of 17 dBi at broadside and 15 dBi at 45° scan angle, while the smaller array, occupying a 6.6 × 11 mm2 package area, has a gain of 15 dBi at broadside and 14 dBi at a 45° scan angle. These arrays are an ideal 3D-integrated package solution for 60 GHz radio transceivers.

A Full-Duplex Single-Chip Transceiver With Self-Interference Cancellation in 0.13 &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$\mu$ &lt;/tex-math&gt; &lt;/inline-formula&gt;m SiGe BiCMOS for Electron Paramagnetic Resonance Spectroscopy

This paper presents a miniaturized EPR spectrometer based on a single-chip transceiver. Utilizing a novel on-chip self-interference cancellation circuit, the electromagnetic coupling from the transmitter (TX) to the receiver (RX) is minimized, allowing simultaneous achievement of large TX output power and low RX noise figure (NF). In the measurement, the RX achieves a NF of 3.1 dB/6.3 dB at 10 MHz/50 kHz baseband frequencies, when the TX and cancellation circuits are turned off. The measured flicker noise corner is 60 kHz, more than $10\times $ lower than the prior work. Moreover, for the first time, the operation of the RX and cancellation circuit is demonstrated when a co-integrated TX is operating at the same time and frequency, while producing >20 dBm output power. When the TX and cancellation circuits are turned on, at −10 dBm interference power, the measured NF is 6.8 dB/11.1 dB at 10 MHz/50 kHz baseband frequencies. This is lower by 5.6 dB/9.6 dB at 10 MHz/50 kHz baseband frequencies, compared to the NF with the cancellation circuit off at the same interference power. The transceiver chip is implemented in IBM $0.13~\mu \text {m}$ BiCMOS process and consumes a power of 2 W. Utilizing this transceiver, an electron paramagnetic resonance (EPR) spectrometer is built and tested. It is observed, through measurement, that the interference cancellation circuit increases the signal-to-noise ratio (SNR) of the EPR signal by 7 dB at −10 dBm interference power. Compared to prior work, the reported EPR spectrometer improves the sensitivity of the system by 25 dB.

55-nm SiGe BiCMOS Distributed Amplifier Topologies for Time-Interleaved 120-Gb/s Fiber-Optic Receivers and Transmitters

Two distributed circuits based on MOS-HBT cascodes are reported in a 55-nm SiGe BiCMOS technology and are aimed at a single-chip time-interleaved transceiver for future 1-Tb/s optical links. The first, a DC-135-GHz single-ended distributed amplifier (DA) was optimized for low noise, linear receivers, and has a measured noise figure (NF) $ 7 dB up to 88.5 GHz, 800 mVpp of linear input range, and 8.5 dB gain. Operation was confirmed with PRBS-31 eye diagram measurements up to 120 Gb/s. Additionally, a novel time-interleaved distributed power DAC test circuit was implemented as a proof-of-concept to investigate the maximum achievable output bandwidth at a differential output voltage swing of 6 Vpp, as needed to directly drive an optical modulator. Simulations of the doubly segmented 6-bit DAC show 4-PAM output eye diagrams at up to 120 GBaud. The measured clock-input-to-data-output small-signal bandwidth is 65 GHz. When the DAC is measured as a switching large-swing driver, the differential output voltage swing remains larger than $5.4~\text {V}_{\mathrm {pp}}$ beyond 50 Gb/s. Time interleaving of 4 thermometer MSBs is demonstrated experimentally to form a 1.8- $\text{V}_{\text {pp}}$ differential, 10-GBaud 3-PAM output signal. The experimental sampling rate is limited to 10 GS/s by the capacitance and bandwidth of the low-frequency probes and pads used for the data lanes.

A Single-Chip Electron Paramagnetic Resonance Transceiver in 0.13-&lt;formula formulatype="inline"&gt;&lt;tex Notation="TeX"&gt;$\mu$&lt;/tex&gt; &lt;/formula&gt;m SiGe BiCMOS

We report the first absorption-based single-chip transceiver for electron paramagnetic resonance (EPR) spectroscopy in silicon. The chip is implemented in a 0.13- $\mu$ m SiGe BiCMOS process technology. The transmitter generates and delivers a continuous-wave microwave signal with a frequency range from 895 to 979 MHz and the receiver adopts a direct-conversion architecture. Based on the single-chip transceiver and a printed-circuit-board-based planar resonator, an EPR spectrometer is assembled and tested. The spectrometer successfully measures the EPR response from samples including 2,2-Diphenyl-1-Picrylhydrazyl powder, Fe $_{3}$ O $_{4}$ nanoparticles, and Fe $_{2}$ O $_{3}$ nanoparticles.

Single-chip photonic transceiver based on bulk-silicon, as a chip-level photonic I/O platform for optical interconnects.

When silicon photonic integrated circuits (PICs), defined for transmitting and receiving optical data, are successfully monolithic-integrated into major silicon electronic chips as chip-level optical I/Os (inputs/outputs), it will bring innovative changes in data computing and communications. Here, we propose new photonic integration scheme, a single-chip optical transceiver based on a monolithic-integrated vertical photonic I/O device set including light source on bulk-silicon. This scheme can solve the major issues which impede practical implementation of silicon-based chip-level optical interconnects. We demonstrated a prototype of a single-chip photonic transceiver with monolithic-integrated vertical-illumination type Ge-on-Si photodetectors and VCSELs-on-Si on the same bulk-silicon substrate operating up to 50 Gb/s and 20 Gb/s, respectively. The prototype realized 20 Gb/s low-power chip-level optical interconnects for λ ~ 850 nm between fabricated chips. This approach can have a significant impact on practical electronic-photonic integration in high performance computers (HPC), cpu-memory interface, hybrid memory cube, and LAN, SAN, data center and network applications.

A broadband single-chip transceiver for multi-nuclear NMR probes.

In this article, we present an integrated broadband complementary metal-oxide semiconductor single-chip transceiver suitable for the realization of multi-nuclear pulsed nuclear magnetic resonance (NMR) probes. The realized single-chip transceiver can be interfaced with on-chip integrated microcoils or external LC resonators operating in the range from 1 MHz to 1 GHz. The dimension of the chip is about 1 mm(2). It consists of a radio-frequency (RF) power amplifier, a low-noise RF preamplifier, a frequency mixer, an audio-frequency amplifier, and fully integrated transmit-receive switches. As specific example, we show its use for multi-nuclear NMR spectroscopy. With an integrated coil of about 150 μm external diameter, a (1)H spin sensitivity of about 1.5 × 10(13) spins/Hz(1/2) is achieved at 7 T.

Future integrated sensor radios for long-haul communication

As CMOS single-chip radios enter the era of big data, techniques to acquire, communicate, and store sensor data will evolve to address new demands placed by a rapidly changing application space. Research and development on wireless sensor radio communication over the past decade has been largely focused on energy efficiency for short-range communication. However, going forward, sensor radios will require new modes of communication, which include leveraging existing network infrastructure and increasing the communication range of a single device. This article overviews several existing approaches for wirelessly communicating sensor data, followed by potential future strategies to enhance range and connectivity using single-chip wireless sensor transceivers. As an example of devices for longrange sensor communication, a regulator-less CMOS power amplifier specifically tailored for the demands of longer-range sensor data communication is described. This PA was designed to provide a fixed high-output power using a dynamic voltage supply as commonly found in sensor applications where an energy storage element (super capacitor) supplies the transceiver. The PA system is integrated in a 90 nm CMOS process, has a peak output power of 24 dBm, with an efficiency of 12 percent at 1.8 GHz, making this device suitable for data communication over distances of several hundred meters. As the PA supply varies from 2.5 to 1.5 V, the power control loop maintains a constant output power with an accuracy of ±0.8 dB.

An IR-UWB Transmitter for Ranging Systems

This brief presents a continuous-time impulse radio ultrawideband transmitter. The transmitter is a part of a high-precision ranging single-chip transceiver that measures the time-of-flight symbol propagation. The clock burst generator in the transmitter will initiate symbol transmission in continuous time unbounded by any clock signal while maintaining an accurate chip rate during symbol transmission. Using a calibration circuit, the clock period can be programmed precisely to compensate for device mismatch. The transmitter is fabricated in Taiwan Semiconductor Manufacturing Company 90-nm CMOS technology and occupies an area of 0.123 <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$ \hbox{mm}^{2}$</tex></formula> . The programmable clock range is from 12.65 to 111 MHz, and the measured rms jitter is 3.26 ps at 50 MHz. The entire transmitter has a power consumption of 1.41 mW at the data rate of 2 Mbit/s.

Terabit/Sec VCSEL-Based 48-Channel Optical Module Based on Holey CMOS Transceiver IC

We report here on the design, fabrication and characterization of 48-channel parallel optical transceivers demonstrating terabit/sec data transfer rate. The 0.48 Tb/s transmit plus 0.48 Tb/s receive throughput was achieved using a second-generation single-chip holey CMOS transceiver IC. In addition to 24 receiver (RX) and 24 laser diode driver circuits, the 5.2 mm × 5.8 mm single CMOS chip incorporates 48 through-substrate optical vias (holes), one for each transmitter (TX) and RX channel. A complete holey Optochip is formed following direct flip-chip attachment of 24-channel 850-nm VCSEL and PD arrays. The 48 optical vias enable optical access to the 24 VCSELs and 24 PDs. The holey Optochip concept provides a dense chip-scale package which is fully compatible with industry-standard top emitting/detecting 850-nm VCSELs/PDs providing optimized high-speed performance through close integration of the optoelectronic (OE) devices with their drive electronics. Furthermore, the optical vias and OE devices are arranged in a 4 × 12 array on 250 μm × 250 μ m pitch to facilitate direct fiber-coupling to a standard 4 × 12 multi-mode fiber array. The Optochips are packaged into complete modules by flip-chip soldering to high-density, high-speed organic carriers. A pluggable connector soldered to the bottom of the carrier provides all module electrical I/O. The 18 mm × 18 mm overall module area is dictated by the 0.8 mm-pitch ball grid array (BGA) of the organic carrier and connector. Fully functional holey Optomodules with 24 TX and 24 RX channels operate up to 20 Gb/s/ch achieving efficiencies (including both TX and RX) of 7.3 pJ/bit. The terabit/sec data rate (480 Gb/s TX + 480 Gb/s RX) is highest reported for single-chip CMOS transceiver modules.