Single Chip Packages Research Articles

Multi‐chip Modules for Telecom Applications

System performance can be improved by the use of MCM (multi‐chip module) technology. Better signal transmission properties, lower power dissipation if C‐MOS chips are used and decreased physical volume will be obtained. Today MCM is an expensive technique, but the authors' cost analysis shows that it has the potential to become more cost‐effective than the standard technique of using single chip packages. It can also become more cost‐effective to use the MCM technique than to increase the number of gates on the silicon chip over a certain level. In order to study the properties of MCM technology, a project has been started at the authors' company in which a processor application is built up on three different types of MCM substrates.

Temperature dependence of thermal expansion of ceramics and metals for electronic packages

The X-Y (in-plane) expansivity was measured over the -40-140 degrees C range for several of the ceramics used in modern hybrids, single-chip packages, and multichip modules. These thermal expansion data were compared to those of silicon and the materials used for leads, lids, heat spreaders, and sinks. The expansivity of aluminas of different purities (92-99.5%), low-temperature cofired ceramics, aluminum nitride, and beryllia was measured. A k=4.8 sample was expansivity-matched to Si, and a k=8.0 sample matched to alumina. No significant effect of metallization of the multilayers on the expansivity was found. Aluminum nitride was found to be well matched to silicon, whereas beryllia was found to be well matched to alumina, Kovar, Invar, Alloy 42, molybdenum, and two composites, namely copper-molybdenum-copper and copper-Invar-copper, were measured. Kovar is well matched to alumina ceramic at room temperature; below and above room temperature, however, the expansivity of Kovar diverges from that of alumina.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Electrical Characteristics of Copper/Polyimide Thin-Film Multilayer Interconnects

A multilayer substrate Containing two-chip emitter-coupled logic (ECL) ring oscillator circuits was fabricated and tested to determine the static and dynamic electrical characteristics of the copper/polyimide thin-film multilayer (TFML) interconnections between chips. The circuit oscillated at 122 MHz without delay lines; delay lines in the circuit enabled measurement of 88 ps/cm propagation delay and -28 dB crosstalk between adjacent parallel lines. The measured electrical characteristics agreed with predictions obtained from static electrical models and SPICE simulations of the interconnections. The ring oscillator circuit has general applications for determining dynamic electrical characteristics of a variety of packaging structures, such as co-fired ceramic single-chip packages and tape-automated-bonding (TAB) leadframes.

High Thermal Conduction Package Technology for Flip Chip Devices

The technology of new packages with high thermal conduction performance, simplified structure, and also high reliability for flip chip devices is described. In order to obtain high thermal conduction, a thermal conduction plate is individually bonded to the back surface of a large-scale integrated (LSI) chip by soft solder and is arranged in close proximity to the inner surface of the cap, when the chip is assembled together with the cap and substrate. The cavity is then filled with a gas which has a high thermal conductance characteristic. As a result, a large part of the heat is effectively drawn off from the back side of the chip to the air-cooling fin through the plate and across the narrow gap filled with the gas. A series of experiments were conducted on a single chip package and a nine chip multichip module. These tests indicated a junction-to-fin thermal resistance of 3.2°C/W for the single chip package and 4.8°C/W as a worst case in the module. In addition a computer model analysis for thermal conduction was studied using a program named TNET-2. It was found that the calculated values corresponded closely to the measured data. More detailed descriptions of packages and results of studies are presented and discussed here.

The role of hybrids in LSI systems: C. T. Goddard IEEE Trans. Components, Hybrids Mfg Technology. Chmt-2(4), 367 (December 1979)

N THE PURSUIT of very large scale integration (VLSI), the physical nature of the single chip may assume many forms. Several of these are displayed in Fig. 1. The beam lead and appliqued beam versions usually have I/O pins on lo- and 20-mil centers. JEDEC standard chip carriers provide external connections on 40- or 50-mil centers and standard hermetic and plastic DIP’s provide leads on lOO-mil centers with 2 rows of leads spaced 300 mils or more. In all of the devices shown here, the physical extension from the chip edges is essentially a mechanical transformer which provides a simple fan-out of leads to provide a match with the grid associated with the technology of the interconnection medium. The larger packages are best suited to multilayer board (MLB) application and the unpackaged varieties are particularly compatible with the hybrid technologies. The chip carrier is intermediate, of course. The nature of simple thin and thick film multichip hybrids combining SSI silicon chips and film resistors is shown in Fig. 2. The distinction between thick and thin film is beginning to smear a little as evidenced by the thick film crossovers used in the thin film circuit. A feature of particular interest here is the reduction in package pin-outs for the hybrid compared to the number of pins which would require interconnection on MLB if each of the nine silicon chips had been separately packaged. For a system requiring the interconnection of several times the nine silicon chips (in single chip packages), either a markedly larger board would be required or board complexity measured in interconnections per square inch would increase. Both of these may have an adverse effect on system economics and both of these assume greater importance as the scale of integration in silicon is increased.

Process and Accelerated Aging Test of GANG Bonding for Gold‐PlatedTAB Outer Leads

This paper presents the evaluation results of thermocompression GANG Bonding of gold‐plated TAB outer leads to three kinds of metallized ceramic substrates. Gold‐Selective Plating (GSP) substrates for multi‐chip package, Thick Film (TF) substrates for multi‐chip package and Single Chip Packages (SCP) which have a trimetal combination of refractory metal (tungsten), Nickel and Gold.The bonding parameters such as the bonding tool (thermode) temperature, pressure, bonding time and preheat temperature were examined on each substrate to get optimum values. As the result, a relation between pull strength and the lead deformation shows that the TAB leads should be bonded with 15–65 percent deformation, the recommended parameters are; the tool temperature of 380–430℃, the bonding pressure ranging from 35 to 45 kg/mm2, with the preheat temperature of 150℃ and the bonding time from 1.0 to 2.5 seconds.The evaluation of initial bondability shows that TAB GANG Bonding has the capability of excellent bonding strength; above 120 grams with standard deviation of less than 20 grams, and the necessity of OLB pads flatness; less than ±12 μm for one ounce copper lead. The normal storage of the substrate and the lead does not affect the bondability. And the results of accelerated aging test of 125℃, 150℃ and 175℃ for more than 8,000 hours show that a lifetime of greater than 70 years at 65℃ operating temperature is predicted. The effective activation energy for the pull strength degradation is 0.86–1.05 eV. This is in reasonable agreement with predictions for interdiffusion of Cu–Au. And no significant degradation of the electric resistance was observed on the GSP samples.The feasibility and the high reliability of the GANG Bonding for gold‐plated TAB outer leads were confirmed.

The Role of Hybrids in LSI Systems

The cost of one square inch of ceramic circuit is about the same as one square inch of multilayer printed wiring board containing two signal layers with buried power and ground. But the interconnection density attainable in hybrid is approximately ten times as high. By transferring interconnections from multilayer board to hybrids, the need for excessive layers in MLB is avoided or the total attainable gate count is increased. In comparison with single chip packages, the use of multichip hybrids provides a continuing competitive edge as the scale of integration in silicon is increased year by year.

The thermal design of an LSI single-chip package: G. N. Ellison IEEE Transactions on Parts, Hybrids, and Packaging, PHP-12, No. 4 (December 1976)

The thermal design of an LSI single-chip package: G. N. Ellison IEEE Transactions on Parts, Hybrids, and Packaging, PHP-12, No. 4 (December 1976)

Abstract: The design and characterisation of single chip bubble memory packages

We will report our experience in the design and characterization of a second generation dual-in-line single chip package currently in production was designed to contain a 0.250 inch square chip and to dissipate less than 350 mW in continuous operation. The package operates in external fields up to 100 Oe and shows no irreversible changes over the range −25°C to 100°C; the overall package size is 0.8×0.8×0.35 inches and it fits a 0.9\ pitch socket. (AIP)

The thermal design of an LSI single-chip package : Gordon N. Ellison. IEEE Trans. Parts, Hybrids Packaging. PHP-12, (4) 371 (Dec. 1976)

The thermal design of an LSI single-chip package : Gordon N. Ellison. IEEE Trans. Parts, Hybrids Packaging. PHP-12, (4) 371 (Dec. 1976)

Thermal impedance of ceramic packages using beam-lead IC chips : N. E. Hardsick, Proc. IEEE57, No. 9, September (1969), p. 1616

A three-dimensional analytical approximation for the thermal impedance of a beam-lead IC package is obtained by calcu- lating the thermal resistance of the individual elements and solving by the electrothermal analog technique. For a single chip package, thermal impedance values are presented for both a centrally located 0.005 inch diameter junction area and a source evenly distributed over the active surface of the chip under the following meunting condi- tions: a) package with external leads heat-oinked; b) package with ceramic base heat-sinked; c) chip thermally isolated on AI,O, sub- strate. Also, variations in the thermal impedance of the package with changes in the chip component dimensions are shown graphically. For arrays of beam-lead chips on small ceramic substrates, curves are presented for the upper and lower boundaries of maximum chip power as a function of the number of chips appliqued to the sub- strate. The results indicate that the relatively low power levels which are characteristic of most logic-type beam-lead devices create no thermal problems when packaged individually. However, for large chip arrays the ability of a particular substrate to dissipate the heat generated may be a limiting factor even for these seemingly insignificant power levels?

Thermal impedance of ceramic packages using beam-lead IC chips

A three-dimensional analytical approximation for the thermal impedance of a beam-lead IC package is obtained by calculating the thermal resistance of the individual elements and solving by the electrothermal analog technique. For a single chip package, thermal impedance values are presented for both a centrally located 0.005 inch diameter junction area and a source evenly distributed over the active surface of the chip under the following mounting conditions: a) package with external leads heat-sinked; b) package with ceramic base heat-sinked; c) chip thermally isolated on Al 2 O 3 substrate. Also, variations in the thermal impedance of the package with changes in the chip component dimensions are shown graphically. For arrays of beam-lead chips on small ceramic substrates, curves are presented for the upper and lower boundaries of maximum chip power as a function of the number of chips appliqued to the substrate. The results indicate that the relatively low power levels which are characteristic of most logic-type beam-lead devices create no thermal problems when packaged individually. However, for large chip arrays the ability of a particular substrate to dissipate the heat generated may be a limiting factor even for these seemingly insignificant power levels.

Thermal impedance of ceramic packages using beam-lead IC chips

A three-dimensional analytical approximation for the thermal impedance of a beam-lead IC package is obtained by calculating the thermal resistance of the individual elements and solving by the electrothermal analog technique. For a single chip package, thermal impedance values are presented for both a centrally located 0.005 inch diameter junction area and a source evenly distributed over the active surface of the chip under the following mounting conditions: a) package with external leads heat-sinked; b) package with ceramic base heat-sinked; c) chip thermally isolated on Al <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</inf> O <inf xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</inf> substrate. Also, variations in the thermal impedance of the package with changes in the chip component dimensions are shown graphically. For arrays of beam-lead chips on small ceramic substrates, curves are presented for the upper and lower boundaries of maximum chip power as a function of the number of chips appliqued to the substrate. The results indicate that the relatively low power levels which are characteristic of most logic-type beam-lead devices create no thermal problems when packaged individually. However, for large chip arrays the ability of a particular substrate to dissipate the heat generated may be a limiting factor even for these seemingly insignificant power levels.