SPICE Simulation Research Articles

Pseudologic Optical Circuit Method for Advanced Color Sensing in IGZO Phototransistor Arrays with Chlorophyll Absorption Layers.

Recently, the elimination of color filters has become a key focus in photodetector research because of the potential to create more compact and cost-effective sensor systems. In this study, a novel concept of a filter-free color-discrimination photosensor using an indium gallium zinc oxide (IGZO, In/Ga/Zn = 3.1:2.6:1.0)-based phototransistor with an integrated chlorophyll absorption layer (CAL) and a solution-processed oxide absorption layer (SAL) was developed. Chlorophyll, known for its role in photosynthesis as a natural light absorber, offers distinct characteristics compared to conventional photodetectors (i.e., SAL/IGZO), whereby the photoresponsivity decreases with increasing wavelength. Using the ability of chlorophyll to absorb blue and red light, the proposed CAL/IGZO phototransistor exhibited a higher photoresponsivity to red light than to green light. The device achieved a photoresponsivity of 1570 A/W for red light and 681 A/W for green light, with a photosensitivity of 8.35 × 105 and 8.96 × 104 and a detectivity of 8.47 × 1011 and 6.80 × 1010 Jones, respectively, under an illumination intensity of 1 mW/mm2. Furthermore, by integrating the proposed CAL/IGZO phototransistor with a SAL/IGZO phototransistor, which exhibited a different order of photoresponse across RGB wavelengths, an innovative color-discrimination pixel pseudologic circuit was successfully developed. The capability of this circuit to distinguish colors across various light intensities was validated through experimental data and SPICE simulations, with the output voltage ranges confirmed as -2.61 to -3.51 V for red, 1.56 to 2.69 V for green, and -0.22 to -0.68 V for blue over light intensities from 0.1 to 3 mW/mm2. This innovative approach allows effective color detection without conventional color filters, providing an advanced solution for photodetection technologies.

A data-driven compact drain current model for InGaAs FinFET using TCAD assisted machine learning approach

Abstract This article presents a novel machine learning-based framework for modeling the drain current of InGaAs FinFETs. An artificial neural network, trained on a comprehensive dataset generated by 3D numerical device simulations, forms the core of this model. The simulations covered a wide range of device geometries and bias conditions, resulting in diverse current-voltage characteristics. Using TensorFlow in a Python environment, we built and trained a neural network to accurately predict drain current. The model’s performance was evaluated on independent test datasets, demonstrating its effectiveness on unseen data. The model accurately captures the effects of varying gate length, drain voltage, and gate voltage. Multiple error metrics, including mean squared error, mean absolute error, root mean squared error, and correlation coefficient, were used to assess its performance. At shorter gate lengths, the calculated relative error in drain current was 2.18% and 1.17% at VDS=50mV and 1V, respectively.
After training, the network parameters were extracted to create a Verilog-A model. This model was integrated into the SPICE simulator for circuit simulations. A resistive load inverter circuit was designed to demonstrate the model’s capabilities, and voltage
transfer characteristics and transient analysis were performed within SPICE. These results validate the effectiveness of the developed machine learning-based InGaAs FinFET model.

Double-gate metal–oxide TFT pixel circuit for improved luminance uniformity of mobile OLED display

The small subthreshold swing (SS) of metal–oxide (MOx) thin-film transistors (TFTs) reduces the data voltage (VDAT) range of the organic light-emitting diode (OLED) display pixel circuit. This leads to a large OLED current error when a small change occurs in the gate-to-source voltage (VGS) of the driving TFT in the pixel. Therefore, we propose a new pixel circuit adopting a double-gate TFT structure for the driving TFT, which is mainly driven by the bottom gate with a thicker gate insulator to provide a wide VDAT range. The proposed pixel circuit further expands the VDAT range by employing threshold voltage (VTH) modulation effect depending on the gray level. It also allows for flexible adjustment of the VTH extraction time to reduce OLED current error at low gray levels. SPICE simulation and measured results verify that the proposed pixel circuit reduces the OLED current error rate to less than 10% even with a VTH variation of ±0.5 V or SS variation of ±5% for the current level from 0.1 nA to 30 nA.

Fabrication, compact & device modeling of 4H–21DNTT organic thin film transistor

Abstract In this study, we explored a novel organic semiconductor (OSC), 6,6 bis-(trans4-butylcyclohexyl) dinaphtho[2,1-b:2,1-f]thieno[3,2-b]thiophene (4H–21DNTT). The work also includes a TCAD device model for optimizing and improving the device performance. Both the experimental and simulated results have demonstrated sufficient mobility to realize complex circuits. To validate its potential, a compact model was developed and employed in the SPICE simulator for complex-circuit simulations. Both models accurately capture the below-threshold, linear, and saturation operating conditions through a unified approach, removing the necessity for explicitly defining the threshold and saturation voltages.

Voltage Differencing Buffered Amplifier Realisation Using 32 nm FinFET Technology and Universal Filter Applications

This paper presents high-frequency universal filter applications based on a voltage differential buffered amplifier (VDBA) using 32 nm fin field effect transistor (FinFET) technology. FinFET technology is a promising alternative to complementary metal-oxide-semiconductor (CMOS) technology to avoid the problems caused by the decrease in transistor size as the technology evolves. In addition to the manufacturing process being similar to CMOS technology, FinFET technology offers many advantages, such as reduced short channel effects, higher drain current, reduced static leakage current, faster switching time, lower supply voltage, lower power consumption, and higher efficiency. The VDBA active circuit block, which has high input impedance and low output impedance, is preferred for high-frequency and high-bandwidth applications. It is advantageous to design active filter circuits using VDBA because of its superior features, such as lower power consumption, higher bandwidth, wider range linearity, and the ability to implement the proposed circuits without external resistors. In this study, FinFET-based VDBA and filter application are simulated with the Spice simulation programme using 32 nm PTM technology parameters. Simulation results using 32 nm FinFET technology are compared with those using 0.18 µm TSMC technology. It is concluded that 32 nm FinFET technology reduces power consumption by 98.8 % and increases bandwidth by 145 times. The successful results show that FinFET technology is superior to CMOS technology in analogue circuit design. FinFET-based VDBA circuits and filters will be more advantageous in the design of signal processing and biomedical applications.

A fin-gate p-GaN HEMT with high threshold voltage and improved dynamic performance

A novel fin-gate p-GaN (FPG) HEMT is proposed to simultaneously increase threshold voltage (Vth) and improve dynamic performance of the p-GaN HEMT. The fin-gate structure works as a normally-on p-channel MESFET between gate and source by forming a Schottky-type contact on sidewall and a source-connected Ohmic-type contact on top of the fin. Thus, the Vth can change with the shutdown voltage of the p-channel MESFET, which can be modulated by the doping concentration and width of the fin-p-GaN. By optimizing the fin structure, a high positive Vth of 4V is achieved without transconductance and breakdown voltage degradation in this work. It breaks the restriction between Vth and on-resistance for conventional p-GaN HEMT. The dynamic characteristics of the FPG HEMT are investigated by SPICE simulations. Owing to the well-grounded p-GaN through the normally-on MESFET, the recovery process of the dynamic shift in Vth (ΔVth) after on/off-state stress can be accelerated by two orders of magnitude. It means an imperceptible dynamic degradation and a great potential in high frequency application for the FPG HEMT.

VCII‐Based Immittance Simulators: Generalized Parallel Configurations

ABSTRACTIn this paper, four new generalized configurations of grounded parallel‐type immittance simulators are proposed. These circuits implement parallel resistor–inductor (RL), parallel resistor–capacitor (RC), parallel capacitor–frequency‐dependent negative resistance (CD), and capacitance multiplier configurations utilizing only two second‐generation voltage conveyors (VCII±) as active elements along with three impedances, without the need for specific matching conditions. The applicability of the proposed parallel RL and capacitance multiplier configurations as a second‐order high‐pass filter (HPF) and a first‐order low‐pass filter (LPF), respectively, is also demonstrated. These applications illustrate the versatility and utility of the proposed structures. Frequency, transient, and Monte Carlo analysis utilizing the CMOS VCII± in the SPICE simulation tool have also been performed to validate the feasibility of the presented circuits. Further validation is carried out through layout design in Cadence Virtuoso, employing 0.18‐μm CMOS technology. Both presimulation and postsimulation results are presented for a thorough assessment of the proposed circuits. Also, the claimed theory is verified by experimental results based on the VCII implementation with commercially available IC AD844.

Discrete Analysis of Electrical Circuit with Sources of Rectangular Pulses

Abstract Discrete transients and stationary process are described in series RC-circuits when the supplied voltage contains periodic rectangular pulses. The analysis is performed using z - transformation to obtain analytical dependencies for the capacitive voltage in any time of the rectangular pulses. The approach is used for discrete analysis of various circuits in which rectangular pulses have different characteristics. The calculated capacitive voltages by the obtained discrete dependencies are identical, compared to the results obtained by SPICE simulation. The method proposed in the present work allows, together with the transient process, to investigate the corresponding stationary process. Cases of stable and unstable transients are shown.

Smart-CX – Method of extraction of parasitic capacitances in ICs

This paper proposes a novel rule-based parasitic capacitance extraction methodology, integrated into Smart-CX, to enhance the accuracy of SPICE simulations and physical verification of ICs. This methodology is crucial during the microchip design phase, particularly in preparation for fabrication on mature to advanced process nodes. The proposed enhanced analytical method addresses the accuracy/time tradeoffs between numerical and analytical extraction techniques. This study validates the accuracy of the methodology by comparison of the extracted parasitic parameters with foundry-provided 2D-models. The parasitic capacitances that are extracted within this method include: area capacitances (Ca), coupling capacitances (Cc), including via-to-via capacitances (Cmv), contact-to-gate capacitances (Cmg), contact-to-active capacitances (Cmc) and fringe type capacitances with the top (Cft) and bottom (Cfb) conductive layers.

Predicting unparalleled degradation progression in PV module using simulation of shunt resistance experimental data

Datasets of various levels of solar cell shunt resistances were available in the literature, resulting in a linear correlation to forecast shunt resistance (Rsh) degradation and failures in photovoltaic (PV) cells. However, some PV failures initiate mildly with one or few cells in a PV module and then distribute to other cells which leads to a major power reduction as well as critical safe operation. Simulating these experimental datasets gives the potential to catch these unparalleled degradations in PV modules at early stages, preventing them from turning critical. In response, SPICE simulation was used to study the effect of PV cells with low shunt resistance in a PV module. The simulation follows four steps, focusing on the electrical output of Current-Voltage (I-V) curve of the solar cells: (a) simulation of the experimental healthy I-V curve of a PV cell; (b) simulation of experimental eleven I-V curves at reduced levels of shunt resistance; (c) simulation of a PV module by using the simulation parameters obtained from the former steps; and (d) lastly, simulation of four different scenarios depending on the number of faulty cells in a PV module. The effect of these scenarios on the I-V curve parameters is compared. Results revealed it is feasible to detect unparalleled degradations, spotting the failed cells (reduced Rsh) in a PV module by implementing a linear model correlating open-circuit voltage (VOC) with short-circuit-current (ISC) (acting as a proxy of Irradiance) at different shunt resistance levels. This model can be simulated as a robust indicator of PV abnormalities and is appropriate for employment in online PV monitoring systems.

A Novel High-Performance Voltage Differencing Buffered Amplifier

In this paper, a novel approach is introduced for the development of a power-efficient voltage differencing buffered amplifier (VDBA) by incorporating an adaptive biasing circuit. The proposed design is specifically tailored to exhibit low power consumption. The VDBA proposed in this study includes a conventional transconductance unit (TU) with an adaptive biasing and a positive feedback circuit. Incorporating adaptive bias cells and cross-coupled positive feedback circuit, the VDBA structure allows for boosted tunable gain based on the input differential voltage. The proposed VDBA shows improved transconductance gain, transient characteristics, linearity for a wide range of inputs, and reduced standby power dissipation. A mathematical formulation has been presented to define the characteristics of the proposed VDBA. To validate the proposed VDBA structure, SPICE simulations were conducted using 180 nm CMOS technology. The input linear range of the proposed VDBA is ± 250 mV. The 3 dB bandwidth of the proposed structure is 200 MHz. The THD has been found low. The Monte Carlo simulations have also been carried out and found the proposed structure is less sensitive to the different parameter variations. The slew rate of the proposed VDBA is found 26.2 V/µS. As an application example, a voltage mode universal MISO biquad filter is also proposed using the proposed structure VDBA.

High-Performance Method and Architecture for Attention Computation in DNN Inference.

In recent years, The combination of Attention mechanism and deep learning has a wide range of applications in the field of medical imaging. However, due to its complex computational processes, existing hardware architectures have high resource consumption or low accuracy, and deploying them efficiently to DNN accelerators is a challenge. This paper proposes an online-programmable Attention hardware architecture based on compute-in-memory (CIM) marco, which reduces the complexity of Attention in hardware and improves integration density, energy efficiency, and calculation accuracy. First, the Attention computation process is decomposed into multiple cascaded combinatorial matrix operations to reduce the complexity of its implementation on the hardware side; second, in order to reduce the influence of the non-ideal characteristics of the hardware, an online-programmable CIM architecture is designed to improve calculation accuracy by dynamically adjusting the weights; and lastly, it is verified that the proposed Attention hardware architecture can be applied for the inference of deep neural networks through Spice simulation. Based on the 100nm CMOS process, compared with the traditional Attention hardware architectures, the integrated density and energy efficiency are increased by at least 91.38 times, and latency and computing efficiency are improved by about 12.5 times.

Analysis of an operational trans-conductance amplifier with positive feedback

In this paper, we present an analysis of an operational trans-conductance amplifier (OTA) with two positive feedback. The direct current (DC) transfer function is obtained by analyzing the OTA using the drain current in the weak inversion region. The analysis results were verified through comparison with SPICE simulations, and the characteristics of the DC transfer function analysis for the OTA design are well matched with the simulation results. The designed OTA dissipates a low power of 41.4 nW, and features the slew rate is improved by 436% compared to a conventional OTA without two positive feedback. Additionally, a DC gain and a unity-gain bandwidth is improved by 36 dB and 6.7 times, respectively. The OTAs are designed for the 0.18 μm complementary metal–oxide–semiconductor (CMOS) process.

Second generation current conveyor based capacitorless floating memristor emulator

AbstractThis article offers a novel flux controlled floating memristor emulator based on second‐generation current conveyor (CCII). The floating memristor is designed using two CCIIs, one resistor, and one PMOS transistor. The presented memristor emulator does not need external capacitance. The proposed designed circuit exhibits pinch hysteresis loops in voltage–current plane up to 2 GHz frequency. The performance of the circuit under consideration is evaluated using 180 nm CMOS technology parameter by the SPICE simulator. The circuit requires a DC power supply of ±1.2 V and exhibits a power consumption of 0.766 mW. Furthermore, the resilience of the planned circuit is assessed by examining process corner fluctuation, supply voltage variation, temperature variation, and transistor size variations. In addition, a Schmitt trigger circuit and high order filters based on designed memristor are used to confirm the operation of the proposed design at high and low frequency, respectively.

A two‐step sizing method for multistage Op Amps based on behavioral initial sizing followed by Spice‐in‐the‐loop refining

AbstractAnalog integrated circuit sizing is a laborious process that requires many times of iteration with Spice simulations. Even by applying the method, it still requires iterations and test assignment of device values (and biasings) in each iteration until reaching a satisfactory sizing result. When facing a design of multiple‐stage circuits (such as multiple‐stage operational amplifier [Op Amp]), sizing becomes more challenging due to the requirement on pole‐zero placement in order to achieve a better high‐frequency performance. Simulation‐in‐the‐loop method has been the dominating means taken by a great many of existing circuit sizer, but they suffer from intolerable runtime while lacking the possibility of offering insight or design knowledge acquisition. On the other hand, behavioral‐level synthesis methods, although intuitive and fast, suffer from accuracy loss due to the adoption of simplified device models and significantly condensed design equations. However, a proper combination of these two types of methods could lead to a lucrative research territory, yet it demands a methodological development for efficient deployment in practice, namely, implementation easy, less runtime, and guaranteed sizing quality. In this paper, we propose a two‐step method that takes the advantage of behavioral synthesis (in the first step) that is capable of fast and broader coverage of design space then makes correction (in the second step) on sizing refining by Spice simulation. Due to the profiling knowledge acquired on the design space in the first step, it can avoid blindness of the optimization landscape that is faced by many simulation‐centric methods which could easily get trapped in local optima. Conducted experiments over eight three‐stage Op Amps with different compensation configurations, including nested Miller capacitor (NMC), NMC with feedforward path (NMCF), NMC with feedforward path and nulling resistor (NMCFNR), NMC with nulling resistor (NMCNR), double pole‐zero cancellation (DPZC), transconductance with capacitances feedback compensation (TCFC), impedance adapting compensation (IAC), active feedback frequency compensation (AFFC), have validated that the proposed method can successfully generate qualified sizing results, offering an opportunity to compare fairly what merit a specific compensation strategy could possibly have.

Domain wall and magnetic tunnel junction hybrid for on-chip learning in UNet architecture

We present a spintronic device based hardware implementation of UNet for segmentation tasks. Our approach involves designing hardware for convolution, deconvolution, rectified activation function (ReLU), and max pooling layers of the UNet architecture. We designed the convolution and deconvolution layers of the network using the synaptic behavior of the domain wall MTJ. We also construct the ReLU and max pooling functions of the network utilizing the spin hall driven orthogonal current injected MTJ. To incorporate the diverse physics of spin-transport, magnetization dynamics, and CMOS elements in our UNet design, we employ a hybrid simulation setup that couples micromagnetic simulation, non-equilibrium Green’s function, and SPICE simulation along with network implementation. We evaluate our UNet design on the CamVid dataset and achieve segmentation accuracies of 83.71% on test data, on par with the software implementation with 821 mJ of energy consumption for on-chip training over 150 epochs. We further demonstrate nearly one order of magnitude (10×) improvement in the energy requirement of the network using unstable ferromagnet (Δ = 4.58) over the stable ferromagnet (Δ = 45) based ReLU and max pooling functions while maintaining similar accuracy. The hybrid architecture comprising domain wall MTJ and unstable FM-based MTJ leads to an on-chip energy consumption of 85.79 mJ during training, with a testing energy cost of 1.55 µJ.

Gate breakdown induced stuck bits in sub-20 nm FinFET SRAM

This paper discusses the stuck bits induced by the gate breakdown of PMOS in the sub-20 nm FinFET static random access memory (SRAM) device. After the heavy-ion experiment, several stuck bits are in the FinFET SRAM matrix, which cannot be set or reset. To investigate the factors that caused the stuck bit, we perform the electrical failure analysis (EFA) to measure the electric characteristics of the transistors in the stuck bits and normal cells separately. The measurement results show a clear gate breakdown at the PMOS pull-up (PPU) transistor in all of the measured SRAM cells. Meanwhile, the SPICE simulation based on the EFA results verifies the impact of the damaged PPU. Finally, considering all of the phenomena, the charge deposition from single events is the major mechanism that causes the stuck bits in FinFET SRAM. The experiment results alert a potential gate breakdown risk in the ultra-high-density FinFET SRAM applied in the space environment.

Grounded and floating memristor emulator employing ICCTA: decremental or incremental operation

ABSTRACT This article describes floating and grounded memristor emulator built with an Inverting Current Conveyor Transconductance Amplifier (ICCTA). One ICCTA, one capacitor, and three resistors are used to implement the charge controlled floating memristor emulator. In contrast, a flux controlled grounded memristor emulator consists of one ICCTA, one resistor, and one capacitor. Both presented circuits do not incorporate complex circuits such as analog multiplier circuits, passive inductors, and analog to digital converter circuits in their implementation, which is advantageous in terms of circuit realisation. The designed circuits may be operated in incremental as well as decremental configurations by appropriate setting of MOS switches. In addition, PVT (process, voltage, and temperature) analysis of the proposed memristor is also included. Furthermore, the non-ideal explanation of the proposed circuits is mathematically examined. The proposed emulators are simulated in SPICE simulator using 180 nm technology. Meminductor circuit and memristor-based low pass filter are used to validate the effectiveness of the designed circuits.

Piezoelectric Transducers: Complete Electromechanical Model with Parameter Extraction.

This paper presents a complete electromechanical (EM) model of piezoelectric transducers (PTs) independent of high or low coupling assumptions, vibration conditions, and geometry. The PT's spring stiffness is modeled as part of the domain coupling transformer, and the piezoelectric EM coupling coefficient is modeled explicitly as a split inductor transformer. This separates the coupling coefficient from the coefficient used for conversion between mechanical and electrical domains, providing a more insightful understanding of the energy transfers occurring within a PT and allowing for analysis not previously possible. This also illustrates the role the PT's spring plays in EM energy conversion. The model is analyzed and discussed from a circuits and energy harvesting perspective. Coupling between domains and how loading affects coupled energy are examined. Moreover, simple methods for experimentally extracting model parameters, including the coupling coefficient, are provided to empower engineers to quickly and easily integrate PTs in SPICE simulations for the rapid and improved development of PT interface circuits. The model and parameter extractions are validated by comparing them to the measured response of a physical cantilever-style PT excited by regular and irregular vibrations. In most cases, less than a 5-10% error between measured and simulated responses is observed.

An aging simulation method based on the change of input vector inside the critical path

Abstract With the large-scale expansion and process shrinking of modern integrated circuits, aging has become one of the main factors threatening circuit reliability. To evaluate the impact of aging on circuit life, it is important to investigate aging simulation methods. Aiming at the problem of slow speed and insufficient accuracy of large-scale digital circuit aging simulation methods, a circuit aging simulation method based on the change of input vector inside the critical path (CICP) is proposed in this paper. First, the critical path (CP) with the tightest timing is extracted by static timing analysis (STA), and SPICE simulation is carried out to accurately predict the aging of the CP of the circuit. Second, the aging simulation is carried out considering the change of the internal input vector of the CP. The simulation results show that after changing the internal input signal, the aging path delay increases up to 3.5%.