SIMON Simulator Research Articles

Analytical Modelling and Performance Characterization of Single Electron Transistor

One important component of the present nanotechnology research field is single electron transistor (SET) which has unrealized quality to operate at breakneck speeds with ultralow power consumption. The single electron transistor is a novel nanoscale switching device that can regulate the motion of a single electron in addition to maintaining its scalability down to the atomic level. In this context, scalability refers to the ability of electronic device to function better as their dimensions get smaller. The basic device properties that this single electron transistor (SET) operates on "quantized current-voltage (I-V) characteristic," "single electron tunneling effect," and "Coulomb blockade," are also covered. This study presents some of the key SET-related topics, such as modelling and simulation methods. Simulation of Nanostructures Method (SIMON) is circuit simulator for tunneling device with just a single electron device based on Monte Carlo approach. It enables simulation of any kind of circuits with voltage source, junctions in tunnels and capacitors in quasi stationary mode and transient mode. The most significant feature of SET that is applied in the research work is Coulomb blockade oscillation, so at the conclusion of this paper, a number of simulations utilizing the SIMON simulator are shown. The simulation results show that for gate capacitance CG = 2af, C∑ = 3af, IBIAS = 2nA, tunnel barrier resistance RT > 4.1KΩ and operating temperature T=21K the model reflects real SET characteristic with maximum voltage gain.

Performance investigation of nanoscale reversible logic gates designed with SE-TLG Approach

ABSTRACT The progressive shrinking of MOS dimensions confronts critical issues while designing low power consuming computational devices. The Single Electron Technology is one of the emerging technological solutions to cope up with the scaling challenges and support Moore’s law. Apart from the miniaturization, another concern is the energy efficiency of the designed circuit. Use of reversible logic in place of the conventional Boolean logic can serve the purpose. The works so far in this field mainly concentrated upon the application aspect of different reversible gates and reversible circuits rather than proper technological approach or device based design .Different reversible gates such as Fredkin, Toffoli and Double Feynman Gate implementation with Single Electron device and their simulation results are presented in this paper. The power consumption, stability and the size are mainly considered as the different performance metrics. The circuit stability and its temperature dependency is also analysed through the Stability plots generated in SIMON simulator. A new reversible gate PE1 for even parity generating circuits is also proposed along with the supporting simulation results .The design issues and power consumption are compared with the SET-CMOS hybrid-based designs of the same circuits.

Analysis of flip flop design using nanoelectronic single electron transistor

Single Electron Transistor (SET) is a nanoelectronic device that operates under the controlled mode of tunneled individual electrons. In this paper, a comparative analysis was performed employing SET based D-Flip flop with conventional logic D-flip flop. SET is eminent nanoscale devices that have low power dissipation, high speed and performance. The flip flop design was simulated using SIMON simulator and the stability of its operation was analyzed applying the Monte-Carlo method that represented stability with low power dissipation and matched the functionality of traditional CMOS devices.

A modified macro model approach for SPICE based simulation of single electron transistor

A new macro model of single electron transistor (SET) for SPICE based simulation of SET circuits is proposed. Two voltage controlled current sources and some scaling factors are incorporated in the existing model to derive our model. The V---I characteristics of the proposed SET is promising enough to be used as the basic element for designing circuits based on SETs. A comparison with the previous models establishes the fact that our model efficiently removes the drawbacks of the existing models. Our model also agrees well with the results obtained from popular SIMON simulator. To verify the accuracy, we have designed a SET inverter cell and investigated its characteristics. The work includes the effect of the parameters on the noise margin and voltage transfer characteristics of the inverter circuit. Further, to verify the applicability, a multi peak negative differential resistance circuit based on the proposed model is designed and simulated.

Coulomb blockade in PtSi/porous Si Schottky barrier as a two‐dimensional multi‐tunnelling junction

The authors report on Coulomb blockade effect in the PtSi/porous Si Schottky barrier. A model of two-dimensional multi-tunnelling junction (2D-MTJ) can explain the blockade characteristic of this barrier. Using the SIMON simulator, the electrical characteristics of the proposed model were investigated. The results show that simulated current–voltage curves achieve a reasonable fit with the measured data and the present model can be used to study the PtSi/porous Si Schottky barrier behaviour. In accordance with both the studies, Coulomb blockade phenomenon is observed in current oscillation and single-electron effect of this device at low temperatures (5 K) is justified using the 2D-MTJ model. In addition, it indicates that by increasing the current value with temperature and for high drain voltages, PtSi/porous Si Schottky barrier behaves like a single island single-electron tunnelling (SET) junction as previously reported by Raissi et al.

Compact Modeling of Single Electron Memory Based on Perceptron Designs

In this work, we present a Single electron random access memories based on perceptron designs used as the basic artificial bio-inspired neural processing element. The operation principles are described and illustrated for the first time by simulations results. Combining the Monte Carlo method with a direct solution of the stationary master equation, we use SIMON simulator and MATLAB for training process. The main goal of this work is to build a multilayer neural network used in recognition and classification using single electron devices. We further provide a write/Erase/ Read states chronogram to provide the key element of our work which is the charge stored in output neuron’s quantum dots.

A Novel High Speed Full Adder Based on Linear Threshold Gate and its Application to a 4-2 Compressor

This paper proposes a novel full adder based on the linear threshold gate (LTG) which belongs to the single-electron-device (SED) family. The advantage of an LTG-based circuit is that it has a satisfactory fan-out as opposed to other SED-based circuits; hence, it can be utilized in any complex circuit network. The proposed full adder is utilized as an application in a 4-2 compressor architecture. Compressors are elementary building blocks which are widely used in arithmetic structures such as multipliers. The proposed 4-2 compressor can operate reliably in any tree structured parallel multiplier due to its high performance full adders. The SIMON simulator demonstrates the correct operation of the proposed full adder design, along with the presented 4-2 compressor. The performance of proposed full adder and the 4-2 compressor, in terms of delay and power consumption, are calculated in complete detail. The comparisons indicate that the proposed full adder has the highest speed in comparison with the previous high speed designs.

I–V characteristics of two-dimensional nanodot-array single electron transistors

We present a two-dimensional nanodot-array single-electron transistor (2DA-SET) analytical current–voltage model on the basis of master equation and the orthodox theory. Electrical characteristics of these multi island single-electron transistors, which composed of several islands up with to 5×5 nanodot array, have been investigated using SIMON simulator to show the temperature dependence of the Coulomb oscillation in 2DA-SET by varying gate voltage in the temperature range from T=5 to 50K. In addition, the effects of self-island capacitance and inter-dot spacing variation on I–V characteristics of the device under study have been inspected. It illustrates that a proportional increase in current value resulting from higher temperature values and different distribution of nanodot capacitance will be suppressed by the capacitance of whole nanodot-array network in arrays with multiple elements. The 2DA-SET device behaves as a single-island SET device regarding high drain voltage. This is probably because the network of islands is electrically enlarged and merges into a single island owing to the high applied voltage. Finally, we compare the advantages of 2DA-SET face to single-island SET.

Electrical characteristics and modelling of multi-island single-electron transistor using SIMON simulator

In this paper, we present a multi-island single-electron transistor (MISET) model based on the orthodox theory and solving the master equation. Using SIMON simulator, we investigate the electrical characteristics of single-electron transistors (SETs) based on multiple islands and show the temperature dependence of the Coulomb oscillation of the SET with one to six islands as a function of gate voltage Vg in the temperature range from T=5 to 50K. Values of current tend to increase proportionally with temperature. For a high drain voltage, the MISET behaved as a single-island device. This is probably because the multiple islands were electrically enlarged and merged into a single island owing to the high applied drain voltage. Finally, we compare the advantages of MISET face to single-island SETs with identical dimensions of islands.