Simulator Silvaco Atlas Research Articles

Study of Process Variation in Nanotube Tunnel Field Effect Transistor

In the nanoscale, the process parameters and device dimension variation extensively affect the electrical performance of the device. Therefore, an inclusive study for the prediction of the overall device behavior is extremely necessary. In this manuscript, process variations caused by random dopant fluctuation (RDFs), variation of oxide thickness, and workfunction during fabrication are analyzed in junctionless nanotube TFET. The work quantitatively evaluates the impact of process variability on the various electrical parameters like energy band diagram, electric field, carrier concentration, and drain current of the nanotube TFET structure. The device simulation has been carried out with a 3-D SILVACO ATLAS simulator.

Thermal management and switching performance of β-Ga2O3 vertical FinFET with diamond-gate structure

In this paper, a beta-phase gallium oxide (β-Ga2O3) vertical FinFET with diamond-gate has been studied by Silvaco-ATLAS simulation. The diamond-gate structure achieves adjustable pin (p-insulator-n) junction owing to the diamond-SiO2-Ga2O3 heterostructure. This design also enhances heat dissipation by virtue of the high thermal conductivity of the diamond. Compared to conventional FinFETs, the diamond-gate FinFET (DG-FinFET) reduces the static operating temperature rise by around 17.30%. Additionally, due to its greater heat dissipation capacity, DG-FinFETs provide a 5.84% increase in current density at 1 kA cm−2 current density level. The structural changes in the diamond-gate also result in a significant reduction in the gate-source capacitance (C GS). At 1 MHz operating frequency and the same gate voltage, DG-FinFETs have 69.29% less gate-source charge (Q GS), 70.80% less charge/discharge delay time, 73.70% less switching loss, and 57.15% less conduction loss. Overall, the simulation and analysis presented in this work indicate a promising advancement of the DG-FinFET structure in high-power and rapid switching applications.

Analysis of optical and electrical properties in CZTSSe thin film solar cells through the 2d theoretical modeling

In this work, a 2D simulator (i.e., SILVACO ATLAS simulator) was used for modeling the Cu2ZnSn(S, Se)4 (CZTSSe) thin film solar cells. This simulation study mainly focused on the influence of the electrical and optical parameters that describe the electrical properties of each layer and the absorbed radiation in the heterostructure. These two parameters are analyzed and optimized to get as high of an efficiency as possible. It was characterized by means of the simulation that the effect of the electrical and optical parameters on the solar cell output parameters (VOC,JSC,FF,andη) was studied. The other parameters, such as temperature, bandgap, mobility, and thickness, were also varied in this simulative study for optimizing the device performance. The second record efficiency of 12.6 % was observed for the CZTSSe thin film solar cell (TFSC). This obtained result was compared with the results attained from the SCAPS-1D simulation as well as the second record efficiency for CZTSSe TFSC. Moreover, the Haze function was used to characterize the transmittance and diffuse reflectance in the rough interfaces between the layers of the solar cell. The Haze function utilized the input data like roughness and correction prefactors, which mainly impact the root-mean-square interface roughness (σrms) value by studying the External Quantum Efficiency curve variation. After analyzing these parameters, the efficiency was slightly improved to 13.02 %. Therefore, theoretical modeling could be beneficial to design highly efficient devices without utilizing experimental resources.

Achieving high photovoltaic performance in graphene/AlGaAs/GaAs Schottky junction solar cells by incorporating an InAlGaP hole reflector layer

The purpose of this study is to enhance the efficiency of Graphene/AlGaAs/GaAs Schottky junction solar cells by introducing various Ga-based thin-film materials as a hole reflector (HR) layer. These HR layers are designed to minimize the recombination rate at the back contact and increase the photogeneration rate. In order to investigate the effect of various HR layers on the efficiency of GaAs solar cells, a reference cell was simulated with an efficiency of 14%. The simulation was conducted using the Silvaco ATLAS simulator, under AM1.5G light with a power density of 100 mW/cm2. Subsequently, InAlGaP (InAl0.65Ga0.35P), AlGaAs (Al0.2Ga0.8As), and InGaP (In0.5Ga0.5P) thin films were individually introduced as HR layers to the Graphene/AlGaAs/GaAs single junction solar cell (SJSC). The addition of HR layers to the conventional Graphene/AlGaAs/GaAs Schottky junction solar cell was found to improve the short-circuit current density (Jsc) by enhancing carrier collection and reducing back interface recombination. This approach has also led to a significant increase in external quantum efficiency (EQE) at long wavelengths of around 500–900 nm. The results of this study demonstrate that incorporating an InAlGaP HR layer in the proposed structure due to its wide bandgap, higher photogeneration rate, and higher absorption rate significantly improves the EQE by absorbing longer wavelength photons and increases the efficiency of the solar cell by more than 1.6%.

Trench Dual Gate Junctionless Field Effect Transistor

Diversified biomolecules sensing is turning out to be the most promising area of research due to ever decreasing healthy lifestyle. Field effect transistorized biosensing approach puts its signature as label free, portable and also very careful pathway. In this present work a trench structured dielectric modulated double gate junction-less field effect transistor (TG-DMJLFET) is urbanized using SILVACO ATLAS simulator for label free detection of biomolecules. The developed structure has two vertically positioned gates in distinct trenches. For immobilizing biomolecules, two cavities are formed in the gate oxide region for dielectric modulation. The dielectric constant (k) has been varied over a wide range of 1.54 (Uricase) to 12(Gelatin) signifying the sensing of diverse charged biomolecules. The sensitivity is evaluated in terms of threshold voltage shift and transconductance . The in-depth electrostatic analysis is illustrated in terms of central potential ,energy band diagram ,drive current and also by the depiction of the electric field .In case of charged biomolecules, the shift in threshold voltage is obtained as 350 mV for change in the di-electric constant (k) ranging from 1.54 to 12. The transconductance alteration is observed as 1.94×10-5 when the k is changed from 3.46 to 12 .The device has showed excellent performance in biomolecules sensing.

Performance assessment of dual material vertical TFET based on staggered heterojunction of GaSb-Si

In this research paper, a new III/V–Si-based TFET is proposed. This device benefits from a doping-less tunneling junction. By using a vertical structure, the issue of scaling is effectively addressed. Instead of using inductive metal, a cladding layer is utilized in our device, which turns the intrinsic source into a p+ region. This helps to overcome the challenges related to silicide formation. We use the Silvaco ATLAS simulator to conduct all the numerical simulations. The impact of defect-related mechanisms on our device performance is thoroughly evaluated. We demonstrate that implementing a large underlap between the gate and drain region in a vertical configuration can effectively solve ambipolar conduction. Parameters such as Ion = 10.1 μA/μm, Ion/Ioff = 1.1 × 1011, and fT = 50.1 GHz at VGS = 0.5V indicate that our device is an excellent option for low-power applications.

A physics-based model of dielectric modulated TFET biosensor considering non-ideal hybridization issue

This article investigates the functionality of Dielectric Modulated-Tunnel Field Effect Transistor (DM-TFET) based biosensor using an analytical model created for the electrostatic potential, electric field and drain current. Channel potential and electric field are determined by solving the 2-D Poisson's equation using the parabolic approximation approach. The drain current is estimated by calculating the generation rate of tunneling using Kane's model. The model illustrates the implications of dielectric constant (k) and charge (NBio) and provides a generic solution that works for both neutral and charged biomolecules. The effect of different biasing conditions and parametric variations on electrical properties of the channel is also studied. Capacitances are modeled for different fill factors of biomolecules entrapped in the cavity region. The model demonstrates its resilience by reacting to different fill factors. The analytical findings are validated using data from SILVACO ATLAS simulations. The comparative sensitivity analysis presented highlights the improvement provided by our proposed work.

Switch-Beam Antenna Techniques for Bridge Structural Health Monitoring With GaAs-Based Solar Energy Harvesting

<bold xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">The structural health monitoring (SHM) of bridges with wireless sensor networks (WSNs) is addressed by leveraging two distinct but interrelated aspects: GaAs-based solar energy harvesting and switched-beam antenna strategies in combination with asynchronous media access control (MAC) protocols. The joint optimization of solar energy harvesting and switched-beam directional antennas at the nodes is considered and compared with an equivalent omnidirectional antenna network. To address the limited energy budget in battery-based sensor nodes which is a serious limitation in long-lived applications such as bridge SHM, an efficient solar harvesting solution is put forth based on the good performance of GaAs cells even under low-light conditions. Given the current state of the art in GaAs cells, single-junction cells were selected due to the cost of double-or triple-junction versions. The simulation model includes the residual energy capacity with GaAs-based solar energy harvesting of actual selected components (microcontroller, radio interface chip). The model was implemented on top of the Omnet<inline-formula> <tex-math notation="LaTeX">$++$</tex-math> </inline-formula> and Silvaco Atlas simulator. The comparative study in this article provides insights into realistic bridge SHM sensor networks, leveraging solar energy harvesting and switched-beam antennas.</b>

Design and Analysis of Charge Plasma-Based Vertical-Nanowire Tunnel FET for Biosensor

In the semiconductor industry, nanoscale devices have better ability to provide for biomolecules detection, but they face various problems during fabrication process, such as high doping concentration, random dopant fluctuation (RDF), higher production cost, low electrostatic control. To overcome these problems, charge plasma (CP) technique has been introduced by the formation of hafnium material at drain side and platinum material at source side with appropriate work-function. The proposed work charge plasma-based vertical-nanowire tunnel FET (CP-VNWTFET) has been designed and analyzed for biosensor application using different dielectric constant and gate underlap method by creating a cavity area under the gate metal. The sensitivity ([Formula: see text]) of biosensor is calculated in terms of change in drain-current ([Formula: see text]) and transconductance ([Formula: see text]) by immobilizing the biomolecules such as Urease, Keratin, Streptavidin, ChOX, Zein, Gluten using gate underlap and dielectric modulation technique. The performance parameters like subthreshold slope (SS), off-current ([Formula: see text]), on-current ([Formula: see text]), on/off current ratio ([Formula: see text]) of the CP-VNWTFET have also been observed while varying the neutral and charged biomolecules at various biased conditions. The device is simulated by using Silvaco ATLAS simulator. The proposed device has been found to be suitable for low power sensor design application.

Robustness of Passivated ALD Zinc Tin Oxide TFTs to Aging and Bias Stress

Thin-film electronics fabricated with amorphous oxide semiconductors (AOS) are being studied for beyond-display technologies because of their superior electron transport. To widen the commercial applications, robust devices fabricated using scalable deposition techniques are required. Here, we fabricate bottom-gate, top contact thin-film transistors (TFTs) using zinc tin oxide, an AOS deposited by atomic layer deposition (ALD), and study robustness to aging and bias stress for devices stored in a dark air ambient with and without Al2O3 passivation. All samples exhibit excellent mobility ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu _{\text {FE}}$ </tex-math></inline-formula> ) and subthreshold swing (SS) robustness to aging. Most of the device aging occurs within the first 25 days, after which the performance stabilizes. Changes due to positive bias stress, which are dominated by interactions with ambient molecules, are greatly reduced by passivation. Passivation, however, results in an increase in contact resistance ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{C}$ </tex-math></inline-formula> ), SS, and negative bias illumination stress (NBIS) instability. The increase in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${R}_{C}$ </tex-math></inline-formula> is attributed to the diffusion of oxygen vacancies that occurs during the passivation process, while the increase in SS and NBIS instability is attributed to subgap interface defects. The experimental results are compared to Silvaco ATLAS simulations to confirm the proposed physical mechanisms and allow quantification of the associated defects and non-idealities.

A highly sensitive Nano Gap Embedded AlGaN/GaN HEMT sensor for Anti-IRIS antibody detection

This study investigates the feasibility of Nano gap embedded AlGaN/GaN HEMT to sense antibody-antigen reaction. The sensor can detect the binding response of a typical antibody Ixodes ricinus immunosuppressor (anti-Iris) protein in Nano cavity. The sensor performance is analyzed by the change in electrical characteristics by the anti-iris antibody and iris antigen interaction. The device performance is optimized independently by varying cavity thickness, cavity length, biomolecule length, and Al composition. The output drain current recorded at VDS = 10V was linearly incremented with the length of the bio layers. The increase in cavity thickness and length will reduce the sensitivity due to a reduction in the cavity fill-in factor. The maximum sensitivity obtained is 169% at a cavity thickness of 10 nm and cavity length of 100 nm with 30% Al content. Silvaco Atlas simulation software has simulated and optimized the proposed device structure.

Influence of Doping Concentration and Thickness of Regions on the Performance of InGaN Single Junction-Based Solar Cells: A Simulation Approach

The impact of doping concentration and thickness of n-InGaN and p-InGaN regions on the power conversion efficiency of single junction-based InGaN solar cells was studied by the Silvaco ATLAS simulation software. The doping concentration 5 × 1019 cm−3 and 1 × 1015 cm−3 were optimized for n-InGaN and p-InGaN regions, respectively. The thickness of 300 nm was optimized for both n-InGaN and p-InGaN regions. The highest efficiency of 22.17% with Jsc = 37.68 mA/cm2, Voc = 0.729 V, and FF = 80.61% was achieved at optimized values of doping concentration and thickness of n-InGaN and p-InGaN regions of InGaN solar cells. The simulation study shows the relevance of the Silvaco ATLAS simulation tool, as well as the optimization of doping concentration and thickness of n- and p-InGaN regions for solar cells, which would make the development of high-performance InGaN solar cells low-cost and efficient.

2D multifunctional SiAs2/GeAs2 van der Waals heterostructure

The structural and electronic properties of two-dimensional (2D) SiAs2/GeAs2 van der Waals heterostructure (vdWH) and its applications are investigated by combing first-principles calculations and Silvaco Atlas simulations. The stable SiAs2/GeAs2 vdWH exhibits an indirect bandgap of 0.99 eV in type II band alignment for light detection and energy harvesting. The vdWH can exhibit a direct bandgap up to 0.66 eV by applying an appropriate electric field (E ext ). Due to the E ext induced charge redistribution, its band alignment can be transformed from type II to type I for light-emitting. Further simulation shows that the band alignment of SiAs2/GeAs2 vdWH can be tuned back and forth between type II and type I by gate voltage in a single field-effect transistor for multiple functional applications. These results may be useful for applications of the SiAs2/GeAs2 heterostructure in future electronic and optoelectronic devices.

A novel normally-off GaN vertical Schottky source tunnel-junction field-effect transistor

In this work, a novel normally-off GaN vertical tunnel-junction field-effect transistor (VTJFET) was proposed and investigated by the Silvaco ATLAS simulator. The topology structure and operation mechanism of the VTJFET are completely different from those of previous GaN vertical power devices. The VTJFET exhibited normally-off operation with a threshold voltage VTH of +2.5 V. The specific on-resistance Ron,sp and the breakdown voltage BV were 1.78 mΩ cm2 and 2940 V, respectively. A high on-off current ratio of 1011 and high power figure of merit (FOM) of 4.9 GW/cm2 were achieved. The Ron,sp and BV of the VTJFET are affected by the doping concentration Ndrift and thickness Tdrift of the drift layer, and a record high optimized FOM of 7.4 GW/cm2 was obtained by varying Ndrift and Tdrift. The VTJFET is intrinsically normally-off and exhibited excellent performance, providing a new direction for the development of GaN vertical devices.

Effect of InGaN Channel on Radio‐Frequency Performance in High‐Electron‐Mobility Transistors with an InAlGaN Barrier

The effect of the InGaN channel on the performance of high‐electron‐mobility transistors (HEMTs) through the Silvaco Atlas simulator is investigated in detail. It is shown that the 2D electron gas (2DEG) density and carrier confinement of the device can be enhanced by replacing the GaN channel with the InGaN channel. The higher 2DEG density significantly increases the saturation drain current density, thus improving the current drive capability of the device. Meanwhile, better carrier confinement alleviates the short channel effects (SCEs) and traps state‐related current collapse in the GaN buffer, effectively improving the reliability of the device. Better carrier confinement also increases the current gain cutoff frequency (fT) and maximum oscillation frequency (fmax) to 133 and 226 GHz, while the fT and fmax of conventional GaN channel HEMTs are 104 and 167 GHz, respectively. These results indicate that AlInGaN/InGaN HEMTs achieve better performance in direct current (DC) and radio frequency (RF).

Impact of Work Function Tunability on Thermal and RF Performance of P-type Window based Junctionless Transistor

The choice of gate metal technology for junctionless transistors needs to have diverse characteristics as metals have distinct work functions and hence, they show incompatibility while tailoring threshold of the device. In such a scenario, bimetallic stacked gate can be a promising candidate to present wide range of tunable work functions required for nano-regime junctionless transistors. This paper explores the electronic phenomena occurring at metal-metal interface and the impact of Platinum (Pt)/Titanium (Ti) bimetallic stacked gate-based work function tunability on the RF and thermal performances of p-type window-based Silicon on Insulator Junctionless Transistor (SOI JLT) using numerical simulator SILVACO ATLAS. The parameters considered for performance evaluation are ON-state current (I_{ON}), OFF-state current (I_{OFF}), I_{ON}/I_{OFF} ratio, transconductance (g_m),\linebreak cutoff frequency (f_T), Transconductance Frequency Product (TFP), Intrinsic Gate Delay (IGD), intrinsic gain (A_V), and Global Device Temperature (GDT). The g_m, f_T, TFP, A_V and GDT improve for modified over conventional in the ON state at higher work function, while IGD improves at lower work function. The improvements of 11.7% and 2.21% are obtained in maximum g_m and f_T, respectively, for modified transistor over conventional. The findings suggest that bimetallic stacked gate modified SOIJLT is a better option than conventional for low-power RF application.

Junctionless Accumulation Mode Ferroelectric FET (JAM-FE-FET) for High Frequency Digital and Analog Applications

In this paper, a Junctionless Accumulation Mode Ferroelectric Field Effect Transistor (JAM-FE-FET) has been proposed and assessed in terms of RF/analog specifications for varied channel lengths through simulations using TCAD Silvaco ATLAS simulator, using the Shockley-Read-Hall (SRH) recombination, ferro, Lombardi CVT, fermi and LK models. Major analog metrics like transconductance (gm), intrinsic gain (AV), output conductance (gd), and early voltage (VEA) are obtained for the JAM-FE-FET arrangement. The proposed structure shows an improvement in parameters like gm, Ion/Ioff, Av, TGF by 6.82%, 27.95%, 5.2%, 38.83% respectively. Further, frequency analysis of the proposed device is performed and several critical RF parameters like fT, TFP, GFP, and GTFP have been observed to be enhanced by 6.89%, 11.38%, 13.65%, 12.01% respectively. Thus, the Junctionless accumulation mode ferroelectric FET (JAM-FE-FET) arrangement has been found to have superior analog and RF performance when compared to Junctionless ferroelectric FET(JL-FE-FET). As a result, the JAM-FE-FET device presented here can be contemplated a good contender for applications in high-frequency systems.

Simulation Study of Single-Event Burnout for the 4H-SiC VDMOSFET with N+ Split Source

Silicon Carbide (SiC) power MOSFET is the next generation device in the supply system of spacecraft. However, the current degradation or catastrophic failure of the power device could be induced when a drain voltage exceeds critical condition. In this article, an improved VDMOSFET structure for the Single-Event Burnout (SEB) is demonstrated. The improved power VDMOSFET includes a P+ shielding region at the JFET region. Meanwhile, forming a CSL layer by ion-implantation at the JFET to reduce the specific on-resistance. The device is etched in both sides to form trench and then implanting N-type impurities at the side walls of the trench to form the N+ split source (SDS-VDMOSFET). The 2-D numerical simulator Silvaco Atlas was used to study the SEB performance for the 1.2 kV-rated SiC SDS-VDMOSFET in a high linear energy transfer (LET) value of 0.5 pC/μm. The simulation results show that the improved structure can effectively reduce the peak lattice temperature induced by heavy-ion and increase the SEB threshold voltage compared with the standard VDMOSFET. Furthermore, the improved structure also presents a lower specific on-resistance. As a result, the maximum temperature of the standard VDMOSFET has exceeded 3000 K at a drain voltage of 400 V. However, the maximum temperature of the improved VDMOSFET is only 2090 K at a drain voltage of 800 V.

Study and optimization of InGaN Schottky solar cell performance

In this work, an extensive numerical simulation of an InxGa1−xN Schottky barrier solar cell is carried out using Silvaco ATLAS simulator. Firstly, the effect of different Schottky metals and Indium fraction (in InxGa1−xN compound) on the solar cell output parameters are studied. A standard Platinum (Pt) work function of 5.65 eV gave a low efficiency of about 7.10% for an Indium (In) molar fraction of 0.54. Since other studies have shown that Pt may have higher work function, this latter was scanned from 5.65 to 6.35 eV. Consequently, the efficiency increased from 7.10% to 22.18% for a work function of 6.35 eV and a 0.7 In fraction. Additional optimizations improved the cell efficiency to 23.3%, by introducing a 4 µm thick intrinsic In0.7Ga0.3N layer between Pt and the doped In0.7Ga0.3N. Further improvement is achieved using a gradual band gap intrinsic layer. Furthermore, this gradual band gap intrinsic layer reduces the effect of interface traps which were found to induce serious degradation of the cell efficiency. The introduction of this gradual band gap intrinsic layer provides a cell efficiency of 38.42% at low trap densities and 28.8% at higher densities.

The gate length effect of high-performance monolayer SiAs2 FETs

The monolayer SiAs2 field-effect transistors (FETs) with gate length (L gate) ranging from 1 to 50 nm were investigated by Silvaco-Atlas simulation in which the main parameters of monolayer SiAs2 were obtained by first-principles calculations. Both the p- and n-FET show extremely high on/off current ratio (1014) and low leakage current (10−18 A μm−1), which are independent of gate length within the 15–50 nm range. And monolayer SiAs2 FETs show practically acceptable values of subthreshold slope and drain-induced barrier lowering when L gate ⩾ 30 nm. On the other hand, the p-and n-FETs show highest transconductance (g m) when L gate is between 25 and 35 nm. Our results suggest that the high performance 35 nm gate length monolayer SiAs2 FETs hold great potential for applications in low-dimensional electronic devices.