Silicon On Sapphire Films Research Articles

Сравнение характеристик тонких пленок PZT на подложках из сапфира и кремния

The properties of ferroelectric sol-gel PZT films deposited on a silicon-on-sapphire (SOS) substrate are compared with those of PZT films formed on a Si substrate. The crystalline structure, asymmetry of the hysteresis loops, polarization dependences of the transient current, short-circuit photocurrent, and open-circuit photovoltage, as well as the substrate bending have been studied. The PZT on SOS films are textured in a single (111) direction and exhibit symmetric hysteresis loops with a strong remanent polarization. The PZT films on Si are textured in the main (111) and weaker (100) directions, have weaker polarization, and exhibit an asymmetry of the hysteresis loops, which is reflected in the magnitude of the transient current and photocurrent. It is shown that the sapphire substrate has a convex bending that causes a compressive stress in the film plane, which weakens the effect of the lattice mismatch between PZT and Pt. By contrast, the Si substrate has a concave curvature, which causes the film to stretch. The deformations and mechanical stresses within the films were estimated. For PZT on Si, an estimate of the strain gradient along the (111) axis was obtained, which makes it possible to relate the asymmetry of the hysteresis loops to the flexoelectric polarization, with the flexoelectric coefficient for sol-gel PZT films found to be 0.0154 µC/cm. The results obtained show that the sapphire substrate provides a better quality of thin PZT films.

Improvement in off-State Leakage Current of n-Channel SOS MOSFETs by Hydrogen Annealing of the SOS Film

The off-state source-to-drain leakage current and punchthrough voltage are the quantities that frequently limit the performance of short-channel floating-body silicon-on-sapphire (SOS) n-channel MOSFETs. In this paper, we demonstrate that the high-temperature hydrogen annealing of the SOS film prior to the device fabrication leads to marked improvement in these two parameters. The effect is attributed to the impact of hydrogen on the out-diffused thin alumina layer formed at the silicon-sapphire interface during the anneal. The thin alumina layer acting as a p-type dopant source at the back interface eliminates the back surface depletion of SOS n-MOSFETs. It also acts as a recombination center to eliminate the floating-body effect of floating-body n-MOSFETs. This technique provides a practical and reliable process to build short-channel floating-body SOS n-MOSFETs with off-state leakage as low as the junction leakage and punchthrough voltage as high as 6 V or higher at the gate length of 0.5 μm without any degradation on the inversion layer carrier mobility or increase in the junction leakage current.

Characterization of stress induced in SOS and Si/γ-Al 2O 3/Si heteroepitaxial thin films by Raman spectroscopy

Raman spectroscopy technique has been performed to investigate the stress induced in as-grown silicon-on-sapphire (SOS), solid-phase-epitaxy (SPE) re-grown SOS, and Si/γ-Al 2O 3/Si double-heteroepitaxial thin films. It was demonstrated that the residual stress in SOS film, arising from mismatch and difference of thermal expansion coefficient between silicon and sapphire, was reduced efficiently by SPE process, and that the stress in Si/γ-Al 2O 3/Si thin film is much smaller than that of as-grown SOS and SPE upgraded SOS films. The stress decrease for double heteroepitaxial film Si/γ-Al 2O 3/Si mainly arises from the smaller lattice mismatching of 2.4% between silicon top layer and the γ-Al 2O 3/Si epitaxial composite substrate, comparing with the large lattice mismatch of 13% for SOS films. It indicated that γ-Al 2O 3/Si as a silicon-based epitaxial substrate benefits for reducing the residual stress for further growth of silicon layer, compared with on bulk sapphire substrate.

Improvement of thin silicon on sapphire (SOS) film materials and device performances by solid phase epitaxy

The increased emphasis on sub-micron CMOS/SOS devices has placed a demand for high quality thin silicon on sapphire (SOS) films with thickness of the order 100–200 nm. It is demonstrated that the crystalline quality of as-grown thin SOS films by the CVD method can be greatly improved by solid phase epitaxy (SPE) process: implantation of self-silicon ions and subsequent thermal annealing. Subsequent regrowth of this amorphous layer leads to a greater improvement in silicon layer crystallinity and channel carrier mobility, evidenced, respectively, by double crystal X-ray diffraction and electrical measurements. We concluded that the thin SPE SOS films are suitable for application to high-performance CMOS circuitry.

Deep states in silicon on sapphire by transient-current spectroscopy

It is demonstrated that deep states in silicon on sapphire (SOS) films can be evaluated by transient-current spectroscopy (TCS). In the TCS spectra, a broad peak extending over 100–200 K was observed for the 6000-Å-thick n-type SOS film. Assuming the value of capture cross section to be 10−15 cm2 and independent of temperature, the density distribution of deep states was estimated. The density distribution shows a peak of 1.2×1012 cm−2 eV−1 at EC−0.25 eV. Raman backscattering spectroscopy was also performed to evaluate the stress in the silicon film. It was concluded that the defects detected by TCS should be caused by the compressive stress of 6.2×108 Pa in the silicon film.

A luminescence study of defects and internal strains in ion-implanted silicon on sapphire films

Low-temperature photoluminescence (4.2 and 35 K) has been used to study the defects created by high-energy particle irradiation (gamma rays, electrons, ions) of silicon on sapphire (SOS) films. It was found that the noble gas atoms implanted into silicon layers take an active part in the processes of interaction with radiation damage. Data on the temperature stability of luminescence centres are given. The residual compressive stress in SOS films is estimated using the photoluminescence method.

Comparison of properties of solid phase epitaxial silicon on sapphire films recrystallized by rapid thermal annealing and furnace annealing

Chemically vapour deposited silicon on sapphire (SOS) films 0.25 μm thick were implanted with 28Si + and recrystallized in solid phase by furnace annealing (FA) and IR rapid thermal annealing (RTA) in our laboratory. An improvement in crystalline quality can be obtained using both annealing procedures. After FA, it is hard to retain the intrinsic high resistivity value (10 4–10 5 Ω cm) observed in as-grown SOS films, so the improvement process cannot be put to practical use effectively. However, it is demonstrated that by properly adjusting the implantation and RTA conditions, significant improvements in both film quality and film autodoping can be accomplished. This work describes a modified double solid phase epitaxy process in which the intrinsic high resistivities of the as-grown SOS films are retained. The mechanism of suppression of Al autodoping is discussed.

A three-dimensional device simulator for radiation-hard MOS-SOS transistors

The effect of the edge parasitic transistor on MOSFET device characteristics fabricated on silicon-on-sapphire (SOS) wafers is analyzed with a new three-dimensional (3D) device simulator. The program performs a numerical solution of the basic semiconductor equations in three dimensions using up-to-date models for the carrier mobilities (including a new field-dependent surface-scattering model) and generation-recombination rates. In addition, depth-dependent models for the carrier mobilities and lifetimes have been introduced to account for the degradation of these parameters near the back interface of SOS films. A novel numerical strategy is implemented that results in efficient and accurate solutions of the floating substrate problem. The accuracy of the simultaneous solution (necessary to solve the floating substrate condition) and the efficiency of Gummel's sequential method are combined to find the two-carrier solution in the full 3D structure. Radiation-induced leakage currents are modeled by adding distributions of charges at the silicon/sapphire interface. The validity of the assumed interface charge distribution model is reinforced by the agreement between simulated and measured post-radiation subthreshold characteristics.

Comparison of phosphorus, arsenic and boron implants into bulk silicon and SOS

Phosphorus, arsenic and boron ions were implanted into both bulk silicon and silicon-on-sapphire (SOS) substrates. It was found that for phosphorus and arsenic the bulk and SOS impurity profiles are identical, whereas for boron the profiles in SOS are deeper than those in bulk silicon. It is assumed that the deeper profiles in SOS are due to a reduction of the electronic stopping power in the SOS films, which affects the lighter boron ions more than the heavier phosphorus and arsenic ions. This conjecture is supported by Monte Carlo implant simulations, which indicate that a reduction of the electronic stopping by roughly 10% could give rise to the observed differences in the SOS and bulk silicon implant profiles.

Photoreflectance Characterization of Silicon Films on Insulator

ABSTRACTPhotoreflectance (PR) was used to study crystalline quality and stress in silicon films on insulator. The position and amplitude of the 3.4 eV PR silicon structure was monitored for both MBE silicon on sapphire (SOS) and SIMOX structures. The SOS film thicknesses ranged from 6 to 4000 nm. The shift in energy of the 3.4 eV structure from its bulk position is dependent on the sample thickness and on the strain in the films. In the SIMOX case, the amplitude of the 3.4 eV PR signal provided information about the crystalline quality of the top silicon layer for a set of six samples, each one removed at a different step of a process involving three implantation-anneal cycles. In this case the PR signal appeared to deteriorate with the each cycle undergone by the samples. Further investigations are needed to resolve the discrepancy bet ween these SOS results and the ones obtained in an earlier set of measurements.

Low-temperature heteroepitaxial growth of Si on Sapphire by disilane gas-source molecular beam epitaxy

Thin epitaxial silicon films with high quality were grown on sapphire by disilane gas-source molecular beam epitaxy. The epitaxial growth occured at substrate temperatures above 600°C, and the growth rate was 120 Å/min at a temperature of 700°C. The activation energy was 13.8 kcal/mol. The RHEED patterns of the silicon-on-sapphire (SOS) film, which was 900 Å thick and was grown at a temperature of 700°C, showed sharp 2×1 streak patterns. It was found that the SOS film was grown smoothly with a thickness of 900 Å. Furthermore, from replica electron micrographs, it was recognized that the growth mode was nucleation and growth, and the coalescence occured at 300 Å.

High-mobility CMOS transistors fabricated on very thin SOS films

It is reported that the mobility of CMOS transistors fabricated on very thin silicon-on-sapphire (SOS) films is a function of the film growth rate. Transistors with mobilities nearly as high as those obtained on 1.0- mu m-thick films have been fabricated on SOS films 0.2 mu m thick that have been grown at growth rates above 4 mu m/min. >

High-quality CMOS in thin (100 nm) silicon on sapphire

Electrical characteristics of enhancement-mode n-channel and p-channel MOSFETs in 100-nm-thick silicon-on-sapphire (SOS) are reported. Channel mobilities (linear operation) of 500 and 200 cm/sup 2//V-s, respectively, have been measured in double solid-phase epitaxially (DSPE) improved material. Deep trap levels associated with the Si-sapphire interface were measured in concentrations as low as 1*10/sup 11/ cm/sup -2/. These results indicate that DSPE-improved SOS films thinned to 100 nm are suitable for application to high-performance down-scaled CMOS circuitry.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Recent advances in solid-phase epitaxial recrystallization of SOS with applications to CMOS and bipolar devices

Recent advances in solid-phase epitaxial recrystallization suggest that this technology may dramatically improve the crystallinity of heteroepitaxial silicon-on-insulators, such as silicon-on-sapphire (SOS). Recent improvements of 0.3- and 0.5-μm SOS films using two solid-phase epitaxial recrystallization processes (SPEAR and DSPE) are reported. Both techniques have reduced the total microtwin densities of SOS samples by more than 100-fold, while increasing electron and hole mobilities approximately 50%. The resulting properties are very close to those of bulk silicon. High-performance submicrometer CMOS devices and circuits in 0.3-μm recrystallized SOS films have been fabricated.

High-temperature behaviour of heavily doped SOS films

The authors present a study of electrical conductivity sigma and thermoelectric power S in the temperature range 100-350 K of silicon-on-sapphire (SOS) films with an average doping level nd approximately=5*1018 cm-3. Using band parameters obtained by a previous study of the low-temperature behaviour of their samples, they obtain the form of the density of states N(E) and they interpret their data by assuming two energy regions contributing to the transport properties in this temperature range. They conclude that their SOS samples behave in practically the same way as bulk Si ones, having a doping level just below the one causing the M-I transition.

Influence of implantation induced damage in sapphire upon improvement of crystalline quality of silicon on sapphire

Crystalline quality improvement of silicon on sapphire (SOS) was carried out using thermal regrowth following Si implantation at energies of 130 and 150 keV, where the projected range of Si corresponded to and exceeded the SOS film thickness, respectively. Under the latter implant condition, it has been shown from Rutherford backscattering spectrometry (RBS) measurements that damage in sapphire does not anneal out after annealing at 1000 °C. RBS and Hall measurements have revealed that the damage introduced into the sapphire during implantation limits the degree of improvement in crystallographic and electrical properties of SOS.

Lattice images of defect-free silicon on sapphire prepared by ion implantation

We report for the first time high resolution cross section transmission electron microscopy (HRXTEM) of defect-free silicon on sapphire (SOS) films. These films are prepared from as-grown SOS films by use of multiple ion implantation and annealing sequences. HRXTEM lattice images for both as-grown and processed films are obtained, and correlation with previous ion channeling experiments on this material is discussed.

Interference Photovoltage Spectroscopy. Probing of the Silicon‐Sapphire Interface of SOS Films

The photovoltage spectra of heteroepitaxial silicon on sapphire (SOS) exhibit an oscillatory pattern (thin film interference effects). The amplitudes of the oscillations increase with decreasing film thickness. We attribute this amplitude increase to anomalous optical behavior of the silicon‐sapphire interface region, and we propose the use of “interference photovoltage spectroscopy” as a practical means for probing the silicon‐sapphire interface.

Channel doping profile of silicon-on-sapphire transistors

Dopant profiles of low-dose channel implant in silicon-on-sapphire (SOS) field-effect transistors are investigated by comparing results from various techniques, including theoretical calculation by the Stanford University integrated-circuit process simulation program (suprem) and experimental measurements by secondary ion mass spectrometry (SIMS), capacitance-voltage (C-V), spreading resistance and metal-oxide-semiconductor Hall effect. It is shown that, for both phosphorus- and boron-implanted SOS films having constant doping profile at a level close to 1×1016 cm−3, as predicted by suprem and measured by SIMS, the charge density measured by C-V technique and free carrier concentration obtained from spreading resistance technique decrease with increasing distance from the Si surface. For SOS films implanted to a level greater than 1× 1017 cm−3 boron, the dopant profile obtained by SIMS analysis coincides with the charge density profile, measured by C-V technique, and the free carrier concentration profile, deduced from spreading resistance, and the actual mobility in SOS films.

Solid Phase Epitaxial Recrystallization of Sos, with Applications to Submicrometer Cmos and Bipolar Devices

ABSTRACTCMOS/SOS devices and circuits were fabricated in 0.3-µm-thick epitaxial silicon-on-sapphire (SOS) films. Two solid phase epitaxial recrystallization techniques (DSPE* and SPEAR**) reduced the total microtwin concentrations in the Si layers more than ten- fold, while increasing electron and hole inversion layer mobilities between 30 and 45%. Leakage currents were substantially reduced in all SPEAR devices and in n-channel DSPE transistors, with some increase observed for p-channel DSPE devices. Drive currents and subthresholds slopes also showed significant improvement in both n- and p-devices. Propagation delays below 75 ps were obtained for CMOS/SOS inverters with Lef = 0.5 µm. The application of DSPE and SPEAR techniques to 0.3-µm SOS films will extend the scaling of CMOS/SOS to circuits with very large scale integration (VLSI) complexity.