SOI FinFETs Research Articles

SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects

SOI FinFET Based 10T SRAM Cell Design against Short Channel Effects

Compact Model Strategy of Metal-Gate Work-Function Variation for Ultrascaled FinFET and Vertical GAA FETs

In this paper, we develop an accurate compact model for work-function variation (WFV)-induced threshold voltage $({V}_{\textsf {th}})$ variations of various 5-nm candidates, in this case, Si SOI FinFETs, vertical gate-all-around nanowire FETs, and nanoplate FETs. Using the typical probability distribution function model to predict the effect of WFV, due to the ideal condition, an error occurs in ultrascaled devices. Therefore, to analyze the influence of WFV accurately, the error rate ( $\alpha $ ) is corrected by considering irregular grain patterns (Voronoi method). In addition, the total number of grains on the metal surface can be calculated while considering the effective grain size and gate area due to the structural characteristics of the device. Finally, the model is benchmarked against 3-D TCAD simulations to demonstrate excellent accuracy [1.53% error in $\sigma $ ( ${V} _{\textsf {th}}$ )]. Moreover, the accuracy is improved by more than 15 times compared with the existing analytical models. As a result, the proposed model based on binomial distribution is able to analyze the effect of WFV at a significantly lower computational cost than 3-D TCAD simulations.

Dual-k Spacer Region Variation at the Drain Side of Asymmetric SOI FinFET Structure: Performance Analysis Towards the Analog/RF Design Applications

Dual-k Spacer Region Variation at the Drain Side of Asymmetric SOI FinFET Structure: Performance Analysis Towards the Analog/RF Design Applications

Thermal-Aware Shallow Trench Isolation Design Optimization for Minimizing <inline-formula> <tex-math notation="LaTeX">${I}_{OFF}$ </tex-math> </inline-formula> in Various Sub-10-nm 3-D Transistors

In this paper, we have devised on shallow trench isolation (STI) design considering leakage current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) in Bulk/silicon on insulator (SOI) FinFET and vertical FET (VFET). The ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ tendency is considered in terms of the interface trap density ( ${D}_{\textsf {it}}$ ) difference depending on the STI material type and STI thickness. In the case of Bulk FinFET, the STI design for each of high performance (HP) and low power (LP) is presented. On the other hand, in the case of SOI FinFET and VFET, STI designs which do not distinguish HP/LP are presented. Max lattice temperature ( ${T}_{\textsf {L,max}}$ )/thermal resistance ( ${R}_{\textsf {th}}$ )/on current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) degradation rate according to STI design in each structure are also analyzed. Finally, we compare the hot carrier injection (HCI)/bias temperature instability (BTI) lifetime as a function of the device temperature which is varied depending on STI design. In conclusion, our proposed STI design effectively reduces the self-heating effect in each structure and increases the HCI/BTI lifetime accordingly.

A Comparative Study of the Curing Effects of Local and Global Thermal Annealing on a FinFET

Recently, localized thermal annealing has been spotlighted as an effective method to cure aged devices. The degraded gate oxide can be successfully cured by local annealing, which utilizes Joule heat inherently generated in the device. But, despite this advantage, there has been no study comparing the curing effects with various other annealing methods. In this study, the curing effects of local annealing and a conventional global annealing method applied to SOI FinFETs are compared. The measured electrical characteristics are discussed to evaluate the damage curing with respect to curing level and variability.

Analysis and performance exploration of high performance (HfO2) SOI FinFETs over the conventional (Si3N4) SOI FinFET towards analog/RF design

Nowadays FinFET devices have replaced the MOS devices almost in all complex integrated circuits of electronic gadgets like computer peripherals, tablets, and smartphones in portable electronics. The scaling of FinFET is ongoing and the analog/RF performance is most affected by increased SCEs (short channel effects) in sub 22 nm technology nodes. This paper explores the analog/RF performance study and analysis of high performance device-D2 (conventional HfO2 spacer SOI FinFET) and device-D3 (source/drain extended HfO2 spacer SOI FinFET) over the device-D1 (conventional Si3N4 spacer SOI FinFET) at 20 nm technology node through the 3-D (dimensional) simulation process. The major performance parameters like Ion (ON current), Ioff (OFF current), gm (transconductance), gd (output conductance), AV (intrinsic gain), SS (sub-threshold slope), TGF = gm/Id (trans-conductance generation factor), VEA (early voltage), GTFP (gain trans-conductance frequency product), TFP (tans-conductance frequency product), GFP (gain frequency product), and fT (cut-off frequency) are studied for evaluating the analog/RF performance of different flavored SOI FinFET structures. For analog performance evaluation, device-D3 and D2 give better results in terms of gm, ID (drain current) and SS parameters, and for RF performance evaluation device-D1 is better in terms of fT, GTFP, TFP, and GFP parameters both at low and high values of VDS = 0.05 V and VDS = 0.7 V respectively.

3D numerical simulations of single-event transient effects in SOI FinFETs

The characteristics and mechanism of single-event transients in silicon-on-insulator (SOI) fin field-effect transistors (FinFETs) were analyzed using Sentaurus technology computer-aided design (TCAD) simulations based on the bipolar amplification effect. The results show that a typical single pulse mode of the transient leakage current is observed. The peak current and collected charge increase approximately linearly with increase of the linear energy transfer. The electric field in the depletion region of the FinFET body–drain junction increases significantly when the drain bias increases, resulting in a sharp increase in the drift current until reaching the saturation state. The variation of the bipolar gain and transient current with the position of incidence of the particle shows good consistency, reaching a maximum in the FinFET drain region, which indicates that the drain depletion region of SOI FinFETs is most sensitive to heavy-ion irradiation due to the bipolar amplification effect. The bipolar gain increases with decrease of the gate length and increase of the fin height and width.

Analysis of subthreshold SOI FinFET based two stage OTA for low power

In this paper, subthreshold design and analysis of Silicon on Insulator Fin Field Effect Transistor (SOI FinFET) based two stage Operational Transconductance Amplifier (OTA) is presented for low power and low supply voltage in nanometre regime. The OTA design optimization is achieved by $$g_{m}/I_{D}$$ methodology which helps to determine the device aspect ratios. Compactness is achieved by using nanometre FinFET technology. The OTA design is simulated using 30 nm SOI FinFET Berkeley Short-channel IGFET Common Multi-gate (BSIM-CMG) model, with bias current and supply voltage of 20 nA and $$\pm 0.5 V$$ ;respectively. The simulation results in subthreshold regime of FinFET based two stage OTA has a gain of 57 dB with a phase margin of 69.81 degree, Common Mode Rejection Ratio (CMRR) of 61.55 dB and power consumption of 108 nW.

Characterization and Optimization of Inverted-T FinFET Under Nanoscale Dimensions

In this paper, a p-type inverted-T FinFET (IT FinFET) has been optimally structured. Focus is made on analyzing the inferior characteristics reported from the previously fabricated IT FinFETs, and obtaining better performances through a novel structure. IT FinFET has a higher layout efficiency and can thus provide larger drain current ( ${I}_{D}$ ) under the same dimension as that of a silicon-on-insulator (SOI) FinFET by securing the extended channels of ultrathin body (UTB) on the field region. We closely observe the leverages of fin width ( ${W}_{\textsf {fin}}$ ), UTB height ( ${H}_{\textsf {UTB}}$ ), and gate length ( ${L}_{g}$ ) on the operation characteristics using a 3-D technology computer-aided design simulation with quantum-mechanical models. ${W}_{\textsf {fin}}$ below 10 nm is evaluated to be suitable for strong gate controllability. We first examine a critical ${H}_{\textsf {UTB}}$ , beyond which a higher drive current is not obtained even with a greater channel width than that of FinFET. When ${H}_{\textsf {UTB}} = \textsf {3}$ and 10 nm, IT FinFET yields 13.3% and 142% of saturation current improvement compared with SOI FinFET under the same footprint. At extremely scaled ${L}_{g}$ , although the immunity against short-channel effects is slightly weaker than that of SOI FinFET, optimally designed IT FinFET can produce a higher current and demonstrates shorter intrinsic delay times.

Performance Enhancement of FinFET Devices with Gate-Stack (GS) High-K Dielectrics for Nanoscale Applications

The Fin shaped Field Effect Transistors (FinFETs), are the front runner of the current sub-nanometer technology node. The semiconductor industry adopts it in high-performance (HP) and low-power (LP) applications due to greater electrostatic control and better scalability. This paper explores the numerically simulation based comparison of bulk and silicon-on-insulator (SOI) technology double gate (DG), triple gate (TG) FinFETs. The essential processing steps required to create the GS high-k dielectric bulk and SOI FinFETs are demonstrated. The electrical performance parameters of the device such as Ion/Ioff ratio, subthreshold swing (SS), and drain induced barrier lowering (DIBL) are extracted. Based on the three-dimensional (3D) ATLASTM simulation results, TG FinFET shows an ameliorated performance over DG in bulk and SOI technology as well. In order to control the short channel effects (SCEs), gate-stack (GS) high-k dielectrics are introduced with fixed thickness interfacial-layer (IL) and high-k dielectric material in between the gate material and semiconductor. The GS high-k dielectrics suppress the SCEs to large extent in both devices and technologies. The GS SOI FinFETs demonstrates the improved performance over the bulk counterpart and TG FinFET is the best among them. Further, the similar kind of investigation has been carried out for Tfin variations. These devices reveal the excellent control of SCEs when the fin is narrow. The ratio of SOI and bulk TG FinFET Ion/Ioff ratio with Tfin variations provide evidence that, the SOI based devices are competent for HP and LP applications.

Parasitic Capacitance and Resistance Model Development and Optimization of Raised Source/Drain SOI FinFET Structure for Analog Circuit Applications

Parasitic Capacitance and Resistance Model Development and Optimization of Raised Source/Drain SOI FinFET Structure for Analog Circuit Applications

A 10-bit 50-MS/s SAR ADC with 1 fJ/Conversion in 14 nm SOI FinFET CMOS

A 10-bit Successive Approximation Register (SAR) Analog to Digital Converter (ADC) was implemented in a 14 nm SOI FinFET CMOS technology, achieving 59.59 dB SNDR at 50 MS/s while consuming 41.3 µW power. Several techniques were used to increase the energy efficiency while ensuring the linearity. First, a segmented architecture with a 5-bit coarse ADC and an 11-bit fine ADC was used. The aligned Switching with Skip (ASS) method was used to generate the five MSBs of the fine ADC from the computed coarse ADC bits, saving 58% switching power compared with non-segmented architecture with merged capacitor switching (MCS) method. Second, VCM-based MCS scheme is used for SAR bit resolving, saving 85.72% switching power compared with traditional SAR switching. Third, the dual supply mode with analog at 0.8 V and digital at 0.4 V was used. This reduces the total digital logic power consumption by 23% comparing with that using the single supply at 0.8 V. The differential architecture was used to minimize the common mode non-idealities. The proposed ADC has been implemented in a 14 nm SOI FinFET technology and achieved a peak Figure of Merit (FoM) of 1.07 fJ/Conversion-step with simulation results.

Modelling of nanoscale multi-gate transistors affected by atomistic interface roughness

Interface roughness scattering (IRS) is one of the major scattering mechanisms limiting the performance of non-planar multi-gate transistors, like Fin field-effect transistors (FETs). Here, two physical models (Ando’s and multi-sub-band) of electron scattering with the interface roughness induced potential are investigated using an in-house built 3D finite element ensemble Monte Carlo simulation toolbox including parameter-free 2D Schrödinger equation quantum correction that handles all relevant scattering mechanisms within highly non-equilibrium carrier transport. Moreover, we predict the effect of IRS on performance of FinFETs with realistic channel cross-section shapes with respect to the IRS correlation length (Λ) and RMS height (). The simulations of the n-type SOI FinFETs with the multi-sub-band IRS model shows its very strong effect on electron transport in the device channel compared to the Ando’s model. We have also found that the FinFETs are strongly affected by the IRS in the ON-region. The limiting effect of the IRS significantly increases as the Fin width is reduced. The FinFETs with channel orientation are affected more by the IRS than those with the crystal orientation. Finally, Λ and are shown to affect the device performance similarly. A change in values by 30% (Λ) or () results in an increase (decrease) of up to in the drive current.

Comparison of bulk FinFET and SOI FinFET

In this study, we compare the differences and advantages between Bulk FinFET and SOI FinFET. The results are simulated by using the ISE TCAD software. By changing the parameters of the gate voltage, drain voltage and gate length to analysis which characteristic is better. Through the experiment results, we demonstrate that the SOI FinFET have the better characteristics than bulk FinFET[1].

Back-Biasing to Performance and Reliability Evaluation of UTBB FDSOI, Bulk FinFETs, and SOI FinFETs

FinFETs and ultrathin body and buried oxide fully depleted silicon on insulator (UTBB-FDSOI) are the main transistors currently used in advanced integrated circuits (ICs). The tunable electrical properties via back-biasing facilitate the threshold voltage adjustment and enable IC designers to achieve a highly efficient and low-power-consuming operation. This study compares the modulation rate before and after hot carrier stress (HCS) of bulk FinFETs, UTBB-FDSOI ( t BOX = 20 nm), and SOI FinFETs ( t BOX>150 nm) via back-biasing. Simplified back-impedance models are proposed based on the impact of back-biasing on electrical characterization. Additionally, HCS with back-biasing shows a higher impact on UTBB FDSOI than on bulk FinFETs during reliability test, implying that the t BOX plays a critical role in the modulation rate. The lifetime with HCS indicates that the bulk FinFETs exhibit faster downscaling degradation than UTBB FDSOI probably due to the nature of multigate devices whose vertical electrical field should increase faster than planer devices during scaling.

GaAs SOI FinFET: impact of gate dielectric on electrical parameters and application as digital inverter

In this paper, a GaAs SOI (silicon on insulator) FinFET is proposed. A comparative study between proposed GaAs FinFET and conventional Si FinFET is presented. The effects of dielectric constant (k) of gate dielectric material on electrical parameters like channel potential, drain current, and Ion/Ioff have been reported. Results show that as k raises, both Ion/Ioff and channel potential increases. Again the impact of k on short channel effects (SCEs) has been investigated. TCAD results show that as k increases subthreshold swing (SS) improves, drain induced barrier lowering (DIBL) degrades, and VT roll off occur. The impacts of k on gate capacitance (CGG) and intrinsic delay (τ) have been presented and they increases as k increases. A digital CMOS inverter is implemented through proposed FinFET and the effect of k on its delay parameter is estimated. Results shows that average delay increase as k increases.

Estimation of the Single-Event Upset Sensitivity of Advanced SOI SRAMs

The single-event upset (SEU) sensitivity of ultra-thin silicon on insulator (SOI), SOI FinFET, and NanoWireFET static random access memories (SRAMs) is investigated using a straightforward multiple-scale approach based on open source and commercial codes. Both Monte-Carlo and technology computer aided design (TCAD) tools are used to estimate the SEU cross section of innovative technologies. Heavy-ion experiments performed on transistors are used to validate TCAD models and 3-D device structures. TCAD simulations are then performed on 3-D SRAM cells to calculate the upset threshold for each technology. It is used as upset criterion in Monte-Carlo simulations of deposited energy in silicon microvolumes to estimate the SEU cross section of innovative SOI technologies. Finally, multiple-bit upsets are addressed to draw trends on the sensitivity of such highly scaled technologies to multiple events.

A Study of High-Low Frequency Charge Pumping Method on Evaluating Interface Traps in Bulk FinFETs

Charge pumping (CP) technology is a useful tool to measure interface traps in devices such as planar MOSFETs and SOI FinFETs but scarcely used in bulk FinFETs. In this paper, high-low frequency (HLF) CP was employed to test the interface traps in bulk FinFETs for the first time. Bulk FinFETs fabricated with different process parameters, such as interface areas, post deposition annealing (PDA) temperatures, interface layer (IL) deposition and high-κ(HK) layer deposition conditions, were charcaterized systematically. It is followed by the evaluation of gate leakage and breakdown voltage to demonstrate the validity of HLF CP test. Achieved results indicate that HLF CP is an accurate method to evaluate interface traps in bulk FinFETs. It is also found that the gate leakage is affected by the high frequency in tests. And frequencies higher than 2MHz in tests can lead to inaccurate results in as-fabricated bulk FinFETs.

The Impact of Charge Collection Volume and Parasitic Capacitance on SEUs in SOI- and Bulk-FinFET D Flip-Flops

Measured single-event (SE) heavy-ion data for comparable silicon on insulator (SOI) and bulk silicon FinFET D flip-flop (DFF) designs demonstrate a notably greater difference between the SOI and bulk responses, which has commonly been observed. Data show greater than $30\times $ in SE upset (SEU) LET threshold and 3 orders of magnitude decrease in saturated SE cross section for SOI FinFETs when compared to bulk FinFETs. The difference in SEU threshold is shown to be due to the saturation of SE transient (SET) pulsewidths at values that are comparable to feedback-loop delays of DFF design in the SOI technology. The feedback-loop delays in FinFET technologies are significantly impacted by the inherent parasitic capacitance. For the bulk technology, SET pulsewidths do not saturate due to charge collection from the substrate region.

FinFET Versus Gate-All-Around Nanowire FET: Performance, Scaling, and Variability

Performance, scalability, and resilience to variability of Si SOI FinFETs and gate-all-around (GAA) nanowires (NWs) are studied using in-house-built 3-D simulation tools. Two experimentally based devices, a 25-nm gate length FinFET and a 22-nm GAA NW are modeled and then scaled down to 10.7- and 10-nm gate lengths, respectively. A TiN metal gate work-function granularity (MGG) and line edge roughness (LER) induced variability affecting OFF and ON characteristics are investigated and compared. In the OFF-region, the FinFETs have over an order of magnitude larger OFF-current that those of the equivalent GAA NWs. In the ON-region, the 25/10.7-nm gate length FinFETs deliver 20/58% larger ON-current than the 22/10-nm gate length GAA NWs. The FinFETs are more resilient to the MGG and LER variability in the subthreshold compared to the GAA NWs. However, the MGG ON-current variability is larger for the 10.7-nm FinFET than that for the 10-nm GAA NW. The LER ON-current variability depends largely on the RMS height; whereas a 0.6-nm RMS height yields a similar variability for both FinFETs and GAA NWs. Finally, the industry preferred 〈110〉 channel orientation is more resilient to the MGG and LER variability in both architectures.