Silicon Carbide Epitaxial Layers Research Articles

SmartSiC™ Substrates: A Boon to Drain Metallization Process

We present results of epitaxial characterization and benchmarking of Silicon Carbide (SiC) epitaxial layers grown on both 6-inch commercially available SiC substrate and on SOITEC’s new generation SmartSiCTM substrate. Multi wafer reactor was utilized to avoid run-to-run variation. Schottky Barrier Diodes (SBD) and electrical test vehicles were fabricated to extract ideality factor, barrier height and ohmic contact resistance for benchmarking.

The investigation of initial decomposition paths of methyltrichlorosilane on (0001) and (000[formula omitted]) surfaces of 4H-SiC: A DFT study

Methyltrichlorosilane (CH3SiCl3, MTS), a favored precursor for chemical vapor deposition (CVD) process of silicon carbide (SiC) epitaxial layer fabrication in a wide variety of temperatures, has been investigated prevalently. In this work, the investigation focused on the initial decomposition paths of MTS with active surface sites on 4H-SiC surfaces. The surfaces employed in this study include both (0001) face and (0001¯) face, which represent Si face and C face, respectively. The decomposition pathways of MTS decomposed with the active surface sites of 4H-SiC surfaces were researched theoretically with employment of transition state theory (TST). The barriers of Gibbs free energies and the estimated reaction rate constants were acquired to discuss the decomposition reactivity of MTS with the active sites on 4H-SiC surfaces. This work shows that MTS has tendency to decompose on both (0001) face and (0001¯) face of 4H-SiC, the H and Cl atoms can be abstracted by active surface sites on (0001) face and (0001¯) face, and impingement of MTS to active surface sites on (0001) and (0001¯) surfaces can yield C-containing and Si-containing surface species.

Temperature Dependence of 3С-SiC Growth During Rapid Vacuum Thermal Silicon Treatment

The paper presents the results of a study of the structure, phase composition, and growth kinetics of silicon carbide epitaxial layers on silicon substrates during their rapid vacuum thermal treatment. Transmission electron microscopy revealed the formation of layers of the cubic polytype SiC (3C-SiC) on silicon during carbidization in the temperature range of 1000–1300 °C. It was found that the formation of SiC layers proceeds in two stages, characterized by different activation energies. In the lower temperature range from 1000 to 1150 °C, the activation energy of the SiC growth process is Ea = 0.67 eV, while in the temperature range from 1150 to 1300 °C, the activation energy increases by almost an order of magnitude (Ea = 6.3 eV), which indicates a change in the limiting physical process. It has been established that the type of conductivity and the orientation of the substrate affect the thickness of the formed SiC layers. In this case, the greatest thickness of silicon carbide layers is achieved on silicon substrates with (111) orientation of p-type conductivity.

Operational Control of Substrates and Epitaxial Layers of Silicon Carbide and Diamond by IR Spectroscopy

A set of efficient operational methods for post-growth determination of the kinetic parameters of charge carriers and impurity concentration in silicon carbide and diamond substrates and epitaxial layers, as well as layer thicknesses, by analyzing infrared (IR) reflection and absorption spectra, is presented.

Formation and propagation mechanism of complex stacking fault in 180 μm thick 4H-SiC epitaxial layers

The formation mechanism and propagation behavior of a complex stacking fault (SF) in thick silicon carbide epitaxial layers was investigated using depth-resolved section X-ray topography and ultraviolet photoluminescence (UVPL) imaging. The SF is initiated in the substrate by deflection of a threading screw dislocation onto two basal half planes creating a Frank fault. This fault propagates into the epitaxial layer and interacts with several threading mixed dislocations, which creates both Frank and Shockley SFs on the same basal plane. UVPL images using different spectral filters show various SF type conversions occurring during propagation of the complex SF.

Correlation of Extended Defects with Electrical Yield of SiC MOSFET Devices

The quality of the silicon carbide (SiC) epitaxial layer, i.e., layer homogeneities and extended defect densities, is of highest importance for high power 4H-SiC trench metal-oxide-semiconductor field effect transistors (Trench-MOSFET) devices. Especially, yield for devices with a large chip area is severely impacted by extended defects. Previously, devices had to be fully manufactured to effectively gauge the impact of a reduction in extended defect densities in the epitaxial layers on device yield. The production of devices such as Trench-MOSFETs is an extensive procedure. Therefore, a correlation between extended defects in the epitaxial layer and electrical device failure would allow to reliably estimate the impact of process changes during epitaxial layer deposition on electrical device yield.For this reason, n-type epitaxial layers were grown on around 1,000 commercially available 150 mm 4H-SiC Si-face substrates, which received a chemical wet cleaning prior to the epitaxy deposition. Substrates with lowest micro-pipe density from two different suppliers were used. The wafers were characterized with the corresponding device layout for defects utilizing surface microscopy as well as ultraviolet photoluminescence techniques. Subsequently, these wafers were used to produce more than 500,000 Trench-MOSFET devices. All devices have been tested on wafer level for their initial electrical integrity.With these methods a precise correlation between extended defects in the epitaxial layer and electrical failures on wafer level could be found. The influence of different substrates on the defect-based yield prediction regarding the electrical yield on wafer level is discussed. Additionally, a calculated kill-ratio is presented and the severity of defect classes on initial device failure, e.g., stacking faults, and their key failures modes are discussed.

The role of boron related defects in limiting charge carrier lifetime in 4H–SiC epitaxial layers

One of the main challenges in realizing 4H–SiC (silicon carbide)-based bipolar devices is the improvement of minority carrier lifetime in as-grown epitaxial layers. Although Z1/2 has been identified as the dominant carrier lifetime limiting defect, we report on B-related centers being another dominant source of recombination and acting as lifetime limiting defects in 4H–SiC epitaxial layers. Combining time-resolved photoluminescence (TRPL) measurement in near band edge emission and 530 nm, deep level transient spectroscopy, and minority carrier transient spectroscopy (MCTS), it was found that B related deep levels in the lower half of the bandgap are responsible for killing the minority carriers in n-type, 4H–SiC epitaxial layers when the concentration of Z1/2 is already low. The impact of these centers on the charge carrier dynamics is investigated by correlating the MCTS results with temperature-dependent TRPL decay measurements. It is shown that the influence of shallow B acceptors on the minority carrier lifetime becomes neutralized at temperatures above ∼422 K. Instead, the deep B related acceptor level, known as the D-center, remains active until temperatures above ∼570 K. Moreover, a correlation between the deep level concentrations, minority carrier lifetimes, and growth parameters indicates that intentional nitrogen doping hinders the formation of deep B acceptor levels. Furthermore, tuning growth parameters, including growth temperature and C/Si ratio, is shown to be crucial for improving the minority carrier lifetime in as-grown 4H–SiC epitaxial layers.

Dislocation-related leakage-current paths of 4H silicon carbide

Improving the quality of 4H silicon carbide (4H-SiC) epitaxial layers to reduce the leakage current of 4H-SiC based high-power devices is a long-standing issue in the development of 4H-SiC homoepitaxy. In this work, we compare the effect of different type of dislocations, and discriminate the effect of dislocation lines and dislocation-related pits on the leakage current of 4H-SiC by combining molten-KOH etching and the tunneling atomic force microscopy (TUNA) measurements. It is found that both the dislocation lines of threading dislocations (TDs) and the TD-related pits increase the reverse leakage current of 4H-SiC. The dislocation lines of TDs exert more significant effect on the reverse leakage current of 4H-SiC, which gives rise to the nonuniform distribution of reverse leakage current throughout the TD-related pits. Due to the different Burgers vectors of TDs, the effect of TDs on the reverse leakage current of 4H-SiC increases in the order to threading edge dislocation (TED), threading screw dislocation (TSD) and threading mixed dislocation (TMD). Basal plane dislocations (BPDs) are also found to slightly increase the reverse leakage current, with the leakage current mainly concentrated at the core of the BPD. Compared to the effect of TDs, the effect of BPDs on the reverse leakage current of 4H-SiC is negligible. Our work indicates that reducing the density of TDs, especially TMDs and TSDs, is key to improve the quality of 4H-SiC epitaxial layers and reduce the reverse leakage current of 4H-SiC based high -power devices.

Growth Mechanism of Semipolar AlN Layers by HVPE on Hybrid SiC/Si(110) Substrates.

In this work, the growth mechanism of aluminum nitride (AlN) epitaxial films by hydride vapor phase epitaxy (HVPE) on silicon carbide (SiC) epitaxial layers grown on silicon (110) substrates is investigated. The peculiarity of this study is that the SiC layers used for the growth of AlN films are synthesized by the method of coordinated substitution of atoms. In this growth method, a part of the silicon atoms in the silicon substrate is replaced with carbon atoms. As a result of atom substitution, the initially smooth Si(110) surface transforms into a SiC surface covered with octahedron-shaped structures having the SiC(111) and SiC() facets. The SiC(111)/() facets forming the angle of 35.3° with the original Si(110) surface act as “substrates” for further growth of semipolar AlN. The structure and morphology of AlN films are investigated by X-ray diffraction (XRD), scanning electron microscopy (SEM), reflection high-energy electron diffraction (RHEED) and Raman spectroscopy. It is found that the AlN layers are formed by merged hexagonal microcrystals growing in two directions, and the following relation is approximately satisfied for both crystal orientations: AlN()||Si(110). The full-width at half-maximum (FWHM) of the X-ray rocking curve for the AlN() diffraction peak averaged over the sample area is about 20 arcmin. A theoretical model explaining the presence of two orientations of AlN films on hybrid SiC/Si(110) substrates is proposed, and a method for controlling their orientation is presented.

Formation of epitaxial 3C-SiC layers on Si by rapid vacuum thermal processing

The results of a study of the structure and phase composition of epitaxial layers of silicon carbide (SiC) formed on silicon substrate with orientation (100) under rapid vacuum thermal processing are presented. Planar-view transmission electron microscopy investigation revealed the formation of epitaxial layers of cubic polytype SiC (3C-SiC) on silicon in the process of carbidisation at 1100 °C during 30 s, using a gas mixture of propane (10 %) and argon (90 %) as a carbon source. The formation of a monocrystalline 3C-SiC with polycrystalline inclusions and twins on all possible planes {111} was found. A rather narrow band of 793 cm–1 transverse optical phonon mode SiC on Raman spectra confirms the formation of a cubic polytype SiC. It is noted that the presence of a 180 cm–1 spectral line and a 793 cm–1 half-width band on Raman spectra indicate the presence of deformation defects in SiC.

Phase Transitions in Silicon-Carbide Epitaxial Layers Grown on a Silicon Substrate by the Method of the Coordinated Substitution of Atoms

Phase Transitions in Silicon-Carbide Epitaxial Layers Grown on a Silicon Substrate by the Method of the Coordinated Substitution of Atoms

Surface Kinetic Mechanisms of Epitaxial Chemical Vapour Deposition of 4H Silicon Carbide Growth by Methyltrichlorosilane-H2 Gaseous System.

The chemical vapour deposition (CVD) technique could be used to fabricate a silicon carbide (SiC) epitaxial layer. Methyltrichlorosilane (CH3SiCl3, MTS) is widely used as a precursor for CVD of SiC with a wide range of allowable deposition temperatures. Typically, an appropriate model for the CVD process involves kinetic mechanisms of both gas-phase reactions and surface reactions. Here, we proposed the surface kinetic mechanisms of epitaxial SiC growth for MTS-H2 gaseous system where the MTS employed as the single precursor diluted in H2. The deposition face is assumed to be the Si face with a surface site terminated by an open site or H atom. The kinetic mechanisms for surface reactions proposed in this work for MTS-H2 gaseous system of epitaxial growth of SiC by CVD technique from mechanisms proposed for H-Si-C-Cl system are discussed in detail. Predicted components of surface species and growth rates at different mechanisms are discussed in detail.

Design, fabrication and test of a bulk SiC MEMS accelerometer

The application of micro accelerometer in extremely high temperature environment has become an urgent problem to be solved. However, current microelectromechanical system (MEMS) Si-based accelerometer cannot adapt to higher temperatures than 500 °C. Because of its excellent properties in high temperature environments, silicon carbide (SiC) shows promising potential in development of high temperature MEMS sensors, and it is a good alternative to Si for developing accelerometers. Due to the difficulty of bulk-SiC fabrication process and the complex structure of MEMS accelerometers, there are few studies on bulk SiC accelerometers and few test data of the performance. In this study, in order to solve the problem of fabrication, a MEMS accelerometer based on bulk SiC processing technology is designed, and fabricated. The sensor is fabricated using a 4H-SiC wafer and adopts the classic elastic beam-proof mass structure. The top surface of the wafer is a doped N-type SiC epitaxial layer that is used as piezoresistive material to develop sensitive resistance. Ultra-thin (20 μm) elastic beams obtained using dry etching form the sensitive mechanical structure to realize a high-sensitivity output in low/medium-g-value environments. The static flip and dynamic vibration experiments show that the final sensor can test low/medium-g-value acceleration signals precisely. Finally, the dynamic sensitivity obtained is 0.21 mV/g under 5 V input voltage and the linearity is 99.8%. This work has potential value for promoting the practical application of fabrication of bulk micromachined SiC in accelerometer, and the test data can provide guidance for future design of bulk SiC piezoresistive sensors.

Thermodynamics, kinetics, and technology of synthesis of epitaxial layers of silicon carbide on silicon by coordinated substitution of atoms, and its unique properties. A review

Thermodynamics, kinetics, and technology of synthesis of epitaxial layers of silicon carbide on silicon by coordinated substitution of atoms, and its unique properties. A review

Recognition of dislocation structure of silicon carbide epitaxial layers by а neural network

Technological features of the growth of single crystal silicon carbide inevitably create condi-tions for the formation of crystal structure defects in them. A method is proposed for recognizing and analyzing a dislocation structure of single crystal silicon carbide based on the use of optical microscopy and a direct distribution neural network. The method was tested on homoepitaxial lay-ers of 4H-polytype silicon carbide. Software has been developed that allows building maps of the dislocation structure distribution over the surface of single crystal silicon carbide. The software was tested on digital images of the surface of silicon carbide epitaxial layers. The accuracy of recognition of dislocation structure was 95%. The dislocation mapping is used in the development of process technologies for reducing their density during the growth of single crystals.

Influence of CMP damage induced during flattening SiC epitaxial layer on device performances

Thick silicon carbide (SiC) epitaxial layers, which are required for the fabrication of SiC ultra-high voltage devices, have to be flattened by chemical mechanical polishing (CMP) in order to eliminate bunched-step segments, shallow pits, and epi-crowns. However, the negative effects of CMP on device performance is concerning. In this research, we attempted to evaluate a SiC epitaxial layer surface after flattening by CMP and to clarify the extent of CMP damage on the performance of a 4H–SiC PiN diode. As a result, a bundle of dislocation half-loops, which were detected by a mirror electron microscope (MEM) inspection system (Hitachi High-Technologies Mirelis VM-1000), was found to occur beneath the epitaxial layer surface flattened by CMP and led to current leakage of the PiN diode.

The Amplitude Defect of SiC Detectors during the Recording of Accelerated Xe Ions

The properties of detectors based on epitaxial layers of silicon carbide (SiC) are presented. It is shown that the developed detectors have good spectrometric characteristics when detecting a particles with energies of up to 8 MeV. The pulse height defect was measured in SiC detectors under irradiation by accelerated xenon ions with different energies. It is shown that this parameter in the spectroscopic analysis of Xe ions is ∼45% of the true energy of the particles in question.

Structure and Hardness Evolution of Silicon Carbide Epitaxial Layers Irradiated with He+} Ions

Structure and Hardness Evolution of Silicon Carbide Epitaxial Layers Irradiated with He⁺} Ions

Stress Characterization of the Interface Between Thermal Oxide and the 4H-SiC Epitaxial Layer Using Near-Field Optical Raman Microscopy.

Stresses induced in the silicon carbide (SiC) epitaxial layer near the interface between thermal silicon oxide and 4H-SiC epitaxial substrate were measured using a near-field optical Raman microscope equipped with a hollow pyramid probe (aperture size: approximately 250 nm). The E2 phonon was observed to undergo a 0.17 cm-1 redshift owing to reduction in oxide-layer thickness from 300 nm to 0 nm; this result was compared against that obtained using a standard Raman microprobe sans the pyramidal probe. The result indicates that the epitaxial layer near the SiO2-4H-SiC interface was maintained under a constant tensile stress of the order of 50 MPa. This agrees well with the result obtained using the finite element method (FEM). Based on results obtained using the said Raman microprobe and Fourier transform infrared (FT-IR) measurements, use of an inhomogeneity formation model at the SiO2-4H-SiC interface has been proposed in this study.

Effect of Defects in Silicon Carbide Epitaxial Layers on Yield and Reliability

Inline metrology tools are widely used to detect defects in SiC epitaxial layers. The defect statistics are used in a variety of ways to determine quality, pass/fail and screen affected die. In this work, we document the automated detection and classification of various epitaxial defects based on type and origin. We further classify these categories into killer and non-killer defects and compare them to the electrical yield of Schottky Diodes. The origins of these defects are determined in broad categories, resulting in a clustering and yield-scaling model, which agrees very closely to experimental data. Further, we look at on-wafer screening techniques of potential weak die by both defect tagging and unclamped inductive switching (UIS) stress testing. Successful 1000-hr reliability tests show the robustness of our detection and screening methods.