Silicon Capacitors Research Articles

An Optimized Device Structure with a Highly Stable Process Using Ferroelectric Memory in 3D NAND Flash Memory Applications

In this paper, we propose an optimized device structure with a highly stable process that addresses threshold voltage shift issues in the String-Select-Line (SSL) and Ground-Select-Line (GSL) gates using ferroelectric memory in 3D NAND flash memory applications. The proposed device utilizes nickel (Ni) instead of tungsten (W) for the GSL and SSL gates, enabling optimized polarization properties during the annealing process and leveraging the disparity in thermal expansion coefficients. Notably, the difference in thermal expansion coefficient from tungsten (W), employed in other Word Line (WL) gates, allows effective control over polarization properties. To validate the proposed structure, we fabricated and measured a Metal–Ferroelectric–Insulator–Silicon (MFIS) capacitor utilizing Hafnium–Zirconium Oxide (HZO) material. The measurement results indicate that a change in the upper metal layer results in a more than fivefold increase in the variance of polarization characteristics between the WL gates (responsible for the memory function) and the SSL and GSL gates dedicated to channel control. In addition, process simulation was conducted using the same device structure, confirming the application of tensile stress to the HZO thin film in the case of a W electrode and compressive stress in the case of a Ni electrode. Furthermore, applying this controlled polarization characteristic parameter to the 3D NAND flash memory structure revealed a reduction in the threshold voltage shift of the control gate from a previous change of 2.6 V or more to 0.05 V, facilitating stable control.

(Invited) 3D Silicon Capacitors in the Frantic Race Towards Ultra High Integration in Advanced Packages

The evolution of the semiconductor industry has led the manufacturers to shift from microelectronics to nanoelectronics. This is the accomplishment of a continuous race towards the ultraminiaturization combined with performances enhancement. The result is depicted in impressive modules where we can observe an heterogeneous integration of components in the package. This paper will explain the progress made in the integration of Silicon capacitors in different fields such as the capacitance, the design , the parasitics , the thickness ,the usage. It will be illustrated by the numerous possibilities of integration . The portfolio of the different technologies used to make high reliability Silicon capacitors will be described and the corresponding performances and advantages will be exposed for each market : Mobile , Medical, Power electronics and Communication .

Negative capacitance silicon nanotube FET: a subthreshold modeling exploration of sub-60 mV/decade swing, negative drain-induced barrier lowering, and threshold voltage roll-off

Negative capacitance silicon nanotube FET: a subthreshold modeling exploration of sub-60 mV/decade swing, negative drain-induced barrier lowering, and threshold voltage roll-off

The numerical study on performance evaluation of a thermal switch capacitor in a magnetocaloric cooling device.

Compact, solid thermal control devices offer a new way to control the intensity and direction of heat flow between the components of a system, which is crucial for both optimized performance and safety. In this work we study a thin, silicon thermal switch capacitor (TSC) used for heat transport in a magnetocaloric cooling system. A numerical model was developed to quantify the effects of various operating conditions and design parameters on the performance of a magnetocaloric device with an embedded TSC. Based on realistic material properties, a maximum cooling-power density of 4000 Wm-2 (2025 ) was obtained for a zero temperature span and an operating frequency of 20Hz. The use of the presented device was demonstrated on a battery system, motivating further experimental studies to develop a new, compact cooling device that can be directly attached to a heat reservoir, making it desirable for a variety of applications.

53 GBd PAM-4 fully-integrated silicon photonics transmitter with a hybrid flip-chip bonded laser

We present a fully-integrated single-lane 53 GBd PAM-4 silicon photonics (SiPh) transmitter (Tx) with a flip-chip bonded laser diode (LD). The LD is butt-coupled to a Si edge coupler including a SiO2 suspended spot-size converter. The coupled power exceeds 10 dBm with a 1 dB allowable misalignment of 2.3 µm. The RF and eye performances of the Tx are evaluated. Extinction ratio >5 dB is obtained at 3.5 Vppd voltage swing. Aided by silicon capacitors, the Tx decouples parasitic inductances leading to remarkable improvements in the eye openings and transmitter dispersion eye closure quaternary by 1.16 dB. By implementing the fully-integrated Tx with driver packaging, we successfully demonstrate 106 Gb/s real-time operation satisfying KP4-FEC threshold at -5 dBm receiver sensitivity.

Vibrational fingerprints of ferroelectric HfO2

Hafnia (HfO2) is a promising material for emerging chip applications due to its high-κ dielectric behavior, suitability for negative capacitance heterostructures, scalable ferroelectricity, and silicon compatibility. The lattice dynamics along with phononic properties such as thermal conductivity, contraction, and heat capacity are under-explored, primarily due to the absence of high quality single crystals. Herein, we report the vibrational properties of a series of HfO2 crystals stabilized with yttrium (chemical formula HfO2: xY, where x = 20, 12, 11, 8, and 0%) and compare our findings with a symmetry analysis and lattice dynamics calculations. We untangle the effects of Y by testing our calculations against the measured Raman and infrared spectra of the cubic, antipolar orthorhombic, and monoclinic phases and then proceed to reveal the signature modes of polar orthorhombic hafnia. This work provides a spectroscopic fingerprint for several different phases of HfO2 and paves the way for an analysis of mode contributions to high-κ dielectric and ferroelectric properties for chip technologies.

Hybrid Design of an Optical Detector for Terrestrial Laser Range Finding

This paper presents the integration of an InGaAs avalanche photodiode (APD)with the first amplification stage, comprised of a low capacitance silicon N-channel dual-gate MOS-FET and associated passive components, in the APD case. This combined linear mode optical hybrid detector is used in the field of terrestrial laser range finding. In this case, a reduction of input capacitance by 0.7 pF and an improvement of signal-to-noise ratio (SNR) at lowbackground noise conditions by 32 percent when compared to the equivalent discrete detector was measured. When integrated in a laser range finding system at very strong daylight conditions an improvement in SNR by approximately 10 percent was achieved. Furthermore a significant improvement in immunity to electromagnetic interference (EMI) is shown. Finally, when used in an eye-safe mobile laser range finding system, ranging beyond 10 km with an accuracy of ±2 m on non-cooperative targets using this hybrid detector is demonstrated.

Design of an Extreme Low Cutoff Frequency Highpass Frontend for CMOS ISFET via Direct Tunneling Principle

In this work, ISFET frontends utilising the direct tunneling current to eliminate trapped charge are proposed. The principle has been investigated and verified via silicon-imitated ISFET first, where silicon capacitors are used to imitate the passivation ones. Because the dominant tunneling components depend on the potential difference between Gate and Drain terminals, a source-follower structure could itself perform a highpass filter with time constant at 10-100 seconds level. Additionally, a time-constant regulation mechanism is presented by feeding the output signal back to the drain terminal of ISFETs, achieving a regulation factor over 50, namely from 4.7 seconds to 243.4 seconds in our implementation. Afterwards in chemical test, proposed ISFETs have been verified in terms of unit passivation capacitance, linearity, noise and sensitivity for ISFETs with 3 different top metal areas. It is found that approximately 30 mV/pH sensitivity can be achieved, and for the first time we managed to derive the relation between chemical flicker noise and sensing metal area.

Development of highly reliable BiFeO3/HfO2/Silicon gate stacks for ferroelectric non-volatile memories in IoT applications

We have investigated the structural, electrical, and ferroelectric properties of metal–ferroelectric-high-k-silicon capacitors with BiFeO3 ferroelectric films deposited on the HfO2/Si substrate. BiFeO3, HfO2 films, and their stack were deposited on the silicon substrate using RF magnetron sputtering and plasma-enhanced atomic layer deposition (PEALD). Film crystal orientation, refractive index, and absorption constant parameters were extracted from X-ray diffraction and ellipsometric analysis. Electrical characterization of metal/ferroelectric/metal (MFM), metal/ferroelectric/silicon (MFS), metal/dielectric/silicon (MIS), and metal/ferroelectric/insulator/silicon (MFIS) capacitor structures provide memory window, leakage current density, hysteresis, fatigue, and data retention time. The metal/ferroelectric/silicon structure exhibits clockwise capacitance–voltage characteristics with the memory window of 5.04 V for the bias voltage of ± 10 V. The electrical and ferroelectric characteristics of MFIS structures were studied for different thicknesses of HfO2 layer, which shows that the introduction of high-k dielectric film between ferroelectric and silicon improves the interface quality. The memory window of the MFIS structure was found to significantly increase to 9.65 V with the introduction of a 10 nm HfO2 layer between the ferroelectric layer and the silicon substrate. Two-order reduction in the leakage current density was also observed in the MF(200 nm)I(10 nm)S structure as compared to the MF(200 nm)S structure. The fabricated MF(200 nm)I(10 nm)S gate stack shows fatigue resistance for read/write operations greater than 1012 cycles and data retention time for greater than 104 s. To the best of author’s knowledge, this is the first investigation to integrate pure BiFeO3 on PEALD-HfO2 dielectric for the gate stack of ferroelectric field effect transistors.

High Bandwidth Capacitance Efficient Silicon MOS Modulator

This article analysed and optimised horizontal Silicon insulator Silicon capacitor (H-SISCAP) phase shifter structures with insulator thickness tox up to 40 nm. The phase shifter has an effective capacitance ( C eff) around 0.5 fF/μm and a phase change efficiency 1.8 V ·cm, of which the balance between capacitance and phase efficiency is comparable with silicon rib waveguide based depletion type phase shifters. Silicon Mach–Zehnder interferometer (MZI) modulators with 200 μm long H-SISCAP phase shifters optimised for TM polarised light have been fabricated and demonstrated with a 3 dB EO bandwidth above 35 GHz and intrinsic H-SISCAP RC bandwidth around 150 GHz. The modulator displays open eye-diagrams for data rates up to 60 Gbit/s without detection equalization and 72 Gbit/s with 2 taps equalization in NRZ-OOK operation. The demonstrated H-SISCAP phase shifter paves the way to build high bandwidth segmented, travelling wave and compact ring resonators modulators for applications of optical transmitters, microwave generations, and LIDAR applications, etc.

Structural and electrical properties of Al/BiFeO3/ZrO2/n-Si structure for non-volatile memory application

In this communication, the structural and electrical properties of metal–ferroelectric–insulator–silicon (MFIS) capacitor structure have been reported for non-volatile memory applications. Sol–gel with spin coating and rf sputtering process have been used for depositing BiFeO3 (BFO) and ZrO2 films, respectively. It has been observed that BFO film shows pure ferroelectric phase, uniform grain size and maximum refractive index at annealing temperature of 500 °C. Thermo-gravimetric analyzer and differential scanning calorimetry analysis indicate good agreement with X-ray diffraction of BFO film. In ZrO2 thin film, it has been observed that ZrO2 is in amorphous state at all annealing temperatures and the maximum refractive index has been found at annealing temperature of 400 °C. Al/ZrO2/n-Si (MIS), Al/BiFeO3/n-Si (MFS) and Al/BiFeO3/ZrO2/n-Si (MFIS) structures have been fabricated to investigate the electrical characteristics. The memory window has been observed by capacitance–voltage (C–V) characteristics and it improves from 1.9 V in MFS structure to 5.4 V in MFIS structure with 8 nm dielectric layer. Leakage current density has been observed by current density–gate voltage (J–V) characteristics and it is order of 10−5 A/cm2 in MF150 nmI8 nmS structure. No charge value degrades up to 1012 iteration cycles in MF150 nmI8 nmS structure.

Lanthanum-doped BiFeO3/ZrO2 gate stack for ferroelectric field effect transistors

A metal–ferroelectric–insulator–semiconductor (MFIS) structure was fabricated with lanthanum (La)-doped BiFeO3 as ferroelectric and ZrO2 as the high-k insulator layer. The BiFeO3 film with 5 M doped La was prepared with sol–gel and ZrO2 film was physically deposited with rf sputtering. Films structural characteristics were obtained using X-ray diffraction and scanning electron microscopy (SEM). The ferroelectric film shows the perovskite structure with orientation (110)/(104) when annealed in the range from 400 to 700 °C. The dielectric film shows an amorphous structure for the same range of annealing temperature. Electrical and ferroelectric properties were obtained by fabricating and characterizing metal/ferroelectric/silicon (MFS), metal/ferroelectric/metal (MFM), metal/insulator/silicon (MIS), metal/ferroelectric/insulator/metal (MFIM) and metal/ferroelectric/insulator/silicon (MFIS) capacitor structures with ferroelectric film of 200 nm thickness and dielectric film of various thicknesses. MFS structure shows a maximum memory window of 3.5 V and leakage current density of 1.4 × 10–8 A/cm2 with ferroelectric film annealed at 500 °C. The memory window was further improved to 6.62 V and leakage current to the order 10–10 A/cm2 with the introduction of 9 nm insulator layer between ferroelectric and silicon. The same device shows an excellent endurance property tested for 1012 cycles and data retention tested for 5.56 h. The device shows a breakdown of 43 V, which is 9 V higher than the MFS structure. To the best of author’s knowledge, this is the first report to integrate La-doped BiFeO3 on ZrO2 (high-k) dielectric for non-volatile memory applications.

Enhancement of ESD performances of Silicon Capacitors for RFID solutions

Abstract Radio-Frequency IDentification devices such as smart cards and RFID tags are based on the presence of a resonant tuned LC circuit associated to the RFID Integrated Circuit (IC). The use of discrete capacitor, external to the IC gives greater flexibility and design freedom. In the race of miniaturization, manufacturers of RFID devices always require smaller electronic components. To save space and in the same time improve performances, capacitors are exposed to height and volume constraints. In the same time, the capacitor has to withstand ESD stresses that can occur during the assembly of the device and during operation. Murata has developed a unique thin capacitor technology in silicon. This paper reports the development of a range of low profile capacitors with enhanced ESD performances. The manufacturing process optimization and the design adjustments will be presented here. The process was optimized by taking into account the main electrical parameters: leakage current, breakdown voltage, capacitance density, capacitance accuracy, Equivalent Series Resistance (ESR) and Self-Resonant Frequency (SRF). The dielectric stack was defined in order to integrate up to 330pF in 0402 case. The process architecture, based on accurate planar capacitor with thick dielectric will be discussed. With this architecture there is no constraint to reach low thickness, such as 100μm or even lower. The ESD threshold of each Silicon Capacitor was investigated with design variations associated to Human Body Model measurements. A Single Project Wafer (SPW) was founded with 36 different capacitor designs. Design modulations specifically addressed the orientation and position of the contacts openings. Special care was taken to maximize the width of the contact holes and metal tracks. A mosaic approach, constructed out of a massive network of parallelized elementary cells was also implemented, so that the charges of the ESD pulse do not concentrate at the same place, leading to electrical failure. Examples of defects due to ESD stress will be shown with failure analysis cross-sections and ways to enhance the ESD threshold by design will be illustrated.

Impact of HfO2 buffer layer on the electrical characteristics of ferroelectric/high-k gate stack for nonvolatile memory applications

For the proposed work, the electrical properties of metal–ferroelectric–insulator–silicon (MFeIS) capacitors with Sr0.8Bi2.2Ta2O9 (SBT) ferroelectric film deposited on HfO2/Si substrate have been investigated. The SBT film was deposited by RF sputtering and HfO2 film by plasma-enhanced atomic layer deposition (PEALD). The structural characteristic of the deposited ferroelectric and dielectric films was obtained using X-ray diffraction and multiple angle ellipsometric analysis. XRD results indicate the polycrystalline and perovskite structure of the SBT film and amorphous structure of the HfO2 film annealed at different temperatures. SBT film deposited on the silicon substrate and annealed at 500 °C shows the maximum refractive index of 3.46 with the maximum grain size of 32 nm. Metal/ferroelectric/silicon (MFeS), metal/ferroelectric/metal (MFeM), metal/insulator/silicon (MIS) and metal/ferroelectric/insulator/silicon (MFeIS) structures were fabricated to obtain the electrical and ferroelectric properties. MFeIS structure with 10 nm buffer layer shows the improved memory window of 5 V as compared to the 3.07 V in the MFeS structures. MFeI(10 nm)S structure even shows endurance higher than 1012 read/write cycles and data retention for more than 8 h.

The application of the scallop nanostructure in deep silicon etching

Micro/nanostructures with high aspect ratios in silicon wafers obtained by plasma etching are of great significance in device fabrication. In most cases, the scallop nanostructure in deep silicon etching should be suppressed. However, the scallop nanostructure could be applied in electronic device fabrication as characteristic information, which indicates the balance between deposition and etching. In this work, the applications of scallop nanostructures in etching process optimization and environmental protection are demonstrated. In addition, the minimum effect of the cycle time on the scallop size is reported for the first time. These results could bring new thoughts to the electronic devices related fields, such as micro-electro-mechanical systems (MEMS), silicon capacitors and advanced packaging.

Investigation of Temperature and Source/Drain Overlap Impact on Negative Capacitance Silicon Nanotube FET (NC Si NTFET) with Sub-60mV/decade Switching

In this paper, the impact of temperature and source/drain overlap on DC characteristics and analog/RF performance of the negative capacitance silicon nanotube FET (NC Si NTFET) have been presented. The performance of the device is examined by coupling the 3D TCAD numerical simulation with 1D Landau-Khalatnikov (LK) equation. The effect of negative capacitance has been investigated for different source/drain overlap lengths (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ov</sub> ) at 300 K and 380 K. The optimal values of source/drain overlap lengths and effective ferroelectric thickness (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</sub> ) have been found to attain significant improvement in device performance in terms of drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">d</sub> ), subthreshold swing (SS), gate capacitance (C <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> ), and cut-off frequency (f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> ). It is reported that a minimum SS of 30.7 mV/decade, and maximum f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</sub> of 2.35 THz are achieved for NC Si NTFET at 300 K for an operating frequency of 1 GHz. It is observed that the core (inner gate) radius (t <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">c</sub> ) can be used to increase the minimum SS and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> to delay the hysteresis and to achieve a better drive current.

Three-dimensional silicon-integrated capacitor with unprecedented areal capacitance for on-chip energy storage

Capacitors are the most critical passive components of future in-package and on-chip electronic systems with augmented energy-storage capabilities for consumer and wearable applications. Although an impressive increase of both capacitance and energy densities has been achieved over the last years for supercapacitors (SCs), electronic applications of SCs have been hindered by their intrinsic low operation voltage (a few Volts), poor frequency range (a few Hz to hundreds of Hertz), and difficult integration with integrated circuit (IC) processes. On the other hand, integrated dielectric capacitors (DCs) able to operate at higher voltage (tens of Volts) and higher frequencies (hundreds of kHz to MHz) suffer from significantly lower capacitance and energy densities.Here, we leverage the unique atomic layer deposition of conductive (TiN) and dielectric (Al2O3 and HfAlOx) nanocoatings (20 and 40 nm) into trenches etched in silicon with ultra-high aspect-ratio (up to 100) to integrate 3D microcapacitors with areal capacitance up to 1 μF/mm2. This sets the new record for silicon capacitors, both integrated and discrete, and paves the way to on-chip energy storage. The 3D microcapacitors feature excellent power and energy densities, namely, 566 W/cm2 and 1.7 μWh/cm2, respectively, which exceed those of most DCs and SCs. Further, the 3D microcapacitors show excellent stability with voltage (up to 16 V) and temperature (up to 100 °C), over 100 h of continuous operation.

A Novel Fabrication Process for High Density Silicon Capacitors by using Metal-Assisted Chemical Etching

Abstract In silicon capacitors, it is most important to increase the surface area of the surface forming the capacitor. In conventional silicon capacitors, trenches are generally formed in silicon wafer using reactive ion etching (RIE) method to expand their surface area. However, with this method, the depth of trenches that can be formed was limited. Furthermore, since RIE method processes silicon wafer only one by one, productivity is low. In this paper, Metal-assisted Chemical Etching (MacEtch) is proposed as a novel method of fabricating high-density silicon capacitors to solve the problems. We used gold formed by electroless plating as a catalyst and controlled them by forming conditions. As a result, vertical trenches greater than 100 μm depth and less than 1 μm width could be formed on a silicon wafer. The silicon wafer on which these trenches are formed has a surface area 100 times or more as compared with the case where there is no trench. We formed a dielectric film and electrodes on these trench surfaces. Consequently, we have realized a silicon capacitors with a capacitance density as high as 200 nF / mm2 or more.

The Characteristics of Transparent Non-Volatile Memory Devices Employing Si-Rich SiOX as a Charge Trapping Layer and Indium-Tin-Zinc-Oxide

We fabricated the transparent non-volatile memory (NVM) of a bottom gate thin film transistor (TFT) for the integrated logic devices of display applications. The NVM TFT utilized indium–tin–zinc–oxide (ITZO) as an active channel layer and multi-oxide structure of SiO2 (blocking layer)/Si-rich SiOX (charge trapping layer)/SiOXNY (tunneling layer) as a gate insulator. The insulators were deposited using inductive coupled plasma chemical vapor deposition, and during the deposition, the trap states of the Si-rich SiOx charge trapping layer could be controlled to widen the memory window with the gas ratio (GR) of SiH4:N2O, which was confirmed by fourier transform infrared spectroscopy (FT-IR). We fabricated the metal–insulator–silicon (MIS) capacitors of the insulator structures on n-type Si substrate and demonstrated that the hysteresis capacitive curves of the MIS capacitors were a function of sweep voltage and trap density (or GR). At the GR6 (SiH4:N2O = 30:5), the MIS capacitor exhibited the widest memory window; the flat band voltage (ΔVFB) shifts of 4.45 V was obtained at the sweep voltage of ±11 V for 10 s, and it was expected to maintain ~71% of the initial value after 10 years. Using the Si-rich SiOX charge trapping layer deposited at the GR6 condition, we fabricated a bottom gate ITZO NVM TFT showing excellent drain current to gate voltage transfer characteristics. The field-effect mobility of 27.2 cm2/Vs, threshold voltage of 0.15 V, subthreshold swing of 0.17 V/dec, and on/off current ratio of 7.57 × 107 were obtained at the initial sweep of the devices. As an NVM, ΔVFB was shifted by 2.08 V in the programing mode with a positive gate voltage pulse of 11 V and 1 μs. The ΔVFB was returned to the pristine condition with a negative voltage pulse of −1 V and 1 μs under a 400–700 nm light illumination of ~10 mWcm−2 in erasing mode, when the light excites the electrons to escape from the charge trapping layer. Using this operation condition, ~90% (1.87 V) of initial ΔVFB (2.08 V) was expected to be retained over 10 years. The developed transparent NVM using Si-rich SiOx and ITZO can be a promising candidate for future display devices integrating logic devices on panels.

Modeling and Analysis of Optical Modulators Based on Free-Carrier Plasma Dispersion Effect

Silicon photonic networks are revolutionizing computing systems by improving the energy efficiency, bandwidth, and latency of data movements. Optical modulators, such as microresonators (MRs) and Mach–Zehnder interferometers (MZIs), are the basic building blocks of silicon photonic networks. This paper proposes a SPICE-compatible electro-optical co-simulation model, basic optical switch integration model (BOSIM), to systematically study optical modulators using PN, PIN, and metal–insulator–silicon (MIS) capacitor device technologies. BOSIM holistically models both transient and steady state properties, such as switching speed, power, transmission spectrum, area, and carrier distribution. BOSIM is validated by the measured data from eight research groups and companies. Compared to MRs, BOSIM shows MZIs are fast, with a high extinction ratio and large bandwidth but in the sacrifice of loss, energy, and area. Using a PIN diode over a PN diode can save area, but retain the loss and energy, while an MIS capacitor has the shock response of carrier distribution in a narrow range and is marginalized gradually. For instance, an MZI can achieve a $2.5 {\times }$ bit rate, $6.06{\times }$ extinction ratio, $71.04 {\times }\,\,3$ -dB bandwidth, but costs at least $1.93 {\times }$ passing loss, $1.46 {\times }$ energy consumption, and $16.67 {\times }$ area, compared with MR.