TiSi2 can be used as a shunting layer to decrease the resistance of the poly-Si lines used as interconnections in integrated Si technology. In this work the correlation between the silicide thickness, the silicide surface roughness, the silicide grain size, the dopants in Si, and the crystallinity of Si was investigated on unpatterned wafers. The results will be used as reference in a further study of silicide formation on sub-micron poly-Si lines. After silicide formation at 700°C, the surface roughness has been found to be strongly dependent on the thickness of the silicide layer formed. The dopants in the Si did not only retard the formation of the C49 phase, but also hindered the transformation of TiSi2 from the C49 to the low resistive C54 phase. The surface roughness did not change when a second annealing step at 850°C was used to transform the silicide from the C49 phase to the C54 phase.
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