Signed-digit Number System Research Articles

Implementation three-step algorithm based on signed digit number system by using neural network

The need for a simple and effective system that works with high efficiency features such as high processing speed, the ability to solve problems by learning method and accomplish the largest amount of data processing accurately and in little time produces that system, which attracted the efforts of the researcher to employ neural networks in computing away from the complexities that burden traditional computers. We presented a model for the design of the arithmetic circuit for the process of addition the sign digit numbers in a new way to deal with the arithmetic operations, which employment of the use of neural networks, this model includes a theoretical and practical simulation of them. The model relied on the implementation of the addition process based on a three-step algorithm adopted by the signed systems. Which is characterized by the possibility of execution in a parallel way, and therefore it provides the advantage of completion of arithmetic operation regardless of the length of their operands, or in other words, whatever the number of bits in the operands. The simulation of the model is done by entering operands for 6 addition operations (each one has operands are 15-bit length) to be executed simultaneously.

Improving Architectures of Binary Signed-Digit CORDIC With Generic/Specific Initial Angles

Coordinate rotation digital computer (CORDIC) is widely used in digital signal processing (DSP) to calculate functions. One of the elegant ways to accelerate CORDIC is employment of the redundant binary signed-digit (BSD) number systems, so-called BSD-CORDIC. This paper aims to achieve efficient BSD-CORDIC structures for generic/specific initial angles. First, three generic BSD-CORDIC algorithms are optimized by exploiting a suitable data gating technique as well as appropriate BSD encodings. The synthesis results demonstrate that for generic CORDIC, the proposed BSD-CORDIC schemes enhance the existing ones in terms of speed, power consumption, and area overhead. Second, the look-ahead BSD-CORDIC is proposed as a special case of BSD-CORDIC with specific initial angles. We also show that for the applications like fast Fourier transform (FFT), where the initial angles are known in advance, the proposed look-ahead BSD-CORDIC with the posibit-negabit encoding, as our best presenting structure, noticeably improves speed, power consumption, and area overhead.

Design and implementation of low power and high speed multiplier using quaternary carry look-ahead adder

Need of Digital Signal Processing (DSP) systems which is embedded and portable has been increasing as a result of the speed growth of semiconductor technology. Multiplier is a most crucial part in almost every DSP application. So, the low power, high speed multipliers is needed for high speed DSP. Array multiplier is one of the fast multiplier because it has regular structure and it can be designed very easily. Array multiplier is used for multiplication of unsigned numbers by using full adders and half adders. It depends on the previous computations of partial sum to produce the final output. Hence, delay is more to produce the output. In the previous work, Complementary Metal Oxide Semiconductor (CMOS) Carry Look-ahead Adders (CLA) and CMOS power gating based CLA are used for maximizing the speed of the multiplier and to improve the power dissipation with minimum delay. CMOS logic is based on radix 2(binary) number system. In arithmetic operation, major issue corresponds to carry in binary number system. Higher radix number system like Quaternary Signed Digit (QSD) can be used for performing arithmetic operations without carry. The proposed system designed an array multiplier with Quaternary Signed Digit number system (QSD) based Carry Look-Ahead Adder (CLA) to improve the performance. Generally, the quaternary devices require simpler circuit to process same amount of data than that needed in binary logic devices. Hence the Quaternary logic is applied in the CLA to improve the speed of adder and high throughput. In array multiplier architecture, instead of full adders, carry look-ahead adder based on QSD are used. This facilitates low consumption of power and quick multiplication. Tanner EDA tool is used for simulating the proposed multiplier circuit in 180 nm technology. With respect to area, Power Delay Product (PDP), Average power proposed QSD CLA multiplier is compared with Power gating CLA and CLA multiplier.

Design and Implementation of Fast Booth-2 Multiplier on Artix FPGA

Abstract Now a day’s speed is very important to meet the requirement of user in today’s chips. We want faster smart phones, laptops and other gadgets that can work at a speed even beyond our imagination. In this paper we have designed a fast multiplier which can provide better results. RBSD stands for Redundant Binary Signed Digit number system which enables fast computing by reducing carry propagation time as carry is not propagated to later stages. This number system is signed digit number representation. This RBSD multiplier is implemented using VIVADO 2019.2 version. The multiplier is implemented in VHDL language. Although there is a slight increase in the delay using VIVADO Multiplier, there is a significant decrease in the number of LUT used. We have used artix FPGA[4] with part number xc7a200tisbv484.

Novel Binary Signed-Digit Addition Algorithm for FPGA Implementation

Signed-digit (SD) number representation systems have been studied for high-speed arithmetic. One important property of the SD number system is the possibility of performing addition without long carry chain. However, many numbers of logic elements are required when the number representation system and such an adder are realized on a logic circuit. In this study, we propose a new adder on the binary SD number system. The proposed adder uses more circuit area than the conventional SD adders when those adders are realized on ASIC. However, the proposed adder uses 20% less number of logic elements than the conventional SD adder when those adders are realized on a field-programmable gate array (FPGA) which is made up of 4-input 1-output LUT such as Intel Cyclone IV FPGA.

A Carry-Free Multiplication Implementation Method

Delay caused by carry propagation is an unfavourable issue that much affects the efficiency of numerical computing in computer system. And the more data bits of the operands, the worse the delay. As data bits of the operands in optical computer can be huge because of the high information capability of light, this makes carry delay be very serious. As multiplication is one of the most important and popular calculations and many multiplications can be carried out in parallel by utilizing huge number of data bits of optical computer, study on how to reduce or even mitigate carry delay in multiplication is very important. To improve the multiplication efficiency, a new carry free method to design and implement multiplication based on Ternary Optical Computer (TOC) is put forward. Fully considering the relations between the operands based on modified signed-digit (MSD) number system, a parallel mulitplication implemeation strategy together with its resource allocation method is presented. The experimental results show that the proposed strategy is correct. It exerts the advantages of optical computing and ensures that no carry delay is introduced in the process of multiplication which much improves the efficiency of optical multiplication applications.

Reverse Conversion Schemes for Signed-Digit Number Systems: A Survey

Although signed-digit number systems have received a considerable attention, the transformation of signed-digit numbers back into the conventional forms, known as reverse conversion, is still a performance bottleneck of signed-digit arithmetic. In this paper, a literature survey of reverse conversion schemes for signed-digit number systems is performed on the basis of the articles published from recognized platforms for the past few decades. The survey reveals some specific problems of this field, which need further investigations.

Design of a high-efficient MSD adder

Carry propagation delay is a big obstacle to improve the addition efficiency in computer system. And the more data bits the operands have, the delay is more serious. As data bits of operand in optical computer can be huge this makes carry delay be very serious. How to decrease or even mitigate carry delay in addition is very important to promote optical computer in numerical computing applications. To improve the addition efficiency, a new method to design and implement optical adder is put forward. Fully considering the relations between the addend and augend based on modified signed-digit (MSD) number system operands, division algorithm is presented. It makes the design and implementation of the adder much easy and feasible. Besides, it also guarantees that no carry delay is introduced in the process of addition. Meanwhile, the architecture of the adder, its implementation as well as the auxiliary electronic circuit are also presented. Experimental results show that the architecture and design of the new MSD adder are correct. It can avoid carry propagation and is much efficient for optical addition operation.

Notes on &quotA Novel Conversion Scheme from a Redundant Binary Number to Two's Complement Binary Number for Parallel Architectures&quot proposed by Choo et. al.

In this article, it is shown that although the reverse conversion scheme for binary signed-digit number system proposed by Choo et. al. can not support full parallelism; the rules on which it is based are correct. In this connection, a mathematical induction technique is used to validate the decomposition rules. Accordingly, it can be inferred that the reverse conversion scheme for binary signed-digit number system proposed by Veeramachaneni et. al. works correctly and performs reverse conversion in Ω (log n) time, where, n is the input size. As a consequence, the scheme by Veeramachaneni et. al. need to be considered as a potential contender of the more recent schemes for the same. General Terms Unconventional Number System, Computer Arithmetic Algorithm.

Comments on &quotArea Time Efficient Sign Detection Technique for Binary Signed-Digit Number System&quot proposed by Srikanthan, Lam and Suman

It is shown that the sign detection technique for binary signeddigit number system reported by Srikanthan, Lam and Suman [1] cannot work correctly. The root cause of the problem is detected and some modifications are proposed. The proposed modifications are found to be significant. General Terms Unconventional Number Systems, Algorithm, VLSI

A Common Subexpression Elimination Tree Algorithm

A common subexpression elimination algorithm is proposed to minimize the complexity of the multiple constant multiplication operation. The coefficients (constants) of the multiple constant multiplication are represented using the binary signed digit number system. The binary signed digit representations of each coefficient are enumerated using the representation tree. The algorithm traverses the tree to calculate the possible subexpressions at each node. Each subexpression is used to find a possible decomposition for the coefficient to be encoded. A complexity formula is proposed to compare the decompositions. The algorithm is designed to prune the tree when it finds a decomposition with minimum complexity. This reduces the search space while minimizing the hardware complexity. Results show that the algorithm has better performance than other published algorithms including linear programming optimization methods. The algorithm outperforms the subexpression sharing method in that uses only the canonical signed-digit representations.

Fir Filter Design Using The Signed-Digit Number System and Carry Save Adders – A Comparison

This work looks at optimizing finite impulse response (FIR) filters from an arithmetic perspective. Since the main two arithmetic operations in the convolution equations are addition and multiplication, they are the targets of the optimization. Therefore, considering carry-propagate-free addition techniques should enhance the addition operation of the filter. The signed-digit number system is utilized to speedup addition in the filter. An alternative carry propagate free fast adder, carry-save adder, is also used here to compare its performance to the signed-digit adder. For multiplication, Booth encoding is used to reduce the number of partial products. The two filters are modeled in VHDL, synthesized and place-and-routed. The filters are deployed on a development board to filter digital images. The resultant hardware is analyzed for speed and logic utilization

RESIDUE-WEIGHTED NUMBER CONVERSION FOR MODULI SET {2n-1, 2n + 1, 22n + 1, 2n} USING SIGNED-DIGIT NUMBER

Signed-digit number systems support carry-free, constant time addition. By introducing the signed-digit number arithmetic into a residue number system (RNS), arithmetic operations can be performed efficiently. In this paper, a new algorithm for residue-to-binary conversion for four moduli set {2n-1, 2n + 1, 22n + 1, 2n} that only requires modulo 24n - 1 SD number addition is proposed. This moduli set has 5n-bit dynamic range. Based on the proposed algorithm, the converters are designed with a two-level binary tree structure formed by the modulo 24n - 1 SD number residue adders. Moreover, we simplify the residue adders in converters to obtain more area and time efficiency. The comparison of the converters proposed with the converter using binary arithmetic using 0.18 μm CMOS gate array technology yields reductions in delays of 44%, 60% and 75% for n = 4, n = 8 and n = 16, respectively.

Carry-free vector-matrix multiplication on a dynamically reconfigurable optical platform

Applying the parallelism of optical computing, we present a novel method of vector-matrix multiplication (VMM) based on a new optical computing platform, the ternary optical computer, which can reconfigure any two-input trivalued logic optical processor at runtime, according to the decrease-radix design principle. In this work, we investigate a novel optical VMM (OVMM) using five logic operations with the modified signed-digit (MSD) number system. To simplify the computation process, we realize a carry-free optical addition in three steps, which is independent of the length of the operands. And a new implementation method is proposed that can be used to realize the MSD multiplication in parallel. Based on the generation of partial products in parallel and the binary-addition-tree algorithm, the multiplication can be implemented with the MSD addition. Our initial experiments have been performed to verify the proposed OVMM method. The results show that the proposed method of OVMM is feasible and correct.

Redundant binary partial product generators for compact accumulation in Booth multipliers

The use of signed-digit number systems in arithmetic circuits has the advantage of constant time addition. When signed-digit number systems are used in binary, they are referred as redundant binary. Here, we present a new encoding technique for generating redundant binary partial products for a multiplier, without using any additional hardware. We express each normal binary partial product in one's complement form, with an extra bit denoting the sign bit. The proposed redundant binary partial product generator (RBPPG) achieves the highest reduction in the number of partial products (75%) for a radix-4 multiplier. The carry-free nature of redundant binary adders is exploited to add the extra bits with the partial products, without using any extra adder stages. The new partial product generation (PPG) technique is shown to improve the speed of multipliers, with the least number of adder stages, irrespective of the multiplier size.

MODULO (2p ± 1) MULTIPLIERS USING A THREE-OPERAND MODULAR SIGNED-DIGIT ADDITION ALGORITHM

In this paper, a new three-operand modulo (2p ± 1) addition is implemented by performing a carry-save addition and a two-operand modular addition based on the p-digit radix-two signed-digit (SD) number system. Thus, the delay time of the three-operand modular adder is independent of the word length of the operands. A modulo (2p ± 1) multiplier is constructed as a ternary tree of the three-operand modular SD adders, and the modular multiplication time is proportional to log 3 p. When a serial modular multiplier is constructed using the three-operand modular SD adder, two modular partial products can be added to the sum at the same time. Two kinds of Booth recoding methods are also proposed to reduce the partial products from p to p/2. Therefore, the performance of a parallel modular multiplier can be modified by reducing half of the modular SD adders in the adder tree. For a serial modular multiplication, two partial products are generated from two Booth recoders and added to the sum by using one three-operand modular SD adder, so that the speed of the modular multiplication is three times as fast as the speed without using the three-operand modular SD adder and the Booth recoding method. A very large-scale integration (VLSI) implementation method by VHDL is also discussed. The design and simulation results show that high-speed modular multipliers can be obtained by the algorithms presented.

Area-time efficient sign detection technique for binary signed-digit number system

Computer arithmetic operations based on the BSD (binary signed-digit) number representation system lend themselves well to high-speed computations due to the facilitation of limited carry addition/subtraction. We propose an area-time efficient method for sign detection in a BSD number system based on optimized reverse tree structure. When compared to other popular approaches, such as the most significant carry detection-based CLA (carry look-ahead) and MRC (multilevel reverse carry) implementations, the proposed method is superior to both area and time costs in VLSI. Synthesis results for different word lengths show that the proposed approach to sign detection in the BSD number system continues to maintain its advantage over area and time measures.

A Radix-4 New Svobota-Tung Divider with Constant Timing Complexity for Prescaling

A new floating-point division architecture that complies with the IEEE 754-1985 standard is proposed in this paper. This architecture is based on the New Svoboda-Tung (NST) division algorithm and the radix-4 MROR (maximally redundant maximally recoded) signed digit number system. In NST division, the divisor and dividend must be prescaled. We summarize a general systematic method to accomplish the prescaling, and we also propose a hardware scheme such that the timing complexity is constant regardless of the bit length of the divisor. For the divider implementation, a new MROR signed digit adder with carry free characteristic is proposed for addition and subtraction, and this adder can improve the cycle time significantly. A 32-b/32-b radix-4 divider is thus designed in Verilog HDL; the simulation results show that this architecture is implementable using currently available libraries. The hardware complexity and performance of this divider is competitive with conventional SRT dividers.

A signed binary addition circuit based on an alternative class of addition tables

Redundant signed digit number systems have been used as a basis for the construction of fast arithmetic circuits for several years. In particular, addition circuits with no carry-ripple effects have been developed using signed binary arithmetic systems. This paper presents a general class of signed binary addition tables and provides a framework for constructing various tables. The existence of an entire class of tables provides a circuit designer with an additional degree of freedom while developing addition circuitry. The choice of the exact form of the addition table can be based on the dominant desired characteristics of the resultant circuit. An example of a circuit derived for area minimization is presented and compared to another signed binary addition circuit that was previously published. Both circuits were optimized and mapped to 20 different CMOS cell libraries. The experimental results indicate an average decrease in area of 26% and an average decrease in dynamic power consumption of 29% with an average increase in delay of only 4.4%.

High-performance compensation technique for the radix-4 CORDIC algorithm

Although the full radix-4 CORDIC algorithm is efficient compared to the standard radix-2 version, the scale-factor overhead causes its improvement to be limited. In this work, an algorithm and its associated architecture have been proposed for parallel compensation of the scale factor for the radix-4 CORDIC algorithm in the rotation mode. The proposed method, which makes no prior assumptions about the elementary angles of rotation, reduces the latency from n to (n/2)+3, where n is the precision length in bits, at the cost of a reasonable increase in hardware complexity. The architecture presented relates to the redundant signed-digit number system. The architecture has been modelled in VHDL and simulated to establish its functional validity.