SiGe Bipolar CMOS Research Articles

Resolution-Related Design Considerations for a 120-GS/s 8-bit 2:1 Analog Multiplexer in SiGe-BiCMOS Technology

This article presents a 120-GS/s 2:1 8-bit analog multiplexer (AMUX) in SiGe-Bipolar CMOS (BiCMOS) technology that exhibits the highest effective resolution reported for an AMUX in any kind of semiconductor technology. This article presents the design considerations that have led to this high resolution. In particular, it contains a discussion on the choice of an AMUX circuit concept to support high linearity. A frequency-domain explanatory model for the signal contribution to the effective number of bits (ENoB) in the presence of mismatch errors is presented and applied to the analysis of timing and signal gain mismatch in the AMUX setup. Typical ENoB versus frequency characteristics were identified and utilized to speed up ENoB simulations and to develop calibration procedures for the different mismatch types in the AMUX setup. The results of the analysis and the performance of the AMUX in the calibrated setup were proven by measurement results.

A 210–291-GHz (8×) Frequency Multiplier Chain With Low Power Consumption in 0.13-μm SiGe

This letter presents a 210–291-GHz $8\times $ multiplier chain in the 0.13- $\mu \text{m}$ SiGe Bipolar CMOS (BiCMOS) technology for the broadband generation of carrier signals, imaging, and spectroscopy. It consists of three cascaded Gilbert-cell doublers with compact input matching networks to generate quadrature collector currents in the switching quad for broadband flat conversion gain. The multiplier chain generates a saturated output power of −7.7 dBm at 244.5 GHz with a 3-dB bandwidth of 81 GHz. It consumes 0.24 W of dc power and occupies 0.86 mm 2 of chip area.

A 60-GHz SiGe Radiometer Calibration Switch Utilizing a Coupled Avalanche Noise Source

This letter presents a novel implementation of a ${V}$ -band single-pole double-throw switch that facilitates the internal calibration of radiometers by integrating an ambient noise source and an avalanche noise source. The switch is implemented in a 0.13- $\mu \text{m}$ SiGe bipolar-CMOS (BiCMOS) process and uses a shunt topology with $\lambda $ /4 directional couplers that inject noise from the avalanche source. The avalanche source is implemented using the collector-base junction of a SiGe heterojunction bipolar transistor (HBT) and attains a measured excess noise ratio of 18.7 dB at 60 GHz. The switch achieves a midband insertion loss of 2.0 dB and an isolation of 22 dB at 60 GHz. An excess input-referred noise temperature of 620 K is added with the noise source ON. To the best of our knowledge, this is the first avalanche noise source using a diode-configured SiGe HBT and the first monolithic two-reference switch for calibrating millimeter-wave radiometers.

III-V-on-Silicon Photonic Transceivers for Radio-Over-Fiber Links

The emergence of the fifth generation wireless networks (5G) and the Internet of Things drives the research on radio access networks. Future wireless networks aim to deliver a dramatic increase in bandwidth to an ever increasing amount of connected devices. To realize such a vision, advanced optical transceivers that link the base-station and the antennas will be required. In this paper, we present the first demonstration of an integrated silicon photonic radio-over-fiber transmitter and receiver, consisting of a directly modulated III-V-on-silicon distributed feedback laser and a Ge-on-Si waveguide photodiode cointegrated with a linear SiGe Bipolar CMOS (BiCMOS) transimpedance amplifier, respectively. Transmission of a high-spectral-efficiency long-term evolution 20 MHz bandwidth 120 Mbit/s 64 quadrature amplitude modulation (64-QAM) orthogonal frequency division multiplexing signal on a 3.5 and 5 GHz carrier over 5 km of standard single mode fiber is demonstrated. We further demonstrate the transmission of 16 Gbps 16-QAM data on a 20 GHz carrier over a 5 km link with a received rms error vector magnitude of 7%.

Complementary current reuse quadrature voltage‐controlled oscillators

This study describes the design and operation principle of quadrature voltage-controlled oscillator (QVCO) with complementary current-reuse (CR) voltage-controlled oscillators (VCOs). One CR complementary metal-oxide semiconductor (CMOS) VCO consists of a pair of p-type metal-oxide semiconductor field-effect transistors (pMOSFETs) and n-type metal-oxide semiconductor field-effect transistors (nMOSFETs), and an inductor. The other CR VCO consists of a pair of pMOSFET and heterojunction bipolar transistors (HBTs), and one inductor. The two CR VCOs are used to construct differential VCOs, which are subsequently used to build QVCOs coupled via coupling networks. The Bipolar-CMOS (BiCMOS) VCO and QVCO have been implemented with the Taiwan Semiconductor Manufacturing Company, Limited (TSMC) 0.18 μm SiGe BiCMOS technology. The CMOS QVCOs have been implemented with the TSMC 0.18 μm CMOS process. The quadrature phase generation and oscillation frequency equations are derived based on the block diagram of QVCO circuit.

Microstrip slow‐wave line for phase shifting cells

The design, simulation and measurements of microstrip slow-wave lines implemented in a 0.25 µm SiGe bipolar CMOS (BiCMOS) process is addressed for Ku-band (10–15 GHz) applications. The simulation results and the measurements show better performances for the proposed microstrip slow-wave line compared with the classical microstrip transmission line. These lines present very low insertion losses and a high phase constant.

무선 중계기용 저전력, 고선형 Up-down Converter

Abstract – We have designed and fabricated a low power and high linearity up down convertor for wireless repeaters using 0.35 ㎛ SiGe Bipolar CMOS technology. Repeater is composed of a wideband up/down converting mixer, programmable gain amplifiers (PGA), input buffer, LO buffer, filter driver amplifier and integer-N phase locked loop (PLL). As of the measurement results, OIP3 of the down conversion mixer and up conversion mixer are 32 dBm and 17.8 dBm, respectively. The total dynamic gain range is 31 dB with 1 dB gain step resolution. The adjacent channel leakage ratio (ACLR) is 59.9 dBc. The total power consumption is 240 mA at 3.3 VKey Words : Repeater, PLL, High linearity, ACLR†Corresponding Author : School of Electrical and Electronics Engineering, Chung-Ang University, Korea.E-mail: ychoi@cau.ac.kr* School of Electrical and Electronics Engineering, Chung-AngUniversity, Korea.** EPIC Solution Co., LTd., Korea. Received : December 09, 2014; Accepted : February 26, 2015

An X-Band Slow-Wave T/R Switch in 0.25-$\mu\hbox{m}$ SiGe BiCMOS

This brief presents a fully integrated X-band transmit/receive (T/R) switch using slow-wave transmission lines for X-band phased-array radar applications. The T/R switch was fabricated in a 0.25- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$\mu\hbox{m}$</tex></formula> SiGe bipolar CMOS (BiCMOS) process and occupies 0.73- <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$\hbox{mm}^{2}$</tex></formula> chip area, excluding pads. The switch is based on shunt–shunt topology and employs isolated n-channel (NMOS) transistors and slow-wave microstrip lines. Additionally, resistive body floating and dc biasing are employed to improve the power-handling capability <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$({P}_{1\, {\rm dB}})$</tex></formula> of the switch. The T/R switch resulted in a measured insertion loss of 2.1–2.9 dB and isolation of 39–42 dB from 8 to 12 GHz. The input referred <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">${P}_{1\, {\rm dB}}$</tex></formula> is 27.6 dBm at 10 GHz. To our knowledge, this brief presents the utilization of slow-wave transmission lines in T/R switches for the first time. Furthermore, it can simultaneously satisfy stringent isolation, insertion loss, and power-handling capability requirements for implementing a fully integrated SiGe T/R module.

Analysis of totem-pole drivers in SiGe for RF and wideband applications

This paper presents an analysis of totem-pole (TP) stages for driver applications and summarizes the major design constraints for an optimization with respect to P1dB, OIP3, and bandwidth. It is shown, that for matched drivers, in contrast to the widely applied common collector (CC) stage, class-AB TP stages offer higher output power and much higher power-added efficiencies (PAE) at comparable bandwidth. A combiner chip in 0.25 μm SiGe Bipolar CMOS (BiCMOS) verifying this concept in hardware as output driver is demonstrated proofing the increased achievable output power, which was measured greater than +0.1 dBm. This is approximately 11 dB higher than for a conventional CC driver. Furthermore, a concept is proposed, where the TP stage can act as a broadband matched driver for differential or balun operation ranging down to DC. As verification a broadband driver design using a class-AB TP stage is presented, which has a 3 dB bandwidth of 7.9 GHz and delivers up to +4.3 dBm into a 50 Ω load, which is 17 dB higher than its CC counterpart. At this output power it consumes a DC power of 12.3 mW and yields a PAE of 16.1%.

An Experimental Study on High-Frequency Substrate Noise Isolation in BiCMOS Technology

In this letter, four substrate noise isolation structures in standard 0.18-mum SiGe bipolar CMOS technology were investigated using S-parameter measurements. The experimental and simulated results on different isolation structures, such as triple-well p-n junction isolated walls, deep trench isolation, and double P+ guard-ring structures, are presented. Each element in the equivalent circuits has been calculated or fitted based on the parasitic resistance, capacitance, and physical dimensions using the device simulator MEDICI and the measured results of the test patterns. The proposed structure B significantly reduced substrate noise below -70 dB up to 20 GHz. The proposed structure C with an extra triple-well junction achieved the best isolation at the lower frequency range, in which |S21| was less than -71 dB from 50 MHz to 10.05 GHz, and -56 dB from 10.05 to 20.05 GHz. The measured results showed an excellent agreement with the calculations. Structure B is good enough and is recommended for a general-purpose RF circuit design, whereas structure C can be used in a highly sensitive RF circuit block below 10 GHz.