SiGe BiCMOS Process Research Articles

Design and analysis of a feedback time difference amplifier with linear and programmable gain

This paper proposes a feedback time difference amplifier (FTDA) that achieves linear, controllable gain and changeable input range for different time difference gains. The proposed FTDA consists of two identical feedback output generators. The feedback output generator achieves a linear input–output transfer characteristic by employing two p-type keepers for time gain feedback control. Its validity was demonstrated using $${0.13}\, {\upmu \hbox {m}}$$ SiGe BiCMOS process. The power consumption is $$91.54 \,{\upmu \hbox {W}}$$ for the highest gain with input signals at $${2}\,\hbox {MHz}$$ . The gain can be controlled from 25.06 to $$734.9\,{\hbox {s/s}}$$ within $$40 \,\hbox {ps}$$ input time interval.

67‐90 GHz broadband power detector with 3 GHz output bandwidth for on‐chip test of millimeter‐wave circuits

SummaryThis paper presents the design of a compact and wide bandwidth millimeter‐wave power detector, integrated at the output of an E‐band power amplifier and implemented in a 55‐nm SiGe BiCMOS process. It is based on a nonlinear PMOS detector core, and its measured output voltage tracks the output power of the PA from 67 to 90 GHz. It provides an insertion loss lower than 0.2 dB, and its responsivity can be tuned between 8 and 17 V/W. The output bandwidth is bigger than 3 GHz, which allows built‐in self‐test when transmitting multigigabit millimeter‐wave signals.

A Passive Tunable Matching Filter for Multiband RF Applications Demonstrated at 7 to 14 GHz

This letter presents a general approach to implement a wideband tunable matching filter for multiband radio-frequency applications. The concept is demonstrated for a two-stage bipolar amplifier to achieve a tunable input and output small-signal match to 50 ${\Omega }$ . The filters are realized as $\pi $ -networks with two fixed inductors and a 4-bit digitally tuned capacitor based on CMOS switches. The utilized technology is a 130-nm SiGe BiCMOS process. A total frequency tuning range of 7–14 GHz with at least 8-dB return loss and 16.5–20 dB gain is confirmed by measurements and aligns well with the theoretical predictions and simulation results. In addition, a compact analytic theory for the proposed network is derived to extend this approach to arbitrary frequencies and bandwidths.

Low‐power three‐path inductor class‐C VCO without any dynamic bias circuit

A 2.48 GHz class-C voltage controlled oscillator (VCO) without any dynamic back bias circuit is presented. The VCO uses three-path high Q-factor inductor as the low loss resonator and class-C cross-coupled nMOSFET pairs for high dc/RF conversion efficiency and direct cross-coupled pMOSFET for dc current reuse. At the supply voltage of 1.2 V, the core power consumption is 0.24 mW. The phase noise of the VCO is −124 dBc/Hz and the VCO figure of merit is −197.0 dBc/Hz. The VCO was implemented in the TSMC standard 0.18 μm SiGe BiCMOS process and occupies a die area of 0.799 × 0.809 mm2.

A 60-GHz Coplanar Waveguide-Based Bidirectional LNA in SiGe BiCMOS

A bidirectional low-noise amplifier (LNA) is presented in this letter. By using transistor bias control and low-loss coplanar waveguide structures with defected ground shield as both interconnect traces and distributed passives, the proposed two-port bidirectional amplifier achieves a measured performance close to the stand-alone LNA from 54 to 65 GHz. The design is fabricated in a 0.18- $\mu \text{m}$ SiGe BiCMOS process consuming a maximum 10.6-mA current from a 1.8-V supply voltage and occupies a 0.85-mm2 core die area.

A Millimeter-Wave CMOS Dual-Bandpass T/R Switch With Dual-Band LC Network

Fully integrated 24/60-GHz concurrent dual-bandpass transmit/receive (T/R) switch in 0.18- $\mu \text{m}$ SiGe BiCMOS process is presented. The developed T/R switch consists of dual-band LC networks and resonators with shunt nMOS transistors performing the switching function. In the receiving (RX) mode, the measured insertion losses (ILs) and isolations (ISOs) are 4.5 and 16 dB at 24 GHz, and 5 and 18.3 dB at 60 GHz, respectively. The ILs and ISOs for the transmitting (TX) mode are 6.7 and 18.2 dB at 24 GHz, and 8.5 and 20.8 dB at 60 GHz, respectively. The measured peak stopband rejections are 61.5 and 65.5 dB for the RX and TX modes, respectively. With single-tone 24 or 60 GHz input, the measured input 1-dB compression point ( $P_{{{1~\text {dB}}}})$ is 23.3 or 18.4 dBm at 24 or 60 GHz, respectively. For concurrent dual-tone 24/60-GHz input, the measured inputs $P_{{{1~\text {dB}}}}$ are 19 and 16.8 dBm at 24 and 60 GHz, respectively. The measured input third-order intercept points are 31.5 and 27.9 dBm at 24 and 60 GHz, respectively.

High Input Impedance Cryogenic RF Amplifier for Series Nanowire Detector

We designed a high input impedance cryogenic radio frequency amplifier to scale up a series array of superconducting nanowire single photon detectors for resolving a wide range of photon numbers. The monolithic integrated chip was fabricated by Tower Jazz's 0.18-μm SiGe BiCMOS process. Temperature dependence of the main components, such as silicon germanium heterojunction bipolar transistor, proportional current source, and poly resistor, were characterized to estimate the quiescent point of the amplifier at cryogenic environment. At 4.2 K, a cryogenic amplifier with 6-kΩ input impedance, 20-dB gain, 4 MHz to 1-GHz bandwidth, and 0.9-mW power dissipation was obtained.

A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

High-Speed SiGe BiCMOS Technologies and Circuits

This work reports on the development of SiGe-BiCMOS technologies for mm-wave and THz high frequency applications. We present state-of-the-art performances for different SiGe heterojunction bipolar transistor (SiGe-HBT) developments as well as the evolution of complex BiCMOS technologies. With respect to different technology generations of high-speed SiGe-BiCMOS processes at IHP we discuss selected device modifications of the SiGe-HBT to achieve high frequency performances of a complex BiCMOS technology towards the 0.5 THz regime. We show the difference of high-frequency performance difference with respect to maximum achievable transit frequencies fT and oscillation frequencies fmax in comparison to RF-CMOS technologies and depict the required increase of additional process effort for the HBT-module integration for a 0.5 THz SiGe-BiCMOS technology. Moreover different high speed circuits are presented like broadband ICs for optical communication, high frequency circuits for wireless communication at 60 and 240 GHz, mm-wave radar circuits at 60 and 120 GHz as well as THz circuits operating at 245 GHz and 500 GHz for spectroscopic applications. All reviewed circuit examples are based on the discussed 130nm-SiGe-BiCMOS technologies and show their potential for a broad range of high-speed applications.

Watt-Level mm-Wave Power Amplification With Dynamic Load Modulation in a SiGe HBT Digital Power Amplifier

Performance limits and design techniques for Watt-level power amplification at millimeter-wave (mm-wave) frequencies using silicon germanium (SiGe) HBT Class-E power amplifiers (PAs) is presented in this paper. A Class-E power modulator architecture is proposed for demonstrating highspeed data transmission using ASK modulation at mm-wave frequencies. Several of these 1-b power modulators are power combined to realize a Watt-level digital PA with several levels of output amplitude at mm-wave frequencies. A dynamic load modulation concept is proposed to mitigate the effect of load pulling in the digital PA at power back-off. A tunable transmission line architecture with variable characteristic impedance is proposed to realize this dynamic load modulation network and enable efficiency enhancement at power back-off levels in the Watt-level digital PA. Watt-level power generation at mm-waves was demonstrated in a eight-way combined digital PA with dynamic load modulation, fabricated in a 0.13-μm SiGe BiCMOS process with ≈29 dBm (0.8 W) measured output power at 46 GHz, 18.4% peak power-added-efficiency, and 60% of the peak efficiency at 6-dB power back-off.

An X-band Schottky diode mixer in SiGe technology with tunable Marchand balun

In this paper, we propose a double balanced mixer with a tunable Marchand balun. The circuit is designed in a SiGe BiCMOS process using Schottky diodes. The tunability of the Marchand balun is used to enhance critical parameters for double balanced mixers. The local oscillator-IF isolation can be changed from –51 to –60.5 dB by tuning. Similarly, the IIP2can be improved from 41.3 to 48.7 dBm at 11 GHz, while the input referred 1-dB compression point is kept constant at 8 dBm. The tuning have no influence on conversion loss, which remains at 8.8 dB at a LO power level of 11 dBm at the center frequency of 11 GHz. The mixer has a 3 dB bandwidth from 8 to 13 GHz, covering the entire X-band. The full mixer has a size of 2050 μm × 1000 μm.

Supply-Scaling for Efficiency Enhancement in Distributed Power Amplifiers

Distributed amplifiers (DAs) feature large bandwidth but relatively low gain and power efficiency. This paper presents a supply-scaling technique to improve the efficiency of a mm-wave DA while maintaining a broadband $50\Omega $ match. An analysis of interstage load modulation and the effects of shunt dc-feed inductors on distributed operation is provided. A single-ended, eight-stage DA is designed in a 90 nm SiGe BiCMOS process. The fabricated amplifier has a gain of 12 dB over a 3 dB bandwidth from 14-105 GHz. The measured peak output power is 17 dBm with a peak power-added efficiency (PAE) of 12.6% at 50 GHz and 3 dB power bandwidth greater than 70 GHz. The DA occupies an area of 2.65 mm × 0.57 mm, and total dc power consumed from four scaling voltage supplies is 297 mW.

Ultra-Wideband Active Balun Topology and Its Implementation on SiGe BiCMOS Across DC-50 GHz

A new type of active baluns consisting of a common emitter (CE) amplifier with degenerative inductor and a common collector (CC) amplifier is proposed, analyzed and demonstrated using a 0.18- $\mu\text{m}$ SiGe BiCMOS process. The parasitic neutralization and compensation techniques are used to keep the balun well balanced at very high frequencies and across an ultra-wide bandwidth. The active balun is particularly not affected by any components connected at its input or output ports, making it very attractive for integrating with other components and for system integration. The designed 0.18- $\mu\text{m}$ SiGe BiCMOS active balun exhibits an amplitude imbalance lower than 1 dB and phase imbalance lower than 100 from dc to 50 GHz, and consumes a low dc power of only 14.4 mW from a dc power supply voltage of 1.8 V.

Tuning of the Relative Phases of a Rotary Travelling Wave Oscillator

This letter describes the implementation and performance of a phase detector and algorithm combination used to tune the relative phases of an 18-GHz RTWO. Symmetrical XOR phase detectors are designed (20 GHz simulated operation), fabricated in a SiGe BiCMOS process and tested to resolve approximately 4 mV/° from 35° to 55° and approximately 5 mV/° from 80° to 100° at 12 GHz. Instances of this phase detector are used to measure the phase of nominal 45° differential transmission line sections of an 18-GHz RTWO. The phase alignment algorithm mitigates differences between these measurements by iteratively adjusting varactors placed differentially across the RTWO transmission line sections.

Monolithic Low-Power 6-Gb/s Optical Transmitter for a Silicon HBT-Based Carrier Injection Electroabsorption Modulator

Photonic devices monolithically integrated with nanoscale electronic signal processing circuitry in silicon are emerging as a disruptive technology to reduce cost and improve optical system integration and performance. Silicon heterojunction bipolar transistor (HBT)-based carrier injection electroabsorption modulators (EAMs) implemented in a commercial silicon process have several merits, including high speed, low power, low driving voltage, small footprint, and high modulation efficiency. A low-power high-speed optical transmitter driver module has been realized in a 130-nm SiGe BiCMOS process for an HBT-based carrier-injection-type modulator. The transmitter consists of a monolithic $2^{7}-1$ pseudorandom bit sequence generator and a driver circuit with digitally tuned preemphasis strength. With 1.5-V power supply, the transmitter circuit consumes 44.5 mW at an operating speed of 6 Gb/s.

Phase error reduction of a digitally controlled phase shifter utilizing a variable phase and gain amplifier

This paper presents a variable phase and gain amplifier (VPGA), featured in a 4-bit digitally controlled phase shifter, that enables significant phase error reduction. The functionality of the VPGA is demonstrated by utilizing it between the third and fourth bits of a digitally controlled phase shifter. The first three bits are implemented using distributed active switches based on HBTs and the fourth bit is realized in a final amplification stage based on switching between common-base (CB) and common-emitter (CE) topologies. By the use of the VPGA, RMS phase error is reduced from 22° to 11° with the cost of reduced gain (0.1–2.5dB) and increased RMS gain error (1.0–2.2dB). A total of 360° phase shift is achieved in 4bit resolution with an RMS phase error of 0.1° at 10.5GHz, and a maximum 11° phase error in 4.5GHz bandwidth. The chip area is 2.150mm×1.040mm including pads, and the VPGA consumes only 0.32mm×0.410mm area. The chip is implemented in a 0.25-µm SiGe BiCMOS process. These performance parameters are attributed to the adjustment method by the VPGA applied in this work, which enables superior performance than the-state-of-the-art utilizing similar technologies.

A Fully Differential Ultra-Compact Broadband Transformer-Based Wilkinson Power Divider

This letter presents a fully differential and integrated transformer-based Wilkinson power divider with a broad bandwidth, low loss, high isolation, and an ultra-compact form factor. Two differential transformers connected in parallel serve as the impedance transforming and power combining network in the proposed Wilkinson power divider. Shunt capacitors are added between the output ports for matching and isolation enhancement. A proof-of-concept transformer-based Wilkinson power divider is designed at 60 GHz and implemented in a standard 130 nm SiGe BiCMOS process with the core chip area of $270 \mu\text{m} \times 107 \mu\text{m}$ and the simulated 1 dB-magnitude fractional bandwidth of 64% at the 60 GHz center frequency. Measurement results of 4 independent samples demonstrate the passive loss of 1.32 dB at 62 GHz with standard deviation of 0.1 dB and the peak isolation of 28 dB at 65 GHz with magnitude and phase imbalance within 0.2 dB and 5 $^{\circ}$ , respectively.

A High-Gain Power-Efficient Wideband V-Band LNA in 0.18- SiGe BiCMOS

This paper presents a high-gain power-efficient wideband V-band low noise amplifier (LNA) realized in 0.18- $\mu\text{m}$ SiGe BiCMOS process. An effective wideband gain shaping method with gain enhancement under low power consumption is employed, where the 1st and 2nd inter-stage matching (ISM) network are designed for better conjugate matching around the lower and upper 3 dB cutoff frequency ends, respectively, without giving up the gains at the opposite frequency ends for each ISM network. The developed LNA achieves the peak measured gain of 32.5 dB at 61 GHz and over 29.5 dB gain across the 3 dB bandwidth from 43 to 67 GHz while consuming only 11.7 mW at 1.8 V supply voltage. The measured average noise figure and group delay variation are 6 dB and less than 28.3 ps over the entire bandwidth, respectively.

Wideband high-isolation SPDT RF switch in 0.18- $$\upmu$$ μ m SiGe BiCMOS technology

A single pole double throw (SPDT) RF switch working in wide band is presented. The SPDT RF switch composed of many single pole single throw (SPST) switches changes the signal flow corresponding to control signals. It is very important to obtain low insertion loss and high power driving capability for dealing with the input signal of wide dynamic range. High isolation is also desirable for suppressing leakage of unwanted signal going through the off-state path. To achieve low insertion loss, the heterojunction bipolar transistor (HBT) along with MOSFET in SiGe BiCMOS process is employed. HBT shows inherently considerably high impedance between collector and emitter terminals when it turns off, so that RF signals leak less through the off-state path. The insertion loss of the proposed SPDT RF switch is maintained less than 2 dB over frequency range of interest. This RF switch cancels leakage signals coming out of the off-state paths, leading to isolation improvement. For leakage cancellation, transformer and common-base structure are employed. In addition, SPST switches are adopted in parallel with inductors for decreasing the phase deviation of the passing signal. Since the RF switch using MOSFET shows worse isolation as frequency increases, leakage signal cancellation is designed to work in higher frequency region for obtaining wideband operation. A high isolation is obtained over 23 dB in measurement. This RF switch operates from 1 to 8 GHz providing low insertion loss. In this design, 0.18-$$\upmu$$μm SiGe BiCMOS process is used and the proposed RF switch occupies the area of 0.3 mm$$^{2}$$2.

Effect of lateral structure parameters of SiGe HBTs on synthesized active inductors**Project supported by the Natural Science Foundation of Beijing, China (Grant Nos. 4142007 and 4122014), the National Natural Science Foundation of China (Grant No. 61574010), and the Higher Educational Science and Technology Program of Shandong Province, China (Grant No. J13LN09).

The effect of lateral structure parameters of transistors including emitter width, emitter length, and emitter stripe number on the performance parameters of the active inductor (AI), such as the effective inductance Ls, quality factor Q, and self-resonant frequency ω0 is analyzed based on 0.35-μm SiGe BiCMOS process. The simulation results show that for AI operated under fixed current density JC, the HBT lateral structure parameters have significant effect on Ls but little influence on Q and ω0, and the larger Ls can be realized by the narrow, short emitter stripe and few emitter stripes of SiGe HBTs. On the other hand, for AI with fixed HBT size, smaller JC is beneficial for AI to obtain larger Ls, but with a cost of smaller Q and ω0. In addition, under the fixed collector current IC, the larger the size of HBT is, the larger Ls becomes, but the smaller Q and ω0 become. The obtained results provide a reference for selecting geometry of transistors and operational condition in the design of active inductors.