Sidewalls Of Structures Research Articles

Silicon nanowire oxidation: the influence of sidewall structure and gold distribution

The oxidation behavior of Si nanowires (SiNWs) grown by the gold (Au) catalyzedvapor–liquid–solid (VLS) growth process in an electron beam evaporation (EBE)reactor is studied. The VLS SiNWs exhibit hexagonal shape with essentially{112} facets where each facet shows a saw-tooth faceting itself, consisting ofalternating {111} and {113} facets. Depending on growth temperatures (450–750 °C) and evaporation currents (40–80 mA) that determine the silicon vapor supply,this facet formation is more or less pronounced. The diffusion of Au atoms onthe faceted SiNW surfaces and the formation of Au nanoparticles on the SiNWfacets during growth and during ex situ annealing are studied. Upon diffusion,the Au atoms agglomerate and form Au nanoparticles that preferably arrangethemselves on {113} facets. Upon annealing in air at temperatures between800 and950 °C the gold nanoparticles agglomerate further and form bigger particles of a fewtens of nm in diameter that reside at the interface between the growing silica (SiO2) layer and the SiNW itself, which in turn shrinks during SiNW oxidation. The oxide layerthickness and the oxide appearance depend on the annealing conditions (time andtemperature) and systematically varied oxidation processing is described in this paper asinvestigated by cross-sectional transmission electron microscopy (TEM) including highresolution studies as well as scanning electron microscopy (SEM) studies. Our resultsstrongly suggest that the SiNWs can be fully oxidized, thus forming silica NWs thatcan either keep their initial shape or, under certain annealing conditions, do notkeep their initial wire shape but assume a bamboo-like shape that forms mostlikely as a result of locally high stresses that are related to nanocrack formation.The nanocracks form in the growing oxide layer mediated by the presence of Aunanoparticles that yield gold-enhanced SiNW oxidation and thus a faster oxidation rate.

A Modal-Based Derivation of Transient Pressure Distribution Along the Tyre-Road Contact

The two-dimensional, frictional tyre-road contact interaction is investigated. A transient contact algorithm is developed, consisting of an analytical belt model, a non linear sidewall structure and a discretized viscoelastic tread foundation. The relationship between the magnitude/shape of the predicted two-dimensional pressure distribution and the corresponding belt deformation is identified. The effect of vertical load and the role of sidewall non linearity are highlighted. The modal expansion/reduction method is proposed for the increase of the computational efficiency and the effect of the degree of reduction on the simulation accuracy is presented. The qualitative results are physically explained through the participation of certain modes in the equilibrium solution, offering directions for the application of the modal reduction method in shear force oriented tyre models.

Design and Optimization of Gate Sidewall Spacers to Achieve 45 nm Ground Rule for High-Performance Applications

In this paper, we describe our triple sidewall spacer scheme to achieve 45 nm ground rule for high-performance applications. This triple sidewall spacer scheme uses three kinds of sidewall spacers, in which the first sidewall is used for the source/drain extension implantation offset (SW1), the second is for the p-channel field effect transistor (PFET) embedded silicon germanium offset (SW2), and the third spacer is for the deep source/drain implantation offset (SW3). We also evaluated the impact of sidewall spacer materials and structures on device characteristics. After optimizing each sidewall spacer material and structure including offset width, we successfully demonstrated identical device characteristics with the minimum poly-pitch layout while minimizing layout dependence. This sidewall spacer scheme has the capability to achieve the 45 nm ground rule, and our sidewall spacer design is mature and suitable for 45-nm-node high-performance applications.

InGaN-Based Light-Emitting Diodes with a Cone-Shaped Sidewall Structure Fabricated Through a Crystallographic Wet Etching Process

The InGaN-based light-emitting diodes (LEDs) were fabricated through a crystallographic etching process to increase their light extraction efficiency. After the laser scribing and the selective lateral wet etching processes at the LED chip edge region, the stable crystallographic etching planes were formed as the GaN {1012} planes and had an including angle with the top GaN (0001) plane measured as 40.3°. The AlN buffer layer acted as the sacrificial layer for the lateral wet process with a 27.5 μm/h etching rate. The continuous cone-shaped sidewall (CSS) structure of the treated LED has a larger light-scattering area and higher light extraction cones around the LED chips. The LED with the CSS structure around the chip edge region has a higher light output power compared to a conventional LED when measured in LED chip form.

Effect of ZnO catalyst on carbon nanotube growth by thermal chemical vapor deposition

In this study, carbon nanotubes (CNTs) were synthesized on a catalyst of ZnO nanorods using thermal chemical vapor deposition. ZnO nanorods were coated on silicon substrates by a hydrothermal process. The CNT growth temperature was maintained at 900°C at an ambient pressure. Methane and argon gases are used for the CNT synthesis. In this work, scanning electron microscopy (SEM) and transmission electron microscopy images were used to observe the surface morphology and sidewall structure, energy-dispersive spectrometry (EDS) was used to identify and analyze the chemical composition of the surface of the CNTs, and Raman spectroscopy was employed to investigate the CNT structures. The research reveals that the carbon nanotubes grown on ZNO nanorods show a multiwalled structure with defective graphite sheets on the walls. The SEM images show that the surface of CNTs grown on the ZnO nanorod catalyst were covered by the nanonode carbon nanoparticles. Raman spectra show that the appearance of the relatively str...

Enhanced Light Extraction Efficiency in InGaN Light-Emitting Diodes Through Photoelectrochemical Sidewall Shaping Process

The cone-shaped-sidewall InGaN-based light-emitting diodes (LEDs) with higher light extraction efficiency were fabricated through the photoelectrochemical (PEC) process. The process procedures were consisted with the PEC selective wet oxidation on n-type GaN without p-type GaN layer, removing Ga2O3 layer, crystallographic wet etching process, and forming cone-shaped sidewall structure. The stable crystallographic etching planes were formed as the p-type GaN { } planes and n-type GaN { } planes with a 27{degree sign} included angle. The InGaN/GaN multi-quantum-well (MQW) layers were located at the cone's tip nano-structure in mesa-edge region, and the micro-photoluminescence spectrums had the blue shift phenomenon from 457.8nm to 450.8nm caused by the quantum confinement effect and particle compress strain released.

Fabrication of a polymeric tapered HARMs array utilizing a low-cost nickel electroplated mold insert

A simple low-cost technique has been developed to fabricate a mold insert for replicating polymeric tapered high aspect ratio microstructures. A backside exposure technique is used to first obtain a tapered sidewall structure as an electroplating mold in SU-8 photoresist on a glass wafer. Nickel electroplating is utilized to form the mold insert. The lowest average surface roughness of the nickel mold insert on the side that interfaces with the glass wafer during electroplating is measured to be 7.02 nm. A novel technique involving use of titanium putty is introduced here to reduce cost and effort required to fabricate the mold insert. Replication of tapered microstructures in polymeric materials utilizing the fabricated mold insert is demonstrated here in polydimethylsiloxane by a direct molding process and in polymethyl methacrylate by hot embossing. The fabrication details for the mold insert are described. Advantages and disadvantages of the use of titanium putty for achieving superior metal surface finish are given.

Nanoscale Multi-Line Patterning Using Sidewall Structure

A patterning technique to define nanoscale multiple lines is developed and optimized using sidewall structure. About 50 nm poly-Si multiple lines, which have 70 nm as one of the narrowest space, are defined by sidewall multi-line patterning technique. These patterns have a good uniformity (deviation 1.5–4.7 nm). In addition, we can control line/space of patterns very easily by sidewall width control in this technique. And this is free from the proximity effect because of the process using sidewall hard mask. So, it is expected that the sidewall multi-line patterning technique can be applied to fabricate single electron devices, quantum devices, and other nanoscale devices.

Divergent channel flow of a liquid crystalline polymer solution

The flow of a `model' lyotropic liquid crystal polymer, (hydroxypropyl)cellulose in water, through a rectangular channel with a divergence in the channel width, is studied by in situ light microscopy. Microscopic texture observations are related to measurements of the flow velocity field, in order to characterize the shear and elongational aspects of the flow and to examine the effects of the divergence from a narrow channel to a wide channel. A strong dependence of flow-induced texture on position in the channel is observed and is related to the interplay of shear and elongational strain. The divergence generates both a perpendicular elongational strain due to the widening of the channel, and subsequently an elongational strain along the flow direction due to the change in flow pattern from quasi-radial to unidirectional down the wide channel. Additionally side wall structure is observed to be more complex than a simple strong alignment, displaying a fine birefringent texture. Finally there is a marked dependence of the macroscopic structure on the strain history of the fluid prior to entry into the channel, indicating that very different structures of, for instance, moulded parts, can result from differences in geometry and fluid treatment prior to entry into the mould itself.

Facet‐Free Selective Silicon Epitaxy by Reduced‐Pressure Chemical Vapor Deposition Process Evaluation and Impact on Shallow Trench Isolation

A facet‐free, selective epitaxy process has been identified using the chemistry in single‐wafer reduced‐pressure chemical vapor deposition. The process window has been explored with respect to shallow trench isolation, simultaneous polycrystalline silicon (polysilicon) deposition, facet formation, and electrical parameters of polysilicon sheet resistance and junction leakage current. The isolation structure can be severely degraded by aggressive pre‐epitaxy bakes through volatile SiO formation; however, the impact is minimized when the prebake is limited to 900°C, 60 s. Concurrent deposition of polysilicon and silicon epitaxy can result in significantly different deposition rates. Low process pressures result in greater relative epitaxy growth rates and high pressures result in lower relative epitaxy deposition rates. The facet‐free process depends heavily on both the gate sidewall structure and the process conditions, where the combination of an undercut into the pad oxide and the nitride sidewall with the process pressure yield a reliably facet‐free process. Electrical results demonstrate that standard Ti or Co self‐aligned silicidation can be extended into a 0.1 μm gate length regime. © 1999 The Electrochemical Society. All rights reserved.

Propagation Losses of Guided Waves in Metallized Sidewall Waveguides

A step-index planar waveguide sidewalled with metals is theoretically studied by the effective refractive index method. Numerical results of the geometrical and wavelength dispersions of the propagation losses and the wavefunction profiles of the guided and the surface plasmon modes are presented. The aim of this study is to investigate the possibility of fabricating low-loss and small-size integrated optical waveguides or circuits using the metallized sidewall structure.

Analysis of Side-Wall Structure of Grown-in Twin-Type Octahedral Defects in Czochralski Silicon

We analyzed the side-wall structure of grown-in octahedral defects in Czochralski silicon standard wafers for large-scale integrated circuits. There are two types of twin octahedral defects: an overlapping type and an adjacent type. In the twin octahedral defects of the overlapping type, a hole is formed in the connection part. The side-wall layer in the hole part is formed continually and is the same thickness as the side-wall layers of both octahedrons. In the twin octahedral defects of the adjacent type, a partition layer is formed in the connection part. Our electron energy-loss spectroscopy analyses identified that the side-wall layer includes SiO2.

Facet Free Selective Silicon Epitaxy by Rapid Thermal Chemical Vapor Deposition

ABSTRACTA facet-free, selective epitaxy process has been identified using the SiH2CI2 /HCI/H2 chemistry in a commercially available, single-wafer epitaxy reactor. The pre-epitaxy bake required a minimum of 900°C in order to obtain a clean silicon surface with reasonable throughput while preserving the integrity of the shallow trench isolation structures. The epitaxy growth rate ranged from as low as 130Å/rnin at 825°C, 10 torr to as high as 1500 Å/min at 875°C and 70 torr while the deposition rate of polysilicon on polysilicon differed significantly: at 10 torr, the epitaxy growth rate is greater by as much as 50%, and at 70 torr the polysilicon deposition rate is greater by as much as 40%. The facet suppression depended heavily on two things: the undercut beneath the polysilicon gate sidewall insulator and the process pressure. The undercut is believed to be responsible for suppressing the initial stage of facet formation, most probably by completely eliminating lateral overgrowth of the crystal. The process conditions then enable continued facet suppression perhaps by restricting the silicon surface mobility. The sidewall structure and process conditions combine to make a reliably facet-free selective epitaxy process

Apparatus for uniform cleaning of wafers using megasonic energy

Apparatus and method for cleaning/etching the surface of an article with sonic energy in the megahertz range which employ an anti-reflection mechanism within a recirculation tank. A tank having at least one side wall and a bottom structure holds a cleaning/etching liquid and a megasonic transducer is associated with the tank for projecting megasonic energy into the liquid. The anti-reflection mechanism is disposed within the tank in close association with the at least one sidewall or bottom structure of the tank to thereby minimize reflection of megasonic energy from the associated surface. Preferably, the megasonic transducer is associated with a first tank sidewall which opposes a second tank sidewall, and the anti-reflection mechanism is disposed adjacent the second tank sidewall. By way of example, the anti-reflection mechanism can comprise a stream of gas bubbles, a plurality of anechoic structures, or a combination of both gas bubbles and anechoic structures.

Sub-20 ps ECL circuits with high-performance super self-aligned selectively grown SiGe base (SSSB) bipolar transistors

This paper describes a high maximum frequency of oscillation f/sub max/ self-aligned SiGe-base bipolar transistor technology, based on a self-aligned selective epitaxial growth (SEG) technology including graded Ge profile in an intrinsic base and link-base engineering using a borosilicate glass (BSG) sidewall structure. The transistor is a new self-aligned transistor, which we call a Super Self-aligned Selectively grown SiGe Base (SSSB) bipolar transistor. The 1st step of the annealing (800/spl deg/C, 10 min) was performed for the diffusion of boron from the BSG film, before the deposition of an emitter polysilicon film. The 2nd step of the annealing (950/spl deg/C, 10 sec) of emitter drive-in was carried out, which enabled us to obtain sufficient current gain using in-situ phosphorus doped polysilicon as an emitter electrode. Sheet resistance for a link-region more than one order lower than that of the epitaxial intrinsic base was obtained after heat treatment. Base profile (boron and Ge) design, and the 2-step annealing technique have realized cut-off frequency f/sub T/ of 51 GHz and f/sub max/ of 50 GHz. ECL circuits of 19-psec gate delay have been achieved.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Characteristics of Zinc Oxide Films on Glass Substrates Deposited by RF-Mode Electron Cyclotron Resonance Sputtering System

There are two types of electron cyclotron resonance (ECR) sputtering systems, DC-mode and RF-mode. In this paper, the properties of zinc oxide (ZnO) film deposited by an RF-mode ECR sputtering system capable of long-term stable deposition are investigated. It is confirmed for the first time that this system is capable of depositing a ZnO film having a sidewall structure without columnar or fibrous grains on an interdigital transducer (IDT)/glass substrate. The ZnO films so deposited were capable of driving the 1.1 GHz fundamental mode in a Rayleigh surface acoustic wave (SAW) without the large propagation loss at high frequencies of conventional ZnO films. Furthermore, ZnO films deposited by this system exhibited 1.7 dB lower insertion loss and a closer agreement between effective electromechanical coupling factors (keff) and the corresponding values calculated with the finite element method (FEM) in comparison with the films deposited by the DC-mode ECR sputtering system.

Characteristics of piezoelectric ZnO films deposited by RF mode electron cyclotron resonance sputtering system

Piezoelectric ZnO films on glass substrate were deposited by an RF mode ECR sputtering system. It was confirmed that in the ZnO films deposited by this system, a smooth sidewall structure of ZnO film without coarse columnar (fibre) grains was observed and that driving a 1.1 GHz fundamental mode of a Rayleigh SAW on ZnO/IDT/glass structure was possible at λ = 2.4 μm.

Device physics and technology of complementary silicon MESFET's for VLSI applications

The development of a complete complementary MESFET technology is presented. The state-of-the-art, fully implanted, CMOS-like process uses Shannon implants together with a refractory silicide Schottky-gate material to combine high gate barrier heights with ease of fabrication. To minimize parasitic resistances, a unique sidewall structure and sidewall spacers are utilized to allow for self-aligned implantation of the source/drain regions. A self-aligned titanium silicidation technique is employed to minimize sheet and contact resistance of the source/drain regions. The SUPREM process simulator was employed extensively. The performance and modeling of device parameters (e.g., threshold voltage, gate leakage, and short-channel effects) and circuit parameters (e.g. standby current, noise margin, and speed) were accomplished through analytic formulations, the PISCES two-dimensional device simulator, and the SPICE circuit simulator. >

On the prediction of propeller tone sound levels and gradients in an airplane cabin

Theoretical and computational methods are presented that will permit a basic prediction of the spatial variation of sound-pressure level in an airplane cabin arising from propeller excitation of fuselage sidewall structure. Analytical results focus on the calculation of the axial variation (or gradient) of the average mean-square pressure in cross section for the case of a trimmed cabin of uniform cross-sectional area terminating fore and aft in reflecting (and absorbing) partitions (i.e., bulkheads). Sample numerical predictions and qualitative comparisons with some available measurement data are presented.

Fine pitch TAB technology with straight side wall bump structure for LCD panel

A wafer-bumped TAB (tape automated bonding) device called the fine-pitch TAB device, which has been applied to a LCD (liquid crystal display) panel designed for a flat-panel display, is introduced and described. The devices, fabricated with flat-surface bumps and a straight side-wall structure instead of the conventional mushroom structure, have several important features, i.e. (1) the shear strength has an average value of 8.65*10/sup 3/ gr/mm/sup 2/, (2) the inner lead pitch (the bump pitch) is 100 mu m in the mass products, and a pitch of about 40 mu m is achieved in the test vehicle. The technique utilizes a triple layer of intermediate metals consisting of titanium, nickel, and palladium, applies the bump photoengraving process using a dry-film resist, uses the cyanide electroplating technique, and uses the ILB (inner lead bonding)/OLB (outer lead bonding) equipment with higher alignment accuracy. >