Si Source Gas Research Articles

Influence and Suppression of Harmful Effects Due to By-Product in CVD Reactor for 4H-SiC Epitaxy

Suppression of harmful effect due to by-product on homo-epitaxial growth of 4H-SiC films using a high speed wafer rotation vertical CVD method was demonstrated. Influence of by-product, such as 3C-SiC deposit on a hot-wall and Si deposit on gas nozzles, formed during the epitaxial growth was investigated in two comparative studies. The analysis of triangular defects with 3C-SiC down-falls on the films revealed that the most of the down-falls which were peeled from the hot-wall adhered to the wafers before the epitaxial growth. By increasing the wafer rotation speed to 300 rpm just after wafer loading into the reactor, the down-falls dropped towards the wafer surface were effectively eliminated, and the maintenance period of the reactor could be increased more than 4 times compared to the case of maintaining the wafer rotation speed of 50 rpm until just before epitaxial growth step. Additionally, the relationship between Si deposit formed on the gas nozzles in the gas inlet and fluctuation of thickness and doping concentration of the films suggested that Si deposit formed on the gas nozzles acts as a trap site of Si source gas. By suppression of the Si deposit using optimizing gas flow condition, no significant fluctuation of thickness and doping concentration of the films were observed and the maintenance period of the gas nozzles could be increased more than 3 times compared to the epitaxial growth using the nozzles on which Si deposit was formed.

Effects of Silicon Source Gas and Substrate Bias on the Film Properties of Si-Incorporated Diamond-Like Carbon by Radio-Frequency Plasma-Enhanced Chemical Vapor Deposition

We have deposited Si-incorporated diamond-like carbon (DLC) films by radio-frequency plasma-enhanced chemical vapor deposition using methane, argon, and organosilanes, and investigated the effects of Si source gas (monomethylsilane, dimethylsilane) and substrate bias (negative dc bias, negative pulse bias) on the structure and the mechanical and tribological properties of the films. The Si-DLC films deposited using monomethylsilane as a Si source gas tended to have a higher Si atomic fraction ratio [Si/(Si+C)] than the films deposited using dimethylsilane. Friction coefficient and internal stress decreased by the incorporation of Si into the films. However, many particles composed mainly of Si were observed on the film surfaces when deposition using a dc bias was carried out at higher monomethylsilane or dimethylsilane flow ratios. It was found that for both the Si source gases, the use of a pulse bias was effective in suppressing the formation of particles and further decreasing friction coefficient and internal stress. Additionally, the pulse-biased Si-DLC films were found to have a higher wear resistance than the dc-biased Si-DLC films.

In situ Ni–Si nanowire junction based on substrate sourced growth and its electrical transport behavior

The authors report on formation of high current carrying Ni–Si nanowires between Ni/heavily doped polycrstaliine Si contacts using substrate sourced growth without any supply of Si source gas. The conductance (G) of a 18nm diameter nanowire bridge in the temperature range of 13–293K showed a power function of temperature Tα, with a typical exponent α≈0.62±0.06, and the dI∕dV were fitted to the Vα with α≈0.55±0.15. Although the power law dependence of the G and dI∕dV, which provides evidence for the interaction of the electrons in a low-dimensional infinite conductor, corresponds to the featured behavior of the interacting electrons within an error tolerance, the strength of the interaction is very weak due to the highly metallic characteristics with finite length and lack of purity of the channel. As a result, the in situ high current carrying Ni-Si nanowire junction can be utilized not only as a nanointerconnector, but also as a tool to study low-dimensional electrical transport properties.

The Self-Assembling “Grow-in-Place” Process: An Environmentally Friendly Approach to Nanowire Device Fabrication

AbstractSilicon nanowires (SiNWs) were fabricated directly from the Si source gas into pre-fabricated permanent nanochannel templates by our self-assembling “grow-in-place” approach. The size, shape, position, orientation, and number of the SiNWs can be precisely controlled by the pre-fabricated nanochannel templates. Our approach is environmentally benign and friendly since only the exact number of SiNWs needed was grown and the SiNWs were always confined in the nanochannel templates. In addition, the templates can be fabricated with built-in contacts and integrated into the final devices, providing contacts, interconnects, and passivation/encapsulation. We are developing a variety of built-in ohmic and rectifying contact structures and approaches for the “grow-in-place” methodology. Some initial results will be discussed here.

A Novel Processing Route to Control Grain Growth in Submicrometer Alumina Compacts

A novel processing procedure for significantly suppressing grain growth in submicrometer alumina compacts has been developed and implemented with the intent of ultimately using the same processing route to control grain size in nanophase alumina compacts. In this study, partially sintered alumina pellets made from 0.5 µm starting powders are altered by the chemical infiltration of Si3N4. The control and infiltrated pellets are then heated to 1650°C for 4 h. The fully sintered pellets are approximately 97% dense. Suppressed grain growth is observed in the infiltrated pellets. The average grain size in the control pellets after densification is 4.2 and 1.2 µm in the infiltrated pellets. Depth of infiltration is measured using transmission electron microscopy (TEM) and scanning electron microscopy (SEM). Depending on the specific infiltration conditions used, the outer 15-50% of the infiltrated pellets exhibit a graded microstructure consisting of a region of abnormal grain growth and a region of suppressed grain growth. Abnormal grain growth is visible on the outer surfaces of the infiltrated pellets where a relatively high ratio of Si to N is present. Further into the pellet, after some depletion of the Si source gas has occurred, regions of suppressed grain growth are apparent. Based on these results, an infiltration profile is determined. A mathematical model is developed to describe the infiltration process and to determine optimal infiltration conditions. High-resolution electron microscopy (HREM), energy dispersive spectroscopy (EDS), electron energy loss spectroscopy (EELS), and X-ray photoelectron spectroscopy (XPS) are used to study the infiltrated samples.

From Si Source Gas Directly to Positioned, Electrically Contacted Si Nanowires: The Self-Assembling “Grow-in-Place” Approach

Our grow-in-place approach to Si nanowire devices uses a silicon precursor gas (e.g., SiH 4 ) to directly produce self-assembled, electrically contacted, crystalline Si nanowires without any intervening silicon material formation or collection/positioning steps. The approach uses the vapor-liquid-solid (VLS) growth mechanism and lithographically fabricated, permanent, nanochannel growth templates to control the size, shape, orientation, and positioning of the nanowires and ribbons. These horizontal templates are an integral component of the final devices and provide contacts, interconnects, and passivation/encapsulation. The approach results in self-assembly of the Si nanowires (SiNWs) and nanoribbons (SiNRs) into interconnected devices without any pick-and-place or printing steps, thereby avoiding the most serious problems encountered in process control, assembly, contacting, and integration of SiNWs and SiNRs for IC applications. As an initial demonstration of our approach, we have fabricated SiNW and SiNR resistors with built-in electrical contacts and encapsulation and report conductivity measurements.

Nucleation Control by Intermittent Supply of Dichlorosilane towards the Fabrication of Polycrystalline Silicon Thin Films with Large Grain Size

To obtain polycrystalline Si (poly-Si) thin films with large grain size, we propose a nucleation control method by intermittent supply of Si source gas in atmospheric pressure chemical vapor deposition. By intermittent supply of dichlorosilane as Si source gas, the nucleus density was controlled to between 105 and 107 cm-2. The maximum grain size of 22 µm with a film thickness of 15 µm was obtained. By optimizing the conditions of intermittent ratio and time, a relatively high preferential orientation of (220) over 65% was achieved. In addition, the poly-Si thin film with continuous columnar structure was obtained.

Structure and properties of rapid thermal chemical vapor deposited polycrystalline silicon–germanium films on SiO2 using Si2H6, GeH4, and B2H6 gases

Deposition of undoped and in situ boron-doped polycrystalline silicon-germanium (poly-Si1−xGex) films on oxide has been investigated at temperatures below 625 °C and a pressure of 4 Torr in a rapid thermal chemical vapor deposition system. The influences of reactant gases such as Si2H6, SiH4, GeH4, and B2H6 on the nucleation behavior, and structural properties of poly-Si1−xGex films formed on oxide were studied. The experimental results showed that in situ boron-doped or undoped poly-Si1−xGex films can be directly deposited on oxide without an initial Si predeposition layer to provide the necessary nucleation sites on the surface when using Si2H6 as the Si source gas. However, when SiH4 was used as the Si source gas, only in situ boron-doped films can be deposited nonselectively on the oxide without the initial Si predeposition layer, and to deposit undoped poly-Si1−xGex films, Si predeposition is needed, otherwise Si1−xGex islands are formed on the oxide. X-ray diffraction analysis showed that poly-Si1−xGex films deposited using Si2H6, GeH4, and B2H6 gas mixture have three singular peaks corresponding to {311}, {220}, and {111} planes, thus indicating the Si1−xGex alloy is formed. In addition, we found that B2H6 gas has a minor effect on the Ge incorporation into the films but reduces the overall deposition rate.

Si Nanowires Grown via the Vapour–Liquid–Solid Reaction

Si nanowires as thin as 10 nm have been grown using silane gas as the source gas in the Vapour–Liquid–Solid (VLS) reaction. This paper describes the nucleation, growth and oxidation of the wires and a technique developed to control the wire diameter and position. A very thin layer of Au is deposited onto a Si(111) surface at room temperature. Silane gas is then introduced into the chamber as the VLS Si source gas and the temperature is raised to 300 to 700 °C. Initially a catalytically active Au surface phase which coats the surface leads to the growth of a defective epitaxial Si layer. As Au/Si molten alloy balls nucleate and grow in size to approach the threshold size for VLS wire growth, which is determined by the Gibbs-Thomson effect, the epitaxial layer growth rate decreases and a transition to Si nanowire growth occurs. The morphology and width of the wires is strongly dependent on the growth temperature and pressure. At low pressure and high temperature relatively thick well-formed wires grow straight up from the substrate surface along the [111] direction. As the temperature is decreased and the pressure is increased thinner wires grow which tend to exhibit growth defects. The Si nanowires can be thinned down by oxidation. A light oxidation yields Si cores which are of the order of 5 nm in diameter. A method to control the position of the Si wires which exploits the difference in Au sticking coefficient on Si and SiO2 surfaces at elevated temperature (T > 540 °C) has recently been developed. Using thermally oxidized Si(111) as a starting substrate, circular holes ≈1.5 μm in diameter were etched through the SiO2 to expose the Si. The sample was heated to 700 °C and exposed to a flux of Au atoms. For low Au fluxes (≈1×1014 atoms cm—2 s—1) the Au sticking coefficient on the SiO2 surface is negligible at 700 °C but remains unity on the exposed Si surface in the holes. The liquid alloy which forms in the holes during Au deposition is able to agglomerate to form a single ball in each hole. The quantity of Au which contributes to each ball can be controlled because it is determined by the hole size and the total Au dose. When silane gas is then introduced into the chamber each alloy ball grows to form a Si wire of controlled diameter whose position is quasi-controlled by the initial patterning. No wire growth occurs on the SiO2 surface due to the absence of Au. This ability to control the size and position of the Si wires should make it possible to conduct optical and transport measurements on a single wire of known dimensions.

Control of the Size and Position of Silicon Nanowires Grown via the Vapor-Liquid-Solid Technique

The diameter and position of vapor-liquid-solid (VLS) grown Si nanowires can be controlled by exploiting the difference in Au condensation coefficient on Si and SiO2 surfaces at elevated temperature. For low Au fluxes in the temperature range 520–700° C, Au condensation is completely selective to Si. Holes are etched through the surface oxide layer of a thermally oxidized Si(111) wafer to expose the Si. When Au is then evaporated onto the surface, the Au atoms condense selectively in the holes and form liquid Au/Si alloy balls. If the holes contain a small Si island protrusion formed by etching this acts as an alloy nucleation center and the alloy can agglomerate to form a single ball, the diameter of which is determined by the diameter of the hole and the total dose of Au. When silane gas is then introduced into the chamber as the Si source gas in the VLS reaction each alloy ball grows to form a Si wire of controlled diameter and position.

Growth of silicon nanowires via gold/silane vapor–liquid–solid reaction

Silicon nanowires (whiskers) have been grown on Si(111) via the vapor–liquid–solid (VLS) reaction using silane as the Si source gas and Au as the mediating solvent. The silane partial pressure and temperature ranges were 0.01–1 Torr and 320–600 °C, respectively. Growth at high partial pressure and low temperature leads to the growth of Si nanowires as thin as 10 nm. These wires are single crystals but exhibit growth defects such as bending and kinking. Lowering the silane partial pressure leads to an increase in the wire width and a reduction in the tendency to form growth defects. At low pressure, 40–100 nm wide well-formed wires have been grown at 520 °C. The VLS reaction using silane allows the growth of Si wires, which are significantly thinner than those grown previously using SiCl4.

Process Improvements in the Selective Epitaxial Growth of Si1 − xGex / Si Strained Layers in a Conventional Hot‐Wall LPCVD System

Three process considerations were identified as essential for the selective epitaxial growth (SEG) of SiGe in hot‐wall tubular low pressure chemical vapor deposition reactors. A thermodynamic analysis of the system revealed that the hydrogen bake condition for SiGe SEG had to be modified from that for Si SEG to eliminate outgassing of residual Ge, which adversely affected the initial growth surface. A two‐step hydrogen bake was developed to eliminate the problem. A high temperature bake, carried out before wafer loading, removed residual Ge deposited on the reactor wall from the previous run. After wafer loading, removed residual Ge deposited on the reactor wall from the previous run. After wafer loading and purge, a lower temperature bake then removed the native oxide. Second, a selectively grown Si buffer layer improved the initial growth surface for later SiGe SEG. The Si buffer layer covered the remaining native oxide, which the previous hydrogen bake did not totally remove, and reduced the defects at the interface. Finally, a small flow of Si source gas during the temperature ramp down period helped to keep the buffer layer surface clean prior to SiGe SEG. All three steps proved to be essential in obtaining SiGe SEG of higher quality.

Ge deposition from digermane on the Si(100)-(2 × 1) surface

The initial deposition of Ge on Si(100) has been followed by TPD (temperature programmed desorption) and AES (Auger electron spectroscopy). The Ge Si(100) surfaces were prepared from repeated cycles of chemisorption and thermal desorption of Ge 2H 6 on the Si(100) surface. Simultaneous exposures of UV light and Ge 2H 6 flux was shown to enhance the Ge deposit per chemisorption/flash cycle. The desorption of D 2 from Ge Si(100) has also been studied. The D 2 desorption maxima shift to lower temperatures with increasing Ge coverage until a new low-temperature desorption state prevails. This fact provides a possible clue to explain the acceleration in growth rate observed during SiGe alloy growth by CVD when GeH 4 is incorporated to the Si source gas.

The Characteristics and Oxidation of Vapor - Liquid - Solid Grown Si Nanowires

AbstractThe Vapor - Liquid - Solid (VLS ) technique allows the growth of high aspect ratio Si wires. The Si nanowires formed by this technique can be thinned down by oxidation. This approach allows the formation of very thin Si cores which may be used to research the properties of Si nanostructures. In this work the growth and oxidation of these wires is characterized.In the growth a very thin layer of Au is deposited on a Si (111) surface, silane gas is introduced into the chamber as the Si source gas and the temperature is raised to 300 – 600°C. Initially a catalytically active Au surface phase leads to the growth of a defective epitaxial Si layer. As Au / Si molten alloy balls nucleate and grow in size to approach the threshold size for VLS wire growth, which is determined by the Gibbs - Thomson effect, the epitaxial layer growth rate decreases and a transition to Si nanowire growth occurs. The morphology and width of the wires is strongly dependent on the growth temperature and pressure. At low pressure and high temperature relatively thick well-formed wires grow straight up from the substrate surface along the [111] direction. As the temperature is decreased and the pressure is increased thinner wires (as thin as 10 nm ) grow which tend to exhibit growth defects. A light oxidation yields Si cores which are of the order of 5 nm in diameter.

Selective TiSi2 Formation Using TiCl4(g), Si(s) and H2(g): A study of the Mask Loading Phenomena

In this paper, we explore the loading effect during reactions of TiC14(g) with Si(s) to form selective TiSi2 in a tungsten halogen lamp heated, cold wall rapid thermal chemical vapor deposition reactor. The process is intended as a replacement for the conventional sellaligned silicide process with the capability of reducing the process steps from four to one. In the absence of a Si source gas for this process, the Si is supplied from the substrate forming TiSi2 via consumption. The chemistry is highly selective to both Si02 and Si3N4. However, it has been previously shown by our group and others that TiSi2 formation can be accompanied by Si substrate etching which can be suppressed by adding H2 to the chemistry. In this study, we have considered cxposed Si area percentages ranging from 18% to 88% on 4” Si substrates. Two simplified gas systems are used to closely examine substrate etching and consumption: TiCI4 - Si(s) and TiCI4 - Si(s) - H2 The Si etch and consumption rates are evaluated for these varying exposure percentages. We have found that the substrate etch rate increases as the exposed area to be etched is decreased as does the substrate consumption rate.

Thermally Deposited Amorphous Silicon

We investigated a thermally deposited amorphous silicon (TAS) film before and after annealing. We used monosilane or disilane as the Si source gas at a deposition pressure of 0.1 to 0.5 Torr. The activation energy of deposition was 1.7 eV (560 to 600°C) and that of was 0.6 eV (510 to 570°C). From TEM observation, the TAS film from 450°C deposition was completely amorphous without crystals and had a smooth surface. Film deposited at 560°C had a few crystals at the interface and had a few bumps on the Si surface. After annealing, the mean grain size of film was about 2 μm and that of film was about 0.3 μm. We also evaluated the crystallinity by XRD and Raman spectroscopy. Films deposited at lower temperatures after annealing showed strong ‘111’‐orientations and high crystal qualities.

Investigation on the growth rate enhancement by Ge during SiGe alloy deposition by chemical vapor deposition

The desorption of deuterium from clean and Ge-covered Si(100) surfaces has been studied using temperature-programmed desorption. The Ge/Si(100) surfaces were prepared using the dissociative adsorption of digermane on Si(100). The presence of Ge on Si(100) dramatically lowers the deuterium (or hydrogen) desorption temperature. The desorption maxima shift to lower temperature with increasing Ge coverage until a new low-temperature desorption state becomes dominant. The lowering of the deuterium desorption energies due to the presence of Ge on the Si(100) surface is used to explain the acceleration in growth rate observed during GexSi1−x alloy growth by chemical vapor deposition upon the introduction of germane to the Si source gas.

Doping of GaN with Si and properties of blue m/i/n/n + GaN LED with Si-doped n +-layer by MOVPE

The doping of GaN with silicon (Si) has been studied using SiH 4 as the Si source gas. A Si-doped n-type GaN film with a free electron concentration of 10 16-10 18cm -3 and resistivity of 1−10 -2Ω cm at RT can be easily obtained by controlling the flow rate of SiH 4 during growth. Blue m/i/n/n + LEDs have been fabricated for the first time using a Si-doped n +-GaN layer. The EL peak wavelength was ≁ 485 nm, and brightness was ≁ 50 mcd at a forward current of 10mA.

Growth of Si-doped Al xGa 1– xN on (0001) sapphire substrate by metalorganic vapor phase epitaxy

Effects of Si-doping on the electrical and luminescence properties of GaN and A1 0.1Ga 0.9N epitaxial films have been studied. GaN and A1 0.1Ga 0.9N films were grown by MOVPE on (0001) sapphire substrates using A1N buffer layers. SiH 4 was used as Si source gas. The conductivities of n-type A1 0.1Ga 0.9N film were found to be controllable by varying the flow rate of SiH 4 during growth. Cathodoluminescence spectra of both GaN :Si film and A1 0.1Ga 0.9N :Si film are strong near the bandedge emission, and their intensity increases with increasing Si concentration. These results indicate that (1) GaN :Si and A1 0.1Ga 0.9N :Si films grown using A1N buffer layers have a high quality and (2) Si replaces group-III (Ga or A1) elements at lattice sites in the GaN film and also in the A1 0.1Ga 0.9N film.

Silicon doping of GaAs and Al xGa 1− xAs using disilane in metalorganic chemical vapor deposition

Disilane is presented as a new Si source gas in the metalorganic chemical vapor deposition of both GaAs and Al x Ga 1- x As. The doping characteristics of disilane were studied over a wide range of growth conditions: temperature, gas phase stoichiometry, and disilane concentration in the growth ambient. Disilane exhibits several features as a doping gas which prove it superior in this application to silane, the conventional silicon source gas. Doping by means of disilane shows no dependence on growth temperature in sharp contrast to the strong temperature dependence found using silane. The decomposition reaction of disilane is very efficient, reducing the amount of dopant gas required by about two orders of magnitude at the lower growth temperatures. The doping efficiency of disilane is also independent of the aluminum content of the Al x Ga 1− x As alloy layers. These results indicate that disilane may be the preferred silicon doping gas for GaAs and Al x Ga 1− x As.