Shortened Reed-Solomon Codes Research Articles

Development of a Shorted Interleaved Reed-Solomon Codes (siRS) for data downlink in Stratospheric Probes and Nano-Satellites

In the last 10 years, the advancement in the electronics have made possible the development of more sophisticated unmanned vehicles and probes, manufactured using Components-Of-The-Shelf (COTS) available to public, whether be for industrial of scientific purposes. In the matter of aerospace exploration, the CubeSats are the best example of sophisticated devices partially of entirely developed using this commercial COTS. The financial cost of some components is still a point of consideration in the design, but it is not entirely a show-stopper since some low-cost components can be optimized to meet the necessary requirements and increase the reliability. In the case of stratospheric probes and nano-satellites, the Telemetry, Tracking and Command (TT&C) subsystem, in charge of the data uplink/ downlink, can be improved by including an Error Correcting Code (ECC), making possible to use commercial transceivers of low-power are low-cost. In this article we describe an implementation of an interleaved and shortened Reed-Solomon Code, which we called siRS, to improve the image and telemetry downlink in stratospheric probes and nano-satellites, using entirely low-cost commercial RF transceivers and an ARM-based mini-PC.

Multiple-Layer Integrated Interleaved Codes: A Class of Hierarchical Locally Recoverable Codes

The traditional definition of Integrated Interleaved (II) codes generally assumes that the component nested codes are either Reed-Solomon (RS) or shortened Reed-Solomon codes. By taking general classes of codes, we present a recursive construction of Extended Integrated Interleaved (EII) codes into multiple layers, a problem that brought attention in literature for II codes. The multiple layer approach allows for a hierarchical scheme where each layer of the code provides for a different locality. In particular, we present the erasure-correcting capability of the new codes and we show that they are ideally suited as Locally Recoverable codes (LRC) due to their hierarchical locality and the small finite field required by the construction. Properties of the multiple layer EII codes, like their minimum distance and dimension, as well as their erasure decoding algorithms, parity-check matrices and performance analysis, are provided and illustrated with examples. Finally, we will observe that the parity-check matrices of high layer EII codes have low density.

Forward Error Correction For Gigabit Automotive Ethernet using RS(450,406) Encoder

Error correction and detection during data transmission is a major issue. For resolving this, many error correction techniques are available. The Reed-Solomon coding is the most powerful forward error correction technique used in Gigabit Automotive Ethernet to compact channel noise during data transmission. The car becomes more smarter day by day and more new advanced electronics is being used in-vehicle. Gigabit Automotive Ethernet(1000BASE-T1) provide fast bandwidth for many kinds of applications and connect different functional parts in the car. The Reed Solomon(RS) coding is the powerful forward error correction(FEC) technique used in 1000BASE-T1 Automotive Ethernet. RS(450,406) coding is also known as shortened Reed Solomon codes. The Reed Solomon(RS) codes are generally used in communication system due to its ability of correcting both random and burst errors. Reed Solomon codes are no-binary systematic linear block codes. RS coding is widely used in high speed communication system. This RS code is implemented using Galois field(GF). The Automotive Ethernet is encoded using RS(450,406) codes through GF(512) for FEC. This RS codes can corrects the error up to t=22 symbol, while other encoding techniques corrects the error in t bits. In this paper we implemented the RS(Reed Solomon) code in Cadence ncsim Verilog software and used Cadence Simvision for showing timing diagrams. This RS code uses 9-bit based shortened (450,406) code.

FPGA-based Implementation of a Streaming Decoder for Shortened Reed-Solomon Codes

FPGA-based Implementation of a Streaming Decoder for Shortened Reed-Solomon Codes

ANALYSIS OF METHODS OF CONSTRUCTION AND ENCODING LOW-DENSITY PARITY CHECK CODES

The article analyzes the famous methods of construction and representations of the check matrix block and convolutional codes with low-density parity-check. The analysis the famous methods of coding block and convolutional codes with low-density parity-check. Showed advantages and disadvantages of the known methods and allowed to identify and formulate a scientific and technical challenge. Shows the method of representation of the check matrix block codes with low-density parity-check using the Tanner graph, which like the check matrix is fully defines the parameters of the code. Check matrix of convolutional codes with low-density parity-check can also be described by Tanner graph, however, because the check matrix is infinite, then the Tanner graph is infinite. The analysis method of constructing the parity check matrix of block codes with low-density parity-check, which is based on a shortened Reed-Solomon code. Codes constructed in this method have a Tanner graph girth at least 6, which allows them to effectively use iterative decoding methods.

Implementation of Product Reed Solomon Codes for Multi level cell Flash controller

In recent years, multi-level cell (MLC) flash memories have been developed as an effective solution for increasing the storage density and reducing the cost of flash memories. MLC flash memories are especially for NAND flash memories . Error control coding (ECC) is essential for correcting errors in Flash memories.In order to correct multiple random errors and burst errors, an efficient decoding algorithms are required.In this work (255, 231) Product Reed-Solomon (RS) code technique for non-volatile NAND flash memory system sare used. In this proposed code that is Product Reed Solomon can correct both multiple random errors and burst errors. The Product Reed Solomon code consists of two shortened Reed-Solomon codes and a conventional Reed- Solomon code. It can correct up to certain symbol errors. A simulation result shows that the code has improved the coding gain and low power consumption.

Novel Burst Error Correction Algorithms for Reed-Solomon Codes

In this paper, we present three novel burst error correcting algorithms for an (n, k) Reed-Solomon code. The algorithmic complexities are of the same order as error-and-erasure decoding, O(rn), where r=n-k. In particular, their hardware implementation shares elements of Blahut error-and-erasure decoding. In contrast, all existing single-burst error correcting algorithms, which are equivalent to the proposed first algorithm, have complexity O(r2n). The first algorithm corrects the shortest single-burst with length f up to r-1. The algorithm follows the key characterization that the ending locations of all candidate bursts can be purely determined by the roots of a polynomial which is a linear function of syndromes, and moreover, the shortest burst is associated with the longest sequence of consecutive roots. The algorithmic miscorrection probability is bounded by q-(r-1-f), where q denotes the field size. The second algorithm extends the first one to correct the shortest burst with length f ≤ r-3 and additionally a random symbol error. The algorithmic miscorrection probability is bounded by q-(r-3-f). The third algorithm probabilistically corrects the shortest burst with length f ≤ r-1-2δ and additionally δ (a small constant) random symbol errors. The algorithmic miscorrection and failure probabilities are both bounded by q-(r-1-2δ-f). Our simulation results for (60, 40) and (30, 16) shortened Reed-Solomon codes verify that the miscorrection probability for three algorithms and the failure probability for the third algorithm all decay exponentially (at the rate of q-1) with respect to the length of burst.

Reduced-Complexity Decoders of Long Reed-Solomon Codes Based on Composite Cyclotomic Fourier Transforms

Long Reed-Solomon (RS) codes are desirable for digital communication and storage systems due to their improved error performance, but the high computational complexity of their decoders is a key obstacle to their adoption in practice. As discrete Fourier transforms (DFTs) can evaluate a polynomial at multiple points, efficient DFT algorithms are promising in reducing the computational complexities of syndrome based decoders for long RS codes. In this paper, we first propose partial composite cyclotomic Fourier transforms (CCFTs) and then devise syndrome based decoders for long RS codes over large finite fields based on partial CCFTs. The new decoders based on partial CCFTs achieve a significant saving of computational complexities for long RS codes. Since partial CCFTs have modular and regular structures, the new decoders are suitable for hardware implementations. To further verify and demonstrate the advantages of partial CCFTs, we implement in hardware the syndrome computation block for a $(2720, 2550)$ shortened RS code over GF$(2^{12})$. In comparison to previous results based on Horner's rule, our hardware implementation not only has a smaller gate count, but also achieves much higher throughputs.

Error resilient data transport in sensor network applications: A generic perspective

AbstractThe error recovery problem in wireless sensor networks is studied from a generic resource‐constrained energy‐optimization perspective. To characterize the features of error recovery schemes that suit the majority of applications, an energy model is developed and inferences are drawn based on a suitable performance metric. For applications that require error control coding, an efficient scheme is proposed based on an interesting observation related to shortened Reed–Solomon (RS) codes for packet reliability. It is shown that multiple instances (γ) of RS codes defined on a smaller alphabet combined with interleaving results in smaller resource usage, while the performance exceeds the benefits of a shortened RS code defined over a larger alphabet. In particular, the proposed scheme can have an error correction capability of up to γ times larger than that of the conventional RS scheme without changing the rate of the code with much lower power, timing and memory requirements. Implementation results show that such a scheme is 43% more power efficient compared with the RS scheme with the same code rate. Besides, such an approach results in 46% faster computations and 53% reduction in memory requirements. Copyright © 2008 John Wiley & Sons, Ltd.

Architecture for decoding adaptive Reed-Solomon codes with variable block length

An adaptive Reed-Solomon (RS) decoder is designed, which can decode RS codes of any block length n as well as any message length k. This unique feature is favorable for a shortened RS code, since it eliminates the need to insert zeros before decoding the code. Furthermore, the value of error-correcting capability t can be changed at every codeword block. The decoder permits 4-step pipelined processing based on the modified Euclid's algorithm (MEA). Each step has a structure suitable for decoding RS codes with varying block length. A new architecture for the MEA is designed for varying values of t. The operating length of the shift registers shortened by one can be adjusted to be varied according to the different values of t. To maintain the throughput rate with less circuitry, the MEA block uses both the multiplexing and recursive technique and the overclocking technique. The adaptive RS decoder over GF(2/sup 8/) having the error-correcting capability of up to 10 has been designed in VHDL, and successfully synthesized in a FPGA chip.

A class of array codes correcting multiple column erasures

A family of binary array codes of size (p-1)/spl times/n, with p a prime, correcting multiple column erasures is proposed. The codes coincide with a subclass of shortened Reed-Solomon codes and achieve the maximum possible correcting capability. Complexity of encoding and decoding is proportional to rnp, where r is the number of correctable erasures, i.e., is simpler than the Forney decoding algorithm. The length n of the codes is at most 2p-1, that is, twice as big as the length of the Blaum-Roth codes having comparable decoding complexity.

Multibit correcting data interface for fault-tolerant systems

A fault-detecting, bidirectional data interface between uncoded data from one component, such as a processor, and coded data in the rest of the system is described. This interface is capable of correcting a single multibit symbol error or detecting the occurrence of two such errors. The device uses a shortened Reed-Solomon code, and two practical symbol sizes are considered; nibble (4-bit) errors are protected by a (40, 32) binary equivalent shortened code, and byte errors are covered by a (80, 64) binary-sized code. The Reed-Solomon codes have maximum protection levels, even when shortened, and allow simplifying the design options. A dual orthogonal basis used for the symbols' representations provides significant hardware savings. The interface unit achieves internal fault detection by comparing regenerated parity values in a totally self-checking equality checker. A fault-tolerant ultrareliable memory module is proposed and evaluated. An illustrative design is realized using a single desktop programmable gate array. >

Nibble-based error detection or correction (EDOC) chip

Common circuit elements in digital designs lead to correlated errors that overwhelm bit-oriented error-correcting devices used for fault-tolerance. We describe the design and implementation of a circuit that will either correct a single nibble (4-bit) error or detect a double nibble error, but not bothsimultaneously. It uses a shortened Reed-Solomon code over a field with 16 elements.