Short-channel Thin-film Transistors Research Articles

(Invited) Improved Thin Film Transistor Model Predicts TFT Operation in the THz Range

Novel Thin-film-transistor (TFT) TFT materials such as ZnO, InGaZnO, AMO-CNT, and organic materials dramatically improved the achieved and projected TFT performance. The low field mobility of oxide materials has reached values comparable to those for short-channel Si CMOS. The effects related to electron inertia and electron density oscillations in field effect transistors channels (FETs) diminish the role of the low field mobility as a figure of merit in short channel devices making the performance gap between TFTs and Si CMOS smaller enabling high frequency TFT applications even reaching sub-THz and THz frequencies (for the operating regimes using the rectification of the plasma oscillations. We report on an improved compact model based on the RPI TFT model [1] and using the Unified Charge Control Model (UCCM). [2, 3] This model accounts for a non-exponential slope in the subthreshold regime by introducing a varying subthreshold slope and accounts for non-trivial capacitance dependence on the gate bias. It also accommodates the inclusion of the parasitics related to the gate impedance. These new features allowed us to obtain an excellent agreement with the measured I-V/C-V characteristics for both long and short n-channel and p-channel TFTs. The application of this new TFT model to the analysis of the TFT response requires accounting for non-local potential distribution in the device channel. This is achieved by using a multi-segment nonlinear transmission line model of the TFT channel reproducing the approach that has been previously used for the THz SPICE/ADS Si CMOS model implementation. As a possible application example, we simulated a TFT complementary inverter. Our simulations showed that using the phase-matched THz signal feeding should yield a very sensitive detection of THz radiation impinging on a short channel TFT. These results show that the TFT RFID and other applications could be extended into the THz range of frequencies.

(Invited) Improved Thin Film Transistor Model Predicts TFT Operation in the THz Range

Novel materials such as ZnO, InGaZnO, AMO-CNT, and organic materials and improved fabrication processes dramatically enhanced the achieved and projected thin film transistor (TFT) performance. The effective field-effect mobility of metal oxide TFT materials has reached values comparable to those for short-channel Si CMOS. We report on an improved compact model based on the RPI TFT model, the unified charge control model (UCCM), and the multi-segment TFT compact model. This improved model accounts for a non-exponential slope in the subthreshold regime by introducing a varying subthreshold slope and accounts for non-trivial capacitance dependence on the gate bias. The application of this new TFT model to the analysis of the TFT response showed that a TFT complementary inverter using the phase-matched THz signal feeding should yield a very sensitive detection of THz radiation impinging on a short channel TFT.

Modeling of High-Current Polycrystalline Silicon Thin Film Transistors by Incorporating Buried Electrode

For display applications, high current and large on/off current ratio are pursued for driving and switching transistors. In this article, a thin film transistor (TFT) device incorporating a buried electrode is proposed, which enables increasing the driving current by reducing the channel length, with the channel length only at the drain side. This lateral short-channel TFT enables increasing the on-current while maintaining the field effect mobility, in comparison to our experimental short-channel vertical TFT structure. Another advantage of the proposed structure lies in the suppression of the Schottky barrier at the source and drain contacts when using high-work-function source/drain contacts for an N-type TFT, with an increased on/off current ratio reaching approximately 106. The suppression of Schottky barrier at the source/drain has been verified by the contact resistance measurements. Even though high driving current is obtained, the off-current is still high due to the weakened electric field at the source/drain sides and needs to be further optimized.

1.3: Realization of Short Channel Thin Film Transistors with High Mobility IGTO

SID Symposium Digest of Technical PapersVolume 52, Issue S1 p. 7-7 Technical Sessions: Session 1: Oxide TFT-High Performance (Active-Matrix Devices)Free to Read 1.3: Realization of Short Channel Thin Film Transistors with High Mobility IGTO Weihua Wu, Weihua Wu National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorYi Zhuo, Yi Zhuo National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorFangmei Liu, Fangmei Liu National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorYuanpeng Chen, Yuanpeng Chen National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorJiangbo Yao, Jiangbo Yao National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorHyun-Sik Seo, Hyun-Sik Seo National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorYuan-Jun Hsu, Yuan-Jun Hsu National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this author Weihua Wu, Weihua Wu National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorYi Zhuo, Yi Zhuo National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorFangmei Liu, Fangmei Liu National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorYuanpeng Chen, Yuanpeng Chen National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorJiangbo Yao, Jiangbo Yao National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorHyun-Sik Seo, Hyun-Sik Seo National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this authorYuan-Jun Hsu, Yuan-Jun Hsu National Engineering Laboratory for AMOLED Process Technology, Shenzhen China Star Optoelectronics Semiconductor Display Technology Co. Ltd, Shenzhen, Guangdong, ChinaSearch for more papers by this author First published: 24 February 2021 https://doi.org/10.1002/sdtp.14351AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL Share a linkShare onFacebookTwitterLinked InRedditWechat No abstract is available for this article. Volume52, IssueS1International Conference on Display Technology (ICDT 2020)February 2021Pages 7-7 RelatedInformation

(Invited) Device Scalability of InGaZnO TFTs for Next-Generation Displays

Amorphous oxide semiconductor thin-film transistors (TFTs) are used as the backplane for large-screen, high-resolution OLED and LCD displays. Amorphous InGaZnO (a-IGZO) TFTs are widely used in commercialized TVs, tablets, and wearable displays for its good device performance, stability, and process controllability. Also, due to its extremely low off-current, a-IGZO TFTs are used for low refresh rate and low-power displays. Furthermore, a-IGZO TFTs have a low process temperature, enabling fabrication on various substrates (including flexible films), and also hybrid integration with other backplane technologies, such as LTPS or Si CMOS. By taking advantage of the low off-current and low process temperature, a-IGZO can be monolithically integrated in the back-end of Si CMOS for low-power applications, as well as embedded memories for long retention and non-volatile operation. There are many incentives to shorten the channel length of IGZO TFTs. First, shorter channels can boost the current without incorporating high-mobility oxides, which usually suffer from reliability issues and small process margin. When gate drivers are integrated directly onto the panel, larger currents allow smaller device footprint, thinner bezel width, and less dead space. Second, transistors with sub-micron pitch are desired to bridge the pixel gap between smartphone displays and micro-displays, and to be used for consumer AR/VR displays with > 1000 ppi. Third, reduced device length is necessary for fine-grained integration with nanoscale CMOS. However, short-channel TFTs suffer from short-channel effects (SCE). For example, threshold voltage (Vt) roll-off, where the Vt reduces for short channel lengths, causes device variability and hence, worse process tolerance. Therefore understanding and control of SCE is critical for designing and fabricating short-channel TFTs.In this paper, we study the device scalability of short-channel IGZO TFTs down to 1μm. The electrical channel length (Leff) is not the same as the gate length (Lg), and is determined by the carrier profile at the gate edges. Leff ( = Lg - ΔL) is obtained by the transmission line method (TLM), or shift-and-ratio method. Accurate ΔL extraction is important in determining the exact device mobility. Since scalability is related to the carrier concentration profile, it is strongly dependent on the process, where oxygen and hydrogen content varies with process conditions, and profiles change during thermal treatments. Devices with higher carrier concentration generally result in larger ΔL and worse SCE. Device simulations using TCAD shows the dependence on overlap (Lov), slope of carrier Gaussian decay (Xc), channel carrier concentration (Nch) on the Leff and SCE. TCAD simulation results are matched with experimental measurements for verification of the simulation models and parameters used. We define a critical carrier concentration (Ncrit) which defines the Leff. Changing the carrier profile while maintaining Ncrit results in little difference in ΔL. For devices with an underlap, similar ΔL values result in similar SCE. However, for devices with an overlap, even with the similar ΔL values, SCE is more sensitive to carrier profile at the channel edges. This study shows that SCE may be controlled through shaping of the carrier concentration profile through optimization of the device structure and process conditions allowing fabrication of short-channel TFTs with good scalability.

Impact of Source-to-Gate and Drain-to-Gate Overlap Lengths on Performance of Inverted Staggered a-IGZO TFTs With an Etch Stopper

We report a comprehensive study on the impact of source-to-gate ( ${L}_{S}$ ) and drain-to-gate ( ${L}_{D}$ ) overlap lengths on the performance of amorphous indium–gallium–zinc–oxide (a-IGZO) thin-film transistors (TFTs) employing the inverted staggered structure with an etch stopper (ES). Although drain current ( ${I}_{D}$ ) is found to marginally decrease with increasing ${L}_{S}$ , it is found to considerably increase with ${L}_{D}$ . With the help of technology computer-aided design (TCAD) simulations, the increase in ${I}_{D}$ with ${L}_{D}$ is attributed to backchannel formation in the region beneath the drain, while the decrease in ${I}_{D}$ with increasing ${L}_{S}$ is attributed to the depletion of carriers from the backchannel in the region beneath the source. In addition, the threshold voltage ( ${V}_{TH}$ ) shifts negatively with increasing ${L}_{D}$ and drain voltage ( ${V}_{D}$ ). All these effects are more pronounced in short channel TFTs than long channel TFTs, which could be the origin of the anomalous dependence of ${V}_{TH}$ of the ES-type a-IGZO TFTs on channel length.

Submicrometer Top-Gate Self-Aligned a-IGZO TFTs by Substrate Conformal Imprint Lithography

Thin-film transistors (TFTs) are the fundamental building blocks of today's display industry. To achieve higher drive currents and device density, it is essential to scale down the channel lengths of TFTs. To be able to fabricate short-channel TFTs in large volumes is also equally important in order to realize lower fabrication costs and higher throughput. In this paper, we demonstrate the application of substrate conformal imprint lithography (SCIL) to pattern top-gate (TG) self-aligned (SA) amorphous indium gallium zinc oxide TFTs down to channel length LG = 450 nm with good device scaling properties resulting in average field-effect mobility (μFE) = ~10 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ·V <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> ·s <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> , V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = ~ 0.5 V, and subthreshold swing (SS) = ~0.3 V/decade. The device performance as a function of channel length outlines the importance of dopant diffusion control for realizing submicrometer SA TFTs. The results demonstrate the compatibility of SCIL-based large-area patterning for the realization of submicrometer TG SA TFTs with a potential for high throughput.

Nano-rheology printing of sub-0.2 μm channel length oxide thin-film transistors

Down-scaling of the channel length of a fully solution-processed oxide thin-film transistor (TFT) to the nanometer-scale is the key to accessing next-generation devices for Internet-of-Things technology. In this work, we report on the fabrication of an oxide TFT with a channel length of 160 nm, which is far less than those obtained by the current direct-printing techniques, by a newly developed nano-rheology printing (nRP) method. The device had an on/off current ratio, subthreshold voltage, hysteresis, and field-effect mobility of approximately 107, 1.7 V, 0 V, and 0.16 cm2 Vs−1, respectively. The key to achieving the sub-micron channel printed TFT is the introduction of a new amorphous La–Ru–O material, which exhibits relatively good conductivity and excellent nRP properties at the nanoscale, for source/drain electrode patterns. Such a short-channel TFT would never be achieved with conventional printing methods, and hence, this approach is highly important for accessing next-generation low-cost, large-area and environmentally friendly printed electronics.

(Invited) Channel Length Dependence of Mechanical Strain for Flexible (a-IGZO) TFT

We investigated the dependence of mechanical strain upon channel length, in flexible amorphous-indium-gallium-zinc-oxide (a-IGZO) thin-film transistors (TFTs) on 20 μm thick Polyimide substrate by using different radii cylinder. The negative shift of the transfer characteristic associated with strain decreases for increasing channel length (L) and is practically suppressed in devices with L=100 μm. Amorphous oxide semiconductor (AOS) based devices are the future of transparent and flexible displays because of many advantages such as low deposition temperature and low manufacturing [1]-[2]. Recently, flexible a-IGZO TFTs on plastic substrates have been enthusiastically studied because they have the advantage of being thinner, lighter, bendable, rollable, and unbreakable [3]-[4]. Fig. 1 (a)-(c) shows the effects of vertical mechanical bending on the electrical performance of the flexible TFTs up to 0.80% strain having the TFT channel width (W) = 50 μm and length (L) = 10, 50, and 100 μm, respectively. A distinct robust TFT performance is observed by long channel TFT (L = 100 μm) as compared to short channel TFT (L = 10 μm) under the same strain condition. All the TFTs exhibited a negative shift of VTH (V) after mechanical strain. Negative VTH (V) shift under mechanical strain is thought to generation of donor-like defects (ΔNGD) at the bending part of the TFT channel [5], which might be at the center part of the channel. This highly strained channel region might generate more defects, resulting in an increase of carrier concentration. It has been reported that long channel length TFTs are less sensitive against the generation of deep donor-like defects [6] which also support our experimental results. Therefore, the TFT with different channel lengths can have a different change in transfer curve. We also performed TCAD simulation to fit the data shown in Fig.1. Circles represent measurement data and solid lines TCAD fitting. In the TCAD simulation, we adopt density of states (DOS) parameters from Mehedi et al.[5]. We also found that the increment of defect states after different strain. These defects are mainly oxygen vacancies [5]-[8]. Therefore, it is confirmed by experimental results and TCAD simulation that the long channel TFTs are more robust and generation of oxygen vacancy might be the origin of the instability under mechanical bending strain. References S. Lee, J. Shin, and J. Jang, Adv. Funct. Mater., 27, 1604921 (2017).S. Lee, D. Jeong, A. Takagi, M. Mativenga, and J. Jang, Adv. Funct. Mater., 27, 1700437 (2017) .H. Nishide, and K. Oyaizu, Science, 319, 5864, PP. 737-738, (2008).M. Koo, K. I. Park, S.-H. Lee, M. Suh, D. Y. Jeon, J. W. Choi, K. Kang, and K. J. Lee, “Nano lett., 12, 9,(2011).M. M. Hasan, M. M. Billah, M. N. Naik, J.G. um and J. Jang, IEEE Electronic Device Letter, 38, 8, (2017).J. G. Um, M. Mativenga, P. Migliorato and J. Jang, App. Phys. Lett., 117, 23, (2015).M. M. Billah, M. M. Hasan and J. Jang, IEEE Electronic Device Letter, 38, 7, (2017).M. M. Hasan, M. M. Billah, and J. Jang, IEEE Electronic Device Letter, 39, 2, (2018). Figure 1

Variability in Output Characteristics of Single-Walled Carbon Nanotube Thin-Film Transistors

Single-walled carbon nanotube (CNT) based thin-film transistors (TFTs) are promising candidates for future electronic devices because of their excellent properties. However, device-to-device performance variability of TFTs can pose challenging problems, which is rooted in the randomness of CNT networks, the variation in individual CNT properties due to change in chirality, and the fabrication imperfections. This paper presents a systematic study of variability in I-V characteristics through a combination of experimental and theoretical analysis of the major sources that cause performance variation. The sources of variation including the percentage of metallic CNTs (m-CNTs), threshold voltage, CNT mean length, and CNT network density have been studied separately. The analysis shows that the presence of m-CNTs is a major source contributing to the performance variation for short channel TFTs, but its effect reduces for large channel length transistors. The threshold voltage is found to be the major source of variation for long channel TFTs. A better consistency in performance can be guaranteed for TFTs with larger channel area, which ensures a smaller variation in CNT network density and CNT mean length. These results provide key insights into the variability estimation of I-V characteristics of CNT-based devices, which is vital for reliability studies of CNT-TFTs based circuits for different electronic applications.

Direct patterning of silver electrodes with 2.4 μm channel length by piezoelectric inkjet printing

The control of channel length is of great significance in the fabrication of thin film transistors (TFTs) with high-speed operation. However, achieving short channel on untreated glass by traditional piezoelectric inkjet printing is problematic due to the impacting and rebounding behaviors of droplet impinging on solid surface. Here a novel method was proposed to obtain short channel length on untreated glass by taking advantage of the difference in the retraction velocities on both sides of an ink droplet. In addition, droplets contact mechanism was first introduced in our work to explain the formation of short channel in the printing process. Through printing droplets array with optimized drop space and adjusting appropriate printing parameters, a 2.4μm of channel length for TFT, to the best of our knowledge, which is the shortest channel on substrate without pre-patterning, was achieved using piezoelectric inkjet printing. This study sheds light on the fabrication of short channel TFT for large size and high-resolution displays using inkjet printing technology.

Coffee-Ring Defined Short Channels for Inkjet-Printed Metal Oxide Thin-Film Transistors.

Short-channel electronic devices several micrometers in length are difficult to implement by direct inkjet printing due to the limitation of position accuracy of the common inkjet printer system and the spread of functional ink on substrates. In this report, metal oxide thin-film transistors (TFTs) with channel lengths of 3.5 ± 0.7 μm were successfully fabricated with a common inkjet printer without any photolithography steps. Hydrophobic CYTOP coffee stripes, made by inkjet-printing and plasma-treating processes, were utilized to define the channel area of TFTs with channel lengths as short as ∼3.5 μm by dewetting the inks of the source/drain (S/D) precursors. Furthermore, by introduction of an ultrathin layer of PVA to modify the S/D surfaces, the spreading of precursor ink of the InOx semiconductor layer was well-controlled. The inkjet-printed short-channel TFTs exhibited a maximum mobility of 4.9 cm(2) V(-1) s(-1) and an on/off ratio of larger than 10(9). This approach of fabricating short-channel TFTs by inkjet printing will promote the large-area fabrication of short-channel TFTs in a cost-effective manner.

Understanding the dependence of the ohmic drain-source leakage current on gold deposition rate in top-contact pentacene-based thin film transistors

We studied the influence of the gold deposition rate on the drain-source leakage current of top-contact pentacene-based thin film transistors (TFTs) with different channel lengths. It is demonstrated that the anomalous leakage current which occurs only in short-channel TFTs monotonically increases with increasing the gold deposition rate. For TFTs with channel length of 30μm, we also investigated the dependence of the drain-source leakage current on the pentacene grain size as well as the gold deposition rate. It is shown that the pentacene grain size influences the leakage current only in the case if high gold deposition rate is employed, whereas the anomalous leakage current can be avoided by reducing the gold deposition rate. Finally, due to the observed ohmic character of the anomalous leakage current, we propose that the origin of the current can be attributed to parasitic leakage paths on the surface of the pentacene layers formed by the lateral diffusion of gold clusters from drain/source edges into the channel region during gold deposition. Based on this hypothesis, the observed dependence of the anomalous leakage current on the gold deposition rate can be well explained.

A Short-Channel TFT of Amorphous In–Ga–Zn–O Semiconductor Pixel Structure With Advanced Five-Mask Process

We propose a new five-mask etch-stopper amorphous In-Ga-Zn-O semiconductor pixel structure for a high-resolution advanced-high-performance in-plane-switching (AH-IPS) display device. A short-channel length (under 5 μm) thin-film transistor (TFT) was successfully fabricated using a selfaligned damage preventing layer. The linear field effect mobility of the 4-μm channel length TFT was 10.4 cm 2 /V · s. Using the proposed structure, we successfully fabricated a 9.7-in AH-IPS quad-extended graphics array liquid-crystal displays panel.

Effect of Grain Growth Control by Atmospheric Micro-Thermal- Plasma-Jet Crystallization of Amorphous Silicon Strips on TFT Characteristics

High performance thin film transistors (TFTs) are fabricated on quarts substrate based on zone-melting-recrystallization (ZMR) of amorphous silicon (a-Si) strips induced by micro-thermal-plasma- jet (µ-TPJ) irradiation. The grain boundaries (GBs) in strip pattern were almost excluded and most of the strips consist of ∑3 coincidence site lattices (CSLs) or in some cases single grains. Strip pattern was quite effective even in the case of short channel TFTs. N- and p-channel TFTs with typical field effect mobility (µFE ) of 380 and 140 cm2/Vs, respectively, are successfully fabricated with significantly reduced characteristics variability. These high µFE and low variation of threshold voltage (Vth ) by strip pattern showed significantly stable output characteristics regardless of the size of TFTs.

Thermoreflectance microscopy analysis on self-heating effect of short-channel amorphous In-Ga-Zn-O thin film transistors

Self-heating effect is recently considered to play an essential role in the degradation of amorphous oxide thin film transistors (TFTs). Previous thermal analysis on amorphous oxide TFTs based on conventional infrared thermography, however, had limitations in studying short-channel TFTs due to its low spatial-resolution. Here, we investigated self-heating effect of short-channel amorphous In-Ga-Zn-O TFTs by using high-resolution thermoreflectance microscopy. For the TFT with a channel length of 15 μm and a distance of 10.8 μm between source and drain electrodes on an etch stopper, the device temperature due to self-heating reached 70–80 °C, and local heating arose close to the center of the channel compared to the drain side in the literature. The channel length dependence of thermal distribution revealed that the asymmetry of local heating weakened with the decreasing channel length due to a heat dissipation by the source and drain electrodes. Transient thermal analysis under a bias stress unveiled that the maximum temperature as a function of stress time strongly depends on bias stress conditions. The temporal behavior of temperature is possibly attributed to the interaction between self-heating and local degradation.

Direct patterning of solution-processed organic thin-film transistor by selective control of solution wettability of polymer gate dielectric

A simple direct patterning method for solution-processable organic semiconductors (OSCs) is demonstrated. The solution-wettable and nonwettable regions of a polymer gate dielectric layer were selectively controlled by a short tetrafluoromethane gas plasma treatment, and we precisely patterned the OSC film in the desired channel region by lamination coating. The patterned OSC films represent polycrystalline structures consisting of crystalline domains varying from 30 to 60 μm, and the resulting short-channel thin-film transistor (TFT) showed a high mobility of up to 1.3 cm2/Vs, a large on/off ratio over 108, and a negligible hysteresis curve. The proposed method is scalable for patterning TFT arrays with large-area dimensions.

Characterization of Charge-Carrier Transport in Semicrystalline Polymers: Electronic Couplings, Site Energies, and Charge-Carrier Dynamics in Poly(bithiophene-alt-thienothiophene) [PBTTT

We establish a link between the microscopic ordering and the charge-transport parameters for a highly crystalline polymeric organic semiconductor, poly(2,5-bis(3-tetradecylthiophen-2-yl)thieno[3,2-b]thiophene) (PBTTT). We find that the nematic and dynamic order parameters of the conjugated backbones, as well as their separation, evolve linearly with temperature, while the side-chain dynamic order parameter and backbone paracrystallinity change abruptly upon the (also experimentally observed) melting of the side chains around 400 K. The distribution of site energies follows the behavior of the backbone paracrystallinity and can be treated as static on the time scale of a single-charge transfer reaction. On the contrary, the electronic couplings between adjacent backbones are insensitive to side-chain melting and vary on a much faster time scale. The hole mobility, calculated after time-averaging of the electronic couplings, reproduces well the value measured in a short-channel thin-film transistor. The results underline that to secure efficient charge transport in lamellar arrangements of conjugated polymers: (i) the electronic couplings should present high average values and fast dynamics, and (ii) the energetic disorder (paracrystallinity) should be small.

Flexible Active-Matrix Organic Light-Emitting Diode Display Using Air-Stable Organic Semiconductor of $\hbox{Dinaphtho}[\hbox{2}, \hbox{3}\hbox{-b}: \hbox{2}^{ \prime}, \hbox{3}^{\prime} \hbox{-f}]\hbox{thieno}[\hbox{3}, \hbox{2} \hbox{-b}] \hbox{-} \hbox{thiophene}$

We developed a flexible active-matrix (AM) organic light-emitting diode (OLED) display driven by an organic thin-film transistor (TFT) (OTFT) using an air-stable organic semiconductor (OSC) of dinaphtho[2, 3 -b:2', 3' -f]thieno[ 3, 2 -b]-thiophene (DNTT) for the first time. We employed a low-temperature cross-linkable olefin-type polymer as the gate insulator (GI) and investigated the properties of the interface between DNTT and polymer GI. The top-contact TFT demonstrated a high mobility of up to 0.8 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s and a near-zero turn-on voltage. DNTT has a deeper highest occupied molecular orbital level than other OSC materials, and this leads to large contact resistance between the source/drain (S/D) contact and OSC. Surface modifications to the S/D contact were investigated to enable efficient carrier injection to fabricate high-performance bottom-contact TFTs. The short-channel TFT we fabricated exhibited a high hole mobility of 0.5 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V·s, a low subthreshold slope of 0.31, and excellent environmental and operational stability. The DNTT-based TFT also demonstrated good applications to processes with less deterioration. Finally, a 5-in flexible OLED display was successively fabricated by integrating the AM backplane with a phosphorescent OLED device. A high luminescence over 300 cd/ m <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> was achieved by driving the DNTT-based OTFTs.

Effect of Dynamic Bias Stress in Short-Channel (L=1.5 µm) p-Type Polycrystalline Silicon Thin-Film Transistors

We have investigated the stability of short-channel (1.5 µm) p-type polycrystalline silicon (poly-Si) thin film transistors (TFTs) under AC bias stress. The threshold voltage of the short-channel (L=1.5 µm) poly-Si TFT was increased by about -7.44 V after AC bias stress, whereas the threshold voltage of the long-channel poly-Si TFT was relatively stable. A two-step degradation process was also observed. In the first step, the threshold voltage of short-channel poly-Si TFTs underwent a consistent positive shift for 100 s. In contrast, the threshold voltage started to undergo a negative shift when accompanied by significant degradation in the subthreshold region. This negative shift of threshold voltage and the significantly degraded subthreshold swing value in the short-channel TFT under dynamic stress may be mainly due to the generation of stress-induced deep- and shallow-level trapping states near the drain junction.