Short-channel MOSFETs Research Articles

Dimension Dependence of Unusual HCI-Induced Degradation on N-Channel High-Voltage DEMOSFET

According to reliability models, a short-channel MOSFET is susceptible to the device characteristics degradation due to the hot carrier injection (HCI) effect. In this paper, we describe an anomalous degradation behavior that is opposite to the general understandings on the n-channel high-voltage drain-extended MOSFETs. The experimental data indicate that the threshold voltage (Vth) degrades much worse in a longchannel device than in a short-channel one during the HCI stress. In addition, a narrow device shows more Vth shifts than a wide one does. These phenomena showing the dimension dependence on the channel length (Lch) and channel width (W) can be attributed to the alleviation of the Kirk's effect and the STI-enhanced residual mechanical stress. An injection efficiency in the form of the normalized gate-to-drain current (Igs/Ids) is successfully introduced to project the dimension-dependent Vth shift. The kinetic equation of trap formation is involved in the numerical simulation for giving a comprehensive interpretation on the degradation mechanism.

On-current modeling of short-channel double-gate (DG) MOSFETs with a vertical Gaussian-like doping profile

An analytic drain current model is presented for doped short-channel double-gate MOSFETs with a Gaussian-like doping profile in the vertical direction of the channel. The present model is valid in linear and saturation regions of device operation. The drain current variation with various device parameters has been demonstrated. The model is made more physical by incorporating the channel length modulation effect. Parameters like transconductance and drain conductance that are important in assessing the analog performance of the device have also been formulated. The model results are validated by numerical simulation results obtained by using the commercially available ATLAS™, a two dimensional device simulator from SILVACO.

A Junctionless Gate-All-Around Silicon Nanowire FET of High Linearity and Its Potential Applications

The linearity of a gate-all-around junctionless silicon nanowire (SiNW) FET has been analyzed. The SiNW FET shows a perfectly linear <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$I_{D}$</tex></formula> – <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$V_{G}$</tex></formula> relation and a nearly zero output conductance. The mechanism of its linear behaviors due to degenerate doping level has been also demonstrated. For RF applications, the proposed SiNW FET exhibits a much lower distortion for a whole range of load resistance, making it superior to modern short-channel MOSFET.

Threshold voltage, and 2D potential modeling within short-channel junctionless DG MOSFETs in subthreshold region

This report focuses on the development of an analytical two-dimensional model to calculate the potential within ultra-scaled junctionless double-gate MOSFETs (DG MOSFETs), which is valid in the subthreshold regime. From that we derive an expression for calculating the threshold voltage of such devices, and present our first results. Compared to conventional MOSFETs, the proposed junctionless transistor has no pn-junctions. Its type of doping in the channel region is the same as in the source/drain regions. The device is turned on by creating a conducting channel in the center of the silicon film, and turned off by depleting it. To achieve good Ion/Ioff ratios, and to ensure a safe switching behavior, the investigation of the subthreshold region is therefore important. The analytical model is compared with numerical simulation results from TCAD Sentaurus. Its validity is confirmed for long-channel, as well as for ultra-scaled devices having a channel length about 22nm. Since the junctionless device is still in its infancy, an analytical model, especially for short-channel devices, can provide help to understand its electrostatic characteristics.

(Invited) FinFET and UTB--How to Make Very Short Channel MOSFETs

New materials with enhanced mobility are clearly going to be important to the IC industry. In addition, the leakage current in future short gate transistors must be suppressed somehow. FinFET was developed for this goal. Its fin shape or its 3D nature is not the reason for its ability to suppress the leakage current. A 2D planar short gate structure, Ultra-Thin-Body (UTB), was proposed and demonstrated at the same time as FinFET. Together they illustrate a new scaling principle. Future monolayer semiconductor transistors are naturally UTB and highly scalable.

Anew Square-Root Circuit Using Short Channel MOSFETs with Compensation for Error Resulting from Carrier Mobility Reduction

Anew Square-Root Circuit Using Short Channel MOSFETs with Compensation for Error Resulting from Carrier Mobility Reduction

Modeling of Short Channel MOSFET Devices and Analysis of Design Aspects for Power Optimisation

 Abstract—The advancement in silicon material processes technology in the manufacture of 45nm MOSFET has extended Moore's Law for some more years. Low power CMOS circuit design has become a challenge due to variations in design parameters caused as a result of short channel effects at deep submicron levels for technology nodes below 1µm. In this paper, we have analyzed the design aspects for short channel devices by method of transistor modeling and further simulations have been carried out using Virtuoso cadence Simulator. The technology nodes considered here are 180nm and 45nm technology since fabrication of 180nm uses conventional process technology and 45nm uses new innovations in process technology. The aim of this paper is to bring out parameter variability issues related to different process technologies and find solutions for power optimization at design level for CMOS circuits.

A comprehensive study of channel hot-carrier degradation in short channel MOSFETs with high-k dielectrics

This paper presents a comprehensive study on channel hot-carrier (CHC) degradation in short channel MOSFETs with high-k dielectric. Different reliability scenarios are analyzed, i.e., temperature influence, impact of high ID and dynamic operation conditions. To explain the CHC damage behavior in short channel devices, we divide the total CHC degradation in two components: the classical CHC damage located at drain side and the degradation produced by the voltage drop over the gate dielectric, which can be considered as bias temperature instability (BTI).

High-Performance Flexible Thin-Film Transistors Exfoliated from Bulk Wafer

Mechanically flexible integrated circuits (ICs) have gained increasing attention in recent years with emerging markets in portable electronics. Although a number of thin-film-transistor (TFT) IC solutions have been reported, challenges still remain for the fabrication of inexpensive, high-performance flexible devices. We report a simple and straightforward solution: mechanically exfoliating a thin Si film containing ICs. Transistors and circuits can be prefabricated on bulk silicon wafer with the conventional complementary metal-oxide-semiconductor (CMOS) process flow without additional temperature or process limitations. The short channel MOSFETs exhibit similar electrical performance before and after exfoliation. This exfoliation process also provides a fast and economical approach to producing thinned silicon wafers, which is a key enabler for three-dimensional (3D) silicon integration based on Through Silicon Vias (TSVs).

Second-stage tuning procedure for analogue CMOS design reuse methodology

Proposed is a two-stage analogue circuit design reuse methodology by extending existing fabrication process rescaling procedures with a follow-on systematic tuning procedure stage based on DC output voltage scaling. It increases the potential for design reuse with short-channel MOSFET circuit designs when compared to the current single-stage rescaling work. Two Miller amplifier circuits were designed in 0.18 and 0.13 µm CMOS processes in order to analyse circuit performance achieved with the proposed method compared to the existing methods. The additional tuning stage results in an improved amplifier gain up to 16 dB and up to 2.5 times faster settling time compared to single-stage scaling with 33% power reduction and 28% smaller silicon area when compared to the original design.

Work Function Engineering With Linearly Graded Binary Metal Alloy Gate Electrode for Short-Channel SOI MOSFET

Over the last few decades, silicon-on-insulator (SOI) technology has been identified as one possible solution for enhancing the performance of CMOS because of its numerous advantages over conventional bulk CMOS technology. One of the primary drawbacks of short-channel SOI MOSFET is the degradation of device threshold voltage with decreasing channel length. Drain-induced barrier-lowering (DIBL) effect, generated from high drain bias, is the main cause behind this length-dependent nature of threshold voltage. This “instability” in threshold voltage is responsible for making SOI device design very challenging. The instability that is known as the threshold voltage rolloff restricts further scaling of SOI devices. In this paper, an idea of work function engineering with continuous horizontal mole fraction variation in a binary alloy gate has been proposed and implemented theoretically. Analytical model-based simulation verified that performance of proposed SOI MOSFET is improved as it has higher immunity to DIBL effect.

Impact of NiPt Thickness Scaling on Contact Resistance From Thin-Body FD SOI to Trigate FETs

The impact of NiPt thickness scaling on total resistance is investigated using short-channel <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$(L_{g} = \hbox{40}\ \hbox{nm})$</tex></formula> nm high- k metal-gate complementary SOI MOSFETs with fin widths varying from 500 nm (“planar single-gate thin-body FD SOI FET”) to 25 nm (trigate FET). It is shown that limiting the amount of NiPt available for silicidation becomes increasingly critical as fin width scales due to a reduced silicide-to-silicon interfacial contact area and facilitated silicide encroachment toward the channel. The prevention of Schottky contact by scaling NiPt thickness from 10 to 5 nm on a 20-nm-thick SOI enabled a <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex Notation="TeX">$ &gt; \hbox{2}\times$</tex></formula> (NFET) and <formula formulatype="inline" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex Notation="TeX">$ &gt; \hbox{6}\times$</tex></formula> (PFET) reduction in total resistance along with swing and DIBL improvements on trigate FETs.

A study on the performance of metal-oxide-semiconductor-field-effect-transistors with asymmetric junction doping structure

Diode currents of MOSFET were studied and characterized in detail for the ion implanted pn junction of short channel MOSFETs with shallow drain junction doping structure. The diode current in MOSFET junctions was analyzed on the point of view of the gate-induced-drain leakage (GIDL) current. We could found the GIDL current is generated by the band-to-band tunneling (BTBT) of electrons through the reverse biased channel-to-drain junction and had good agreement with BTBT equation. The effect of the lateral electric field on the GIDL current according to the body bias voltage is characterized and discussed. We measured the electrical doping profiling of MOSFETs with a short gate length, ultra thin oxide thickness and asymmetric doped drain structure and checked the profile had good agreement with simulation result. An accurate effective mobility of an asymmetric source–drain junction transistor was successfully extracted by using the split C–V technique.

On the Interpretation of Ballistic Injection Velocity in Deeply Scaled MOSFETs

The ballistic injection velocity is examined in state-of-the-art Si extremely thin SOI MOSFETs using ballistic quantum simulations and a virtual source (VS) compact model. The results indicate that the device performs at around 50%-60% of its ballistic limit and that the ballistic injection velocity at the top of the potential barrier (ToB), as obtained by numerical simulation, can be significantly lower than its counterpart extracted at the VS. This occurs because, at high drain bias, the ToB moves under the influence of gate bias toward the source contact, where additional mobile charge resides that are not directly induced by the gate contact but by the source contact. This effect becomes increasingly important as channel length shrinks and is affected by several factors, including the details of the source design. The accurate estimation of a physically meaning “injection velocity” under ballistic limit could be therefore very difficult in very short channel MOSFETs.

Analytical modeling of subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs

An analytical model for subthreshold current and subthreshold swing of short-channel triple-material double-gate (TM-DG) MOSFETs is presented in this paper. Both the drift and diffusion components of current densities are considered for the modeling of subthreshold current. Virtual cathode concept of DG MOSFETs is utilized to model the subthreshold swing of TM-DG MOSFETs. The effect of different length ratios of the three channel regions under three different gate materials of device on the subthreshold current and subthreshold swing of the short-channel TM-DG MOSFETs have been discussed. The dependencies of subthreshold current and subthreshold swing on various device parameters have been studied. The simulation data obtained by using the commercially available 2D device simulation software ATLAS™ has been used to validate the present model.

$\hbox{MOS}^{3}$: A New Physics-Based Explicit Compact Model for Lightly Doped Short-Channel Triple-Gate SOI MOSFETs

In this paper, we present a new compact drain-current model for double-gate or triple-gate silicon on insulator (SOI) metal-oxide-semiconductor field-effect transistors, which is based on a physics-based 3-D analysis. Explicit analytical model equations for the height of the potential barrier are derived in closed form from a 3-D model for the channel electrostatics without the need to introduce any fitting parameter. The device current is described by a superposition of a surface-channel current above threshold and a center current in the subthreshold region, accounting for the movement of the most leaky path in the device cross section. Comparison with Technology Computer Aided Design (TCAD) shows a good scalability of the model down to a gate length of 30 nm. Furthermore, the I-V characteristics are compared with measurements and obtain accurate results down to an effective channel length of 53 nm.

Symmetrical unified compact model of short-channel double-gate MOSFETs

An explicit charge-based unified compact drain current model for lightly doped or undoped DG MOSFETs is proposed. It takes into account the short-channel effects, the subthreshold slope degradation, the drain-induced barrier lowering and the channel length modulation effects. The model is valid and continuous in all regimes of operation and it has been validated by developing a Verilog-A code and comparing the model results of transfer and output characteristics with simulation results exhibiting an average error of about 3%. The efficient solution of the Lambert W function for the inversion charge and the symmetry of the model make it suitable for circuit simulation and allow fast and accurate simulations of the transistor characteristics.

A new field dependent mobility model for high frequency channel thermal noise of deep submicron RFCMOS

In this paper, a new field dependent effective mobility model including the drain-induced vertical field effect (DIVF) is presented to calculate the channel thermal noise of short channel MOSFETs operating at high frequencies. Based on the new channel thermal noise model, the simulated channel thermal noise spectral densities have been compared to the channel thermal noise directly extracted from noise measurements on devices fabricated using GLOBALFOUNDRIES’ 0.13 μm RFCMOS technology. The comparison has been done across different channel length, finger width and number of finger for different frequencies, gate biases and drain biases. Excellent agreement between simulated and extracted noise data has shown that the proposed model is scalable over different dimensions and operating conditions. The proposed model is simple and can be easily implemented in a circuit simulation environment.

A novel surface potential-based short channel MOSFET model for circuit simulation

In this paper a novel analytical approximation method for surface potential (ψs) calculation in compact MOSFET model is presented. It achieves excellent accuracy and good calculation speed over all regions from accumulation to strong inversion. With this approximation method, a surface potential-based compact model for short channel MOSFET is developed. Comparison with measured data is also presented to validate the new model.

Investigation of the Potential Barrier Lowering for Quasi-ballistic Transport in Short Channel MOSFETs

Investigation of the Potential Barrier Lowering for Quasi-ballistic Transport in Short Channel MOSFETs