Turn-on Voltage Shift Research Articles

Evaluation of Device Charging in Ion Implantation

Device charging in the ion implantation is evaluated by using two different types of electrically erasable-programmable read-only memory (EEPROM) devices and two different types of metal-oxide-semiconductor (MOS) capacitors. The averaged charging voltage is measured by the turn-on voltage shift (ΔVT) of a grounded source EEPROM, while the transient charging effect is detected by a floating source EEPROM. The yield of the MOS capacitor reaches its maximum when the grounded source EEPROM shows the minimum ΔVT. The effects of the charge-collecting electrode area and substrate type of the MOS capacitor are also examined.

Drain-voltage dependence of IGFET turn-on voltage

The turn-on voltage (or threshold voltage) characteristic of an enhancement-type insulated-gate field-effect transistor (IGFET) in its pentode operation region, is analyzed based on a simple model. A new definition for the turn-on voltage at just-saturated state is given and a new simple formula for the turn-on voltage shift in IGFETs pentode operation region, is deduced. This assumes a reduction of gate-induced bulk charge under the influence of the drain voltage. Agreement of the theory with experiment is good.

Temperature dependence of turn-on voltage of gold-doped MOSFETs

The temperature dependence of the turn-on voltage of gold-doped and control n- and p-channel MOSFETs has been measured. To account for the large positive shift of turn-on voltage, V T Au , of gold treated n- and p-channel devices, it has been proposed that the gold eliminates the fast interface traps of continuous energy distribution, and that additional acceptor states very close to the valence band can cause additional charge Q A Au , which can dominate the effect of acceptor and donor levels of gold ions in the silicon surface space charge region, and can also over-compensate the surface state charge, Q ss . To fit the theoretical V T Au versus T curve to experimental curves, an accumulation of electrically active gold within the surface space charge region has been considered in n-channel devices and depletion in p-channel devices.

Metal-nitride-oxide-silicon field-effect transistors, with self-aligned gates

Silicon insulated-gate field-effect transistors (FETs) have been fabricated by processes involving relatively non-critical photoresist and self-limiting etching steps. Important features of the method include the formation of the gate insulator under extremely clean conditions, incorporation of an alkali ion barrier (silicon nitride) to achieve stable device characteristics and automatic alignment of the gate electrode with respect to source and drain. The gate insulator, comprising 600 Å of grown silicon dioxide covered with 400 Å of silicon nitride, is formed at the beginning of fabrication. Thus, the SiSiO 2 interface is established at a point where the best state-of-the-art cleaning techniques can be applied to the starting material. A thick (8000 Å) layer of SiO 2 is pyrolytically deposited over the nitride to minimize contact capacitances in the finished structure. This must be removed from the active device region, and advantage is taken of the difference in etch rate between SiO 2 and silicon nitride to ensure a well-controlled gate insulator thickness. Thus the nitride layer serves the dual function of providing a barrier to mobile ions in the completed structure, and of acting as an etch-resistant layer during fabrication to achieve control over geometry. A polycrystalline layer of silicon is used to form the gate electrode, which is shaped early in the process, and is used to define the limits of the source and drain windows. This aspect of the fabrication assures self-alignment of the gate electrode with respect to source and drain. During the diffusion of source and drain regions the polycrystalline silicon is rendered sufficiently conductive that no metallization of the gate electrode is required, except at one end for contacting purposes. This eliminates the need for a critical photoresist alignment. Both n and p induced-channel (enhancement) devices have been made with this process. Turn-on voltages at 10 μA drain current of +1.35 V ( n-channel) and −2.6 V ( p-channel) with less than 12 per cent spread over a slice were obtained. Analysis of the device characteristics indicates field-effect mobilities of 335 and 233 cm 2/V-sec for the n- and p-channel devices respectively. Aging behavior under bias at 300°C indicates the presence of residual mobile positive charge of the order of 1.5 × 10 11 charges/cm 2, resulting in turn-on voltage shifts of less than 1 V over several hundred hr with +10 V applied to the gate.

A model for shifts in the gate turn-on voltage of insulated-gate field-effect devices induced by ionizing radiation

Insulated gate field-effect devices with thermally grown silicon dioxide and deposited nitride insulation were subjected to electron irradiation up to a total dose of sufficient magnitude to establish dynamic equilibrium. The resultant linear shift of the gate turn-on voltage with applied gate bias over a wide range of biasing conditions has been interpreted by a model postulating a positive space charge region bounded by the insulator-semiconductor interface and a negative space charge region bounded by the insulator-metal interface. It is shown that the linearity holds for an arbitrary space charge distribution within these two regions whose widths are independent of the gate voltage during irradiation. The conditions for obtaining completely radiation-resistant devices have also been derived.

Comparison of MOS and Metal-Nitride-Semiconductor Insulated Gate Field-Effect Transistors under Electron Irradiation

Insulated gate field-effect transistors with silicon dioxide and silicon nitride insulationwere irradiated with 1 MeV electrons over a wide range of biasing conditions. In nitride insulated devices the radiation induced shift in gate turn-onvoltage was greatly reduced and source-drain leakage currents eliminated. The dependence of the equilibrium shift in gate turn-on voltage on gate bias varied critically with the structure of the insulating layer, and an attempt has been made to correlate this with charge transfer mechanisms across the interfaces of the insulator.

Complementary MOS transistors

The design, fabrication and evaluation of complementary n− and p-channel MOS transistors with enhancement-mode characteristics (i.e. normally off) are discussed in terms of their process technology. These structures are fabricated simultaneously on an epitaxial silicon layer, grown upon a (111) substrate, with threshold voltages of V TN = +1.5 V and V TP = −4.1 V for the same oxide thickness of t ox = 1000 A ̊ . The theoretical CV curves for the MOS system are used to evaluate the various fabrication processes such as, the chemical treatments, high temperature gas treatments, evaporation systems, etc. resulting in a reproducible surface state density of N ss = 7.0 × 10 11 / cm 2. The temperature-bias stability is discussed in terms of the shift in turn-on voltage V GSt and the use of a phosphorus-glass results in ΔV GSt of less than 50 mV for field strengths of 2 × 10 6 V/cm at a temperature of 150°C. Excessive phosphorus-glass results in a polarization of the gate dielectric. The electrical characteristics of the complementary MOST's are presented and discussed.