Chemical Mechanical Planarization (CMP) is a critical process in semiconductor manufacturing used to achieve nanoscale planarity in integrated circuits. Traditionally, CeO2-based slurries are used for Shallow Trench Isolation (STI) CMP, largely due to the Ce³⁺/Ce⁴⁺ redox couple that plays a key role in facilitating tetraethyl orthosilicate (TEOS) material removal while mitigating primary surface defectivity (i.e., scratching, dishing, erosion). However, post-polish residual CeO2 nanoparticles contribute to secondary defects (e.g.., surface residue, scratching), necessitating enhanced cleaning strategies. Previous work suggests that amino alcohols enhance post-CMP cleaning processes through modulating CeO2 surface interactions and subsequently improving post-polishing CeO2 particle removal. Based upon these results, this work investigates the incorporation of amino alcohols into CeO2-based slurries, focusing on their influence on polishing efficiency, surface defectivity, and electrochemical behavior at the slurry-substrate interface. Electrochemical impedance spectroscopy (EIS) and cyclic voltammetry (CV) were used to analyze interfacial charge transfer dynamics, changes in CeO2 redox activity, and adsorption effects, providing mechanistic insight into the additives’ impact on CeO2 properties. Zeta potential and particle size measurements offered insight into how amino alcohols alter the interfacial electrochemical properties of CeO2 nanoparticles and their impact on slurry stability and particle-substrate adhesion. Additionally, previous studies have shown that the integration of megasonic energy improves both CeO2 post-CMP cleaning performance and STI CMP polishing performance by promoting localized redox activity. Megasonic energy was applied to evaluate its effects on surface reactions driven by redox processes. It works synergistically with amino alcohols to help reduce the adhesion of CeO2 particles, break up nanoparticle agglomerates, and enhance control over defects. Surface characterization techniques, including defect imaging and surface wettability analysis, was done to further quantify changes in particle adhesion and interfacial chemistry.

Chemical mechanical planarization (CMP) is an indispensable technique for achieving global planarization in shallow trench isolation (STI) structures, a critical component in modern integrated circuits. With the continuous advancement of technology and increasing demands for chip performance, the critical metrics of STI CMP processes have become increasingly stringent, placing higher requirements on the performance of polishing slurries. In particular, SiO2/Si3N4 removal rate selectivity (RRS) and surface flatness directly impact product quality and yield. In this study, we present a supramolecular strategy for tailoring ceria (CeO2) surfaces to enhance CMP performance, especially SiO2/Si3N4 removal rate selectivity (RRS) and surface flatness. Specifically, we functionalized CeO2 nanoparticles with β-cyclodextrin (β-CD), a macrocyclic supramolecular host, to modulate surface properties. This modification not only improves the colloidal stability of the resulting CeO2 slurries but also endows them with three key advantages: (1) elevated material removal rate (MRR), (2) outstanding post-polishing surface quality, and (3) significantly enhanced SiO2/Si3N4 RRS. Furthermore, the β-CD-modified CeO2 surface serves as a versatile platform for secondary functionalization with small molecules. By incorporating glutamic acid as a co-modifier, we demonstrate synergistic improvement in SiO2/Si3N4 RRS, highlighting the cooperative effects between supramolecular and molecular additives. This work establishes a facile supramolecular approach to engineer high-performance CeO2-based CMP slurries for STI applications. More broadly, it validates the potential of hybrid modification strategies-combining macrocyclic hosts with small-molecule guests-to precisely tune abrasive/surface interactions and advance CMP technology.

Effective post-CMP (p-CMP) cleaning is essential for minimizing surface defects and ensuring the reliability of semiconductor devices. In Shallow Trench Isolation (STI) processes, cerium dioxide (CeO₂) nanoparticles, commonly used in slurries for oxide CMP, adhere to oxide surfaces via Ce–O–Si bonds, complicating their removal and increasing the risk of defects. This study investigates the application of megasonic energy through the Flucto-Clean® system to activate cleaning chemistries delivered to a polyvinyl alcohol (PVA) contact cleaning brush, thereby enhancing CeO₂ particle removal while mitigating surface roughness, subsurface damage, and secondary defect formation (e.g., scratching, and pitting). The Flucto-Clean® system employs megasonic energy to generate cavitation phenomena within the cleaning solution, producing localized pressure that enhances chemical reactivity. Such a cavitation effect generates reactive oxygen species (ROS) which modulate ceria surface chemistry to weaken Ce–O–Si bonds. ROS-induced redox cycling shifts ceria oxidation states from Ce⁴⁺ to Ce³⁺, creating oxygen vacancies that facilitate enhanced particle removal efficiency (PRE >92% at 60W). Unlike traditional methods relying on mechanical force, this approach reduces the shear force required for cleaning, minimizing friction-induced defects. Oxidation-reduction potential (ORP) measurements confirm the creation of a highly-reactive cleaning environment under megasonic activation. Cyclic voltammetry highlights changes in charge transfer dynamics, demonstrating the pivotal role of ROS in modifying particle-surface interactions. Surface characterization techniques, including atomic force microscopy (AFM) and multi-channel optical scans, reveal significantly reduced defectivity and surface roughness compared to conventional cleaning approaches. These findings establish megasonic-activated cleaning as a highly effective strategy for achieving defect-free oxide surfaces during STI p-CMP cleaning, leveraging the synergistic effects of ROS activity and reduced mechanical force to optimize cleaning performance.

To continue the extension of Moore’s Law, precise control over critical semiconductor processing steps such as Chemical Mechanical Planarization (CMP), particularly in Shallow Trench Isolation (STI), becomes increasingly crucial. The effectiveness of STI CMP relies on the redox activity at the surface of ceria (CeO₂) nanoparticles. It is widely reported that CeO₂ nanoparticles are uniquely suited for STI CMP due to the surface oxidation states (Ce³⁺/Ce⁴⁺), enabling efficient oxide removal but requiring careful modulation to optimize polishing performance. This work investigates the activation of ceria-based slurries under megasonic energy (i.e., Flucto-CMP®) to enhance oxide CMP, specifically through improved redox cycling. Megasonic-induced cavitation phenomena at the particle-substrate interface drive localized pressure and temperature fluctuations that amplify redox activity and promote the generation of reactive oxygen species (ROS). These effects accelerate electron transfer processes, facilitating dynamic redox cycling between Ce³⁺ and Ce⁴⁺ oxidation states, which enhance material removal rates and mitigate defect formation (i.e., scratching, pitting, dishing, etc.). Electrochemical characterization, including cyclic voltammetry (CV), demonstrates that megasonic activation significantly enhances charge transfer at the interface, correlating with increased material removal (+30%). These findings correlate with oxidation-reduction potential (ORP) values, which suggest a more reductive environment conducive to efficient polishing performance. Surface analysis techniques such as atomic force microscopy (AFM) and multi-channel (polarization, reflectivity, surface slope, and dark field) scans of oxide surfaces reveal reduced surface roughness, minimized subsurface damage, and lower nanoparticle residue defects following megasonic-activated polishing. This work highlights the synergistic effects of Flucto-CMP® cavitation-induced ROS generation and redox modulation on STI CMP performance.

A common dielectric material utilized in Shallow Trench Isolation (STI) is tetraethyl orthosilicate (TEOS), which is polished utilizing Ceria (CeO2) nanoparticles. While CeO2 is efficient in polishing TEOS due to its ability to form strong Ce-O-Si bonds, the nanoparticle is prone to remain on the surface as a nanoparticle residue. Traditional post-Chemical Mechanical Planarization (p-CMP) cleaning utilizes a polyvinyl alcohol (PVA) brush to remove residues; however, it can generate various secondary defects (i.e., scratching, pitting) because of the stress placed at the brush-wafer interfaces. To minimize defectivity, a low-stress process has become attractive to remove residues via Megasonic cavitation. Previous research has shown the effective cleavage of the Ce-O-Si bond that leads to enhanced nanoparticle removal. Albeit this has not been mechanistically evaluated to determine the degree of aggregation of the CeO2 nanoparticles as a function of applied energy. Previous work has shown an alteration in the “Ce3+/Ce4+” charge state of the nanoparticle surface in the cleaning waste effluent, which can be correlated to an increase in particle removal efficiency (PRE). However, little emphasis has been placed on how the surface redox state changes under varying megasonic conditions (i.e., wattage, frequency). This work will also focus on how the introduction of redox-active additives (i.e. amino alcohols) could lead to an alteration of particle removal. Initial results show an increase in PRE with increasing wattage, though with diminishing returns at the highest wattages. Further analysis was done to compare the behavior of calcined and colloidal ceria nanoparticle dispersions under megasonic cleaning conditions.

This article presents a new global shutter (GS) pixel design with radiation-hardened-by-design (RHBD) device modifications and correlated double sampling (CDS). Global shutter imagers present undeniable advantages by exposing all pixels simultaneously. Once in-pixel storage is included, the pixel readout can be operated simultaneously with exposure, enabling faster operation and flashed light. Additionally, this architecture is robust against motion defects and easy to operate in synchronous mode. The radiation tolerance of the outlined pixel is targeted up to 1 MGy SiO2 total ionizing dose (TID). A partially pinned photodiode (pPPD) structure, combined with an enclosed transistor layout known as a “butterfly” [1,2] is used to withstand such a high TID value. The use of the p+ implant on top of the photodiode and recessed shallow trench isolation (STI) reduce the dark current from the TID-induced interface traps and SiO2 interface while also shielding the photodiode (PD) region from TID-induced positive charges in the SiO2. CDS [3] is required to reduce the read noise by suppressing important noise sources such as photon shot noise, thermal noise (kTC) and flicker noise contributions. Two in-pixel storage capacitors and two readout paths are implemented to allow CDS. The pixel operation includes a sample phase where the pixel signal is locally stored followed by a reset phase and the pixel reset is stored. The in-pixel storage is designed with enclosed butterfly MOS devices that allow great charge density for low area and with limited leakage due to the RHBD design. The readout is performed by operating two output source followers (SF) and two output buses. The pixel is designed using 180 nm CMOS Image Sensor (CIS) technology. It achieves a pre-rad dynamic range of 60.9 dB and a shutter efficiency of 99,6%.

With the continuous scaling of CMOS technology, stress engineering has become increasingly critical at advanced technology nodes, especially in tall and narrow FinFET structures. Asymmetric layout environments (such as dual-Fin structures or poly cuts) can introduce stress imbalance originating from shallow trench isolation (STI), which in turn affects device performance. In this study, TCAD simulations were performed on n-type FinFETs representative of the 10 nm technology node, with a physical gate length of 20 nm, to investigate the correlation between asymmetric stress and device drive current. As the Fin width decreases, the asymmetric stress from STI induces noticeable performance fluctuations, with the mobility enhancement under saturation bias reaching a maximum of 8.42% at W = 6 nm. Similarly, as the Fin body angle deviates from 90° and the Fin top narrows, with Wtop = 6 nm and Wbottom = 8 nm, the mobility enhancement peaks at 7.65%. The simulation results confirm that STI-induced asymmetric stress has a significant impact on the Fin sidewall channel, while its effect on the top channel is minimal. To mitigate these effects, CESL stress engineering is proposed as an effective solution to amplify the top channel current, thereby reducing the influence of asymmetric stress on device performance. A CESL stress of 2.0 GPa is shown to improve device stability by approximately 20%.

Abstract The shallow trench isolation chemical mechanical polishing (STI CMP) technique is critical to ensure the flatness of the isolation layer and the merit of the device performance. The need for a moderate and adjustable silicon oxide and silicon nitride removal rate selectivity ratio to avoid deep oxide dishing pits and severe silicon nitride loss in polishing remains a challenge. Regarding the difficulty in regulating the selectivity ratio of the removal rate (RR) of SiO2 and Si3N4 in STI CMP, this paper innovatively employs L-isoleucine as an inhibitor, achieving a moderately adjustable selectivity ratio in the nano-CeO2 abrasive system. The RRs of SiO2 and Si3N4 were respectively reduced to 238 and 11 nm/min, with a selectivity ratio of 21.6, and the surface roughness (Sq) was decreased to 0.32 and 0.19 nm, respectively. Coefficient of friction , X-ray photoelectron spectroscopy, and theoretical calculations indicated that the L-isoleucine molecule can adsorb on the surface of SiO2 and Si3N4 wafers to form a passivation layer, while also adsorbing on the surface of CeO2 abrasive to retard the wear effect.

Effect of picolinic acid and sorbitol in ceria-based slurry on shallow trench isolation chemical mechanical polishing

Abstract Advanced 10 nm device delayering is a critical process for verifying and validating the circuit design layout and extracting the structures buried inside the chip. The work featured in this article takes advantage of chemically assisted focused ion beam processing with ultraviolet spectroscopy to destructively delayer integrated circuits starting from the shallow trench isolation layer, enabling high-resolution SEM imaging at each layer.

Complementary metal oxide semiconductor (CMOS) image sensors have become increasingly widely used in the field of radiation environments due to their numerous advantages, and their radiation effects have also attracted much attention. Some experimental studies have shown a decrease in the saturation output of CMOS image sensors after irradiation, while others have reported an increase. This article conducts further in-depth research on the inconsistent result based on proton irradiation experiments and TCAD simulations, analyzing the degradation mechanism in full well capacity (FWC), conversion factor (CVF), and saturation output of the 4T pinned photodiode (PPD) CMOS image sensors due to proton cumulative radiation effects. In experiments, the sensors are irradiated by 12 MeV and 60 MeV protons with a fluence up to 2×10<sup>12</sup> p/cm<sup>2</sup>. The sensors are unbiased during irradiation. The experimental results show that proton irradiation at 12 MeV and 60 MeV results in an increase of 8.2% and 7.3% in conversion gain, respectively, and a decrease of 7.3% and 3.8% in full well capacity, respectively. The saturation output shows no significant change trend under 12 MeV proton irradiation, but increases by 3% under 60 MeV proton irradiation. In TCAD simulation, a three-dimensional 4T PPD pixel model is constructed. A simulation method that combines the Traps and Gamma Radiation model within TCAD and minority carrier lifetime mathematical model is employed to conduct global and local cumulative proton irradiation simulations for analyzing degradation mechanisms. It is proposed that the degradation of saturation output at the pixel level is determined by the FWC of PPD, the physical characteristics of the reset transistor and the capacitance of floating diffusion, but they have opposite effects. Proton irradiation leads to the accumulation of oxide-trapped positive charges in the shallow trench isolation on both sides of PPD, resulting in the formation of leakage current path in silicon, thereby reducing the full well capacity. A decrease in FWC leads to a decrease in saturation output. While, the radiation effect of the reset transistor causes the FD potential to increase during the FD reset phase, further leading to an increase in saturation output. Irradiation causes a decrease in the capacitance of the floating diffusion, resulting in an increase in conversion factor and consequently increasing the saturation output. The difference in radiation sensitivity among the three influence factors at the pixel level may result in a decrease or increase in saturation output with proton fluence. The above work comprehensively reveals and analyzes the mechanism of degradation in FWC, CVF and saturation output after irradiation, and the research results have certain guiding significance for the radiation damage analysis of CMOS image sensors.

Chemical mechanical polishing (CMP) represents one of the most important steps in the manufacturing of integrated circuits, and high surface quality is always required for the CMP processes of shallow trench isolation (STI) structures. Herein, a new series of polydopamine (PDA)-coated cerium oxide core-shell nanoparticles has been developed as efficient and non-damaging abrasives for CMP of SiO2 on the surface of silicon wafers. The composite abrasives with the structure of SiO2@CeO2@PDA have been fabricated in a simple manner and thoroughly characterized using scanning electron microscopy, transmission electron microscopy, energy dispersive X-ray spectroscopy, X-ray diffraction, and X-ray photoelectron spectroscopy. The SiO2 core enhances the content of Ce3+ in the abrasives, while the water-soluble PDA layer facilitates the interaction between the abrasives and SiO2 dielectrics. As a result, the wafers polished with SiO2@CeO2@PDA not only achieved a high polishing rate, but also exhibited a high surface quality (Ra = 0.109). This study not only presents a new efficient and non-damaging type of cerium oxide abrasive for CMP, but also highlights the potential of the surface coordination strategy in the fabrication of advanced abrasives for the manufacturing of integrated circuits.

The continuous miniaturization of semiconductor devices made it increasingly difficult to achieve high aspect ratio (HAR) features with precise control over the profile due to low etch selectivity over mask and aspect ratio dependent etching (ARDE). In this study, we investigated the effects of pulsed plasma modes, bias pulsing parameters, and additive gases(CF4 and C4F8) on the etching characteristics of nanoscale silicon (Si) trench using inductively coupled plasmas (ICPs) with Cl2/Ar gas mixtures. Compared to CW plasmas, synchronously pulsed plasmas exhibit improved Si etch profiles and reduced ARDE effects. Furthermore, asynchronously pulsed plasmas showed further decreased in the ARDE effect compared to synchronously pulsed plasmas. The additive gases changed the Si trench sidewall etch profiles by protecting Si trench sidewalls during etching using asynchronously pulsed plasmas. To understand the etch mechanism of pulsed plasmas, plasmas have been characterized with high voltage probes, time resolved optical emission spectroscopy (OES), a residual gas analyzer (RGA), and a retarding field energy analyzer (RFEA). Also, the XPS measurement has been performed to understand chemical reactions on the etched material surfaces. Experimental results demonstrated that, by controlling bias pulsing parameters and utilizing additive gases, nanoscale Si trench etch characteristics can be more precisely managed. This technique showed a promise for advanced etching applications requiring HAR features, such as nano-through silicon vias (TSVs), shallow trench isolation (STI), etc., making it a valuable method for next-generation semiconductor device fabrication.

Abstract As the density of bit cells increases, reliability issue in state-of-the-art Dynamic Random Access Memory (DRAM) becomes critical. Row Hammer (RH) is one of the reliability issues in sub-20 nm DRAM product. This work proposes an air gap technique [i.e., placing an air gap beneath passing wordline (PWL)], to suppress the RH in sub-20 nm DRAM. Using 3D TCAD simulations, the electric field and Shockley-Read-Hall (SRH) recombination rate are investigated when the PWL is activated. And, when the PWL is deactivated, the leakage current toward the bitline is extracted, to investigate the impact of the air gap on RH. It turned out that a low-k dielectric material in the air gap can effectively help to reduce the electric field intensity near the interface between shallow-trench-isolation (STI) and silicon. The relatively weak electric field can prevent the flow of electrons that causes read/write errors through trap-assisted recombination. By adopting the air gap in STI, 82 % improvement was estimated in terms of alleviating RH.

A comprehensive investigation of total ionizing dose effects on bulk FinFETs through TCAD simulation

Shallow trench isolation via chemical mechanical polishing (CMP-STI) tests of Si wafers using CeO2 slurry were studied. The impact of CeO2 slurry's solid concentration on the SiO2 removal rate and the selectivity ratio The effects of the solid concentration of CeO2 slurry on the removal rate of SiO2 and selectivity (SiO2/Si3N4) were investigated. The CeO2 abrasive was well matched to the XRD standard pattern, confirming that it had a cubic phase and the absence of any impurities. The SEM image showed that CeO2 primary particles had a spherical-like shape with a size within 30-60 nm. Additionally, the prepared CeO2 slurry showed a relatively high dispersion level. The wettability degree of the CeO2 slurry on top of the Si wafer surface was also sufficient. Furthermore, results from polishing tests indicated that both the SiO2 removal rate and the selectivity increased linearly with a rise in CeO2 solid concentration.

The effect of amino acid addition in CeO2-based slurry on SiO2/Si3N4 CMP: Removal rate selectivity, morphology, and mechanism research

With the persistent advancement of semiconductor technology, the demand for high-efficiency device manufacturing processes has surged. Chemical Mechanical Planarization (CMP) is a cornerstone for achieving angstrom-scale surface uniformity crucial for integrated circuits (IC) and logic devices. Shallow Trench Isolation (STI) CMP involves the selective removal of bulk oxide to electrically isolate active components on wafer surfaces. The modulation of the Ce3+ to Ce4+ surface state is essential for improved performance in both CMP and post-CMP (p-CMP) applications. Ce3+ is ideal for oxide material polishing due to its strong adherence to oxide surfaces, while Ce4+ is optimal for p-CMP cleaning, given its weak bond to oxide surfaces. Current p-CMP industry-standard methods utilize mechanical approaches, such as polyvinyl alcohol (PVA) brush scrubbing. However, this process induces high levels of shear force (SF), leading to secondary defects on the wafer surface (i.e. scratches, corrosion, increased surface roughness). To address these limitations, non-contact cleaning methods utilizing megasonic energy have emerged, which rely on generating reactive oxygen species (ROS) to induce particle removal. Thus, this study focuses on enhancing ceria particle removal during post-CMP cleaning by employing amine-based chemistries coupled with megasonic energy. While preliminary results imply that the mechanical cavitations induced by megasonic waves improve cleaning efficiency, this method will be optimized via the introduction of amine-based chemistries. Specifically, this work aims to leverage the unique properties of amines coupled with megasonic energy to facilitate enhanced ceria removal through electron donation, inducing a reduction in the oxidation state of ceria from Ce³⁺ to Ce⁴⁺. This approach improves particle removal while limiting secondary defects, enhancing redox activity induced by megasonic waves and chemical interactions. The mechanisms behind this method will be validated with CeO2 oxidation state kinetics, interfacial frictional changes, wafer surface roughness analysis, and SEM validation of particle removal efficiency.

The invention of CMP by IBM in 1983 represents an inflection point in the evolution of semiconductors. It was a bold and risky idea to mechanically apply abrasives to the surface of a wafer, but this new process for restoring a wafer to a planar state was the key to continued areal scaling and increased device complexity. Initially applied to a simple application for filling trenches with insulator, the potential of this technique was evident. Through understanding of material properties and subsequent manipulation of slurry chemistry, CMP was applied to enable the more challenging and technically critical processes for Shallow Trench Isolation and Tungsten contacts. The late 1990’s saw the introduction of copper interconnects. IBM was first to market this technology which continues to support conductors down to lines widths on the order of 10 nanometers! The CMP process required for copper interconnects demanded a thorough understanding of the materials present and potential surface phenomena for exploitation. For this need, a new and complex mechanism for copper planarization was invented. Equally challenging was the need for a subsequent non-selective barrier removal step. For this a unique, self-balancing approach was also invented, borrowing some elements from previous STI technology. Device architecture has progressed from planar geometry to FINFETs to Gate All Around, or Nanosheet technology. This evolution has required increasingly more CMP process steps with a concurrent demand for increased process control. Gate height control for Nanosheeets is currently paramount for performance, affected by many CMP steps in the process flow. A typical requirement is less than 1nm added variability per CMP step! Looking forward, CMP continues to be tapped to enable technology evolution. Polish steps are becoming part of the patterning process to enable pitch splitting for upcoming nodes. A VTFET integration approach can enable further area scaling but presents integration challenges; CMP is being asked to enable “third color” schemes for the protection of NFET vs PFET devices which is necessary at various points in the in the VTFET process flow. Heterogeneous Integration is demanding nanometer control of topography across large contact pads and large lateral distances. Finally, extreme scaling is creating fundamental challenges for metal polish at the contact and interconnect levels. CMP tool architecture currently does not provide for control of ambient conditions at the wafer surface during wet transport and post CMP cleaning. Subsequently, unwanted metal dissolution is observed. New tool designs will be needed to control wafer surface conditions, and particularly oxygen exposure through all steps within the CMP tool. This talk is dedicated to the special session in honor of Professor S.V. Babu

Effects of co-60 gamma-ray irradiation on the DC and RF characteristics of SiGe HBTs