Seven-level Inverter Research Articles

ANFIS-PSO-Based Optimization for THD Reduction in Cascaded Multilevel Inverter UPS Systems

Uninterruptible Power Supplies (UPSs) protect electronic equipment by delivering consistent power. Among the core components of a UPS is the inverter, which converts stored DC energy from batteries into AC power. This work focuses on a cascaded multilevel inverter topology for its ability to reduce voltage Total Harmonic Distortion (THD), which is essential for maintaining UPS efficiency and power quality. Using an ANFIS (Adaptive Neuro-Fuzzy Inference System) model, enhanced with the Particle Swarm Optimization (PSO) algorithm, the switching angles were optimized to minimize THD. This work focused on an online UPS with a seven-level inverter structure powered by three LifePo4 S17 batteries, with critical load levels (100%, 95%, 50%, 15%, and 5%) represented in 35 experimental cases. The experimental design allowed the ANFIS-PSO model to adapt to varying voltages, achieving robust THD reduction. The results demonstrated that this combination of ANFIS and PSO provided effective angle optimization, with a low standard deviation of 0.06 between the training and simulated %THD, highlighting the process’s accuracy. The analysis showed that, in most cases, the simulated THD values closely aligned with, or even improved upon, the calculated values, with discrepancies not exceeding 0.2%. These findings support the ANFIS-PSO model’s potential in enhancing power electronics applications, particularly in critical sectors like renewable energy and power transmission, where THD minimization is crucial.

Backstepping control of multilevel modified SVM inverter in variable speed DFIG-based dual-rotor wind power system

The backstepping control (BC) scheme has been successfully used in a variety of high-effectiveness industrial AC drives. This study presents the application of the BC technique based on multilevel modified space vector modulation (BC-MSVM) to get better the energy performance of a dual-rotor wind turbine system (DRWT). Two techniques are suggested to command the stator power of a doubly-fed induction generator (DFIG) driven by a DRWT. This work addresses the problems of the DRWT-based energy production system, such as stream fineness, power overshoot, and torque ripples. The use of a multilevel inverter in BC-MSVM led to an enhancement in the competence of the multilevel BC-MSVM technique and the system as a whole, and this is proven by the results performed using MATLAB software on a 1500 kW DFIG-DRWT. The use of a seven-level inverter led to a minimization in the rates of overshoot, ripples, steady-state error, and response time of active power by 26.66%, 53.84%, 2.09%, and 9.09%, respectively. Regarding the reactive power, the ratios were estimated at 18.12%, 34%, 25%, and 1.41%, respectively. These ratios prove that using a higher-level inverter significantly improves the voltage quality and characteristics of the DFIG-DRWT.

Self-Voltage Balanced Switched-Capacitor Seven-Level Inverter for Asymmetrical Solar PV Source Applications

In this paper, a novel structure of self-voltage balanced switched-capacitor-based seven-level inverter (SVB-SCSLI) is proposed for asymmetrical input energy source applications. SVB-SCSLI develops a seven-level staircase waveform with a minimum number of semiconductor devices compared to existing multilevel inverters (MLIs). The proposed converter is more suitable for the solar PV system where unequal DC voltage sources are available. The SVB-SCSLI also resolves the main difficulty of connecting many inverters in parallel to achieve staircase voltage. Besides, it attains voltage balancing capability at DC-link by holding constant capacitor voltage at every cycle. The detailed loss and steady-state analysis of the SVB-SCSLI are examined. Furthermore, the proposed converter’s efficiency improves with better power quality than other topologies reported in the literature. Finally, a prototype is fabricated, and experimental results are presented to validate the feasibility of SVB-SCSLI.

Transformer-Less Seven-Level Inverter with Triple Boosting Capability and Common Ground

This paper proposes a single-phase, transformer-less, seven-level inverter that utilizes eight switches, three capacitors, and two diodes to produce seven voltage levels with triple boosting ability. The availability of the common-ground point eliminates the leakage current in PV applications. The proposed Transformer-Less Triple-Boosting Seven-Level Inverter (TLTB7LI) has the ability to feed different types of loads from non-unity to unity power factors. The voltage balancing of capacitors takes place naturally without the need for auxiliary circuits and complicated control strategies. This paper investigates the appropriateness of the proposed TLTB7LI for grid-connected application. The Peak Current Controller (PCC) is employed to generate the switching pulses and regulate the active/reactive power transfer between the converter and the output, which guarantees the high quality of injected current to the output. Moreover, the operational principles, its control technique, as well as the design procedure of the key components of the proposed inverter have been presented. The superiority of the proposed inverter over existing counterparts has been verified through comparative analysis. The simulation and experimental analysis validated the proper operation of the proposed TLTB7LI.

A new triple voltage gain seven level switched capacitor-based inverter with minimum voltage stress

Abstract This paper presents, a new seven level triple voltage gain inverter topology is proposed based on switched capacitor technique. The proposed inverter topology has minimum voltage stresses on the switches and balanced capacitor voltages. This paper briefs the operation of proposed topology, voltage stress analysis, capacitor sizing and generation gate signals for the switches. In addition, proposed topology is modeled in industrial based software PLECS with practical switches to study thermal behavior and efficiency analysis. Further, the proposed inverter topology is compared with competitive topologies in the recent literature. The proposed topology has merits like minimum total standing voltage, switching redundancy and inherent polarity generation. Furthermore, MATLAB based simulations and experimental analysis is done to validate the superior performance the proposed topology. The experimental results for the proposed seven-level inverter are presented and discussed in brief by considering different types of loads, amplitude modulation variations and frequency variations.

Performance Characteristics of a Newly Developed Asymmetric Seven-Level Inverter Utilizing Various Hybrid Pulse Width Modulation Strategies

This study unveils a notable breakthrough in inverter technology, holding promise for substantial improvements in voltage quality and the attenuation of harmonic distortions within power systems. This study concentrates on the design and implementation of a novel Seven-Level Asymmetric Inverter (NSLAI) by incorporating various hybrid Pulse Width Modulation (PWM) techniques. The primary goal is to improve the output voltage magnitude while decreasing the Total harmonics compared to conventional PWM methods. The investigation introduces a novel Seven-Level Asymmetric Inverter (NSLAI) with innovative Hybrid Pulse Width Modulation (PWM) strategy. The purpose of this study is to investigate the distinct features of a recently developed asymmetric seven-level inverter, with a focus on exploring its characteristics through the implementation of diverse hybrid pulse width modulation strategies. Hybrid PWM methodology intricately centers on enhancing voltage quality and achieving better harmonious spectral characteristics. The gate signal producing approach for this suggested PWM technology incorporates a hybrid PWM methodology that combines trapezoidal and sinusoidal waveforms, as well as a standard triangular carrier signal enabling NSLAI. The hybrid version of PWM practices is deliberately used to generate switching signals for the NSLAI. An intensive evaluation of numerous indicators of effectiveness across multiple modulation indexes leads in the demonstrating of quantitative findings that compare the unique Hybrid PWM practice with established PWM tactics. Notably, the hybrid reference Carrier Overlapping strategy has emerged as a leading approach surpassing conventional pulse width modulation techniques. It achieves a significantly higher fundamental Root Mean Square voltage output and remarkably lower percentage of Total Harmonic Distortion values compared to all within the hybrid reference Variable Frequency strategy. The principal analytical tool used in the modeling investigation is MATLAB-SIMULINK. This study marks a watershed moment in the development of inverters, claiming significant improvements in battery power quality and distortion caused by harmonics avoidance across power systems, as evidenced by extensive simulation and prototype-based discoveries.

A Fault-Tolerant Control Method Based on Reconfiguration SPWM Signal for Cascaded Multilevel IGBT-Based Propulsion in Electric Ships

Electric ships have been developed in recent years to reduce greenhouse gas emissions. In this system, inverters are the key equipment for the permanent-magnet synchronous motor (PMSM) drive system. The cascaded insulated-gated bipolar transistor (IGBT)-based H-bridge inverter is one of the most attractive multilevel topologies for modern electric ship applications. Usually, the fault-tolerant control strategy is designed to keep the ship in operation for a certain period. However, the fault-tolerant control strategy with hardware redundancy is expensive and slow in response. In addition, after fault-tolerant control, the ship’s PMSM may experience shock and overheating, and IGBT life is reduced due to uneven switching frequency distribution. Therefore, a stratified reconfiguration carrier disposition Sinusoidal Pulse Width Modulation (SPWM) fault-tolerant control strategy is proposed. The proposed strategy can achieve fault tolerance without any extra hardware. A reconfiguration carrier is applied to improve the fundamental amplitude of inverter output voltage to maintain the operation of the ship’s PMSM. In addition, the available states of faulty H-bridge are fully used to contribute to the output. These can improve the life of IGBTs by reducing and balancing the power loss of each H-bridge. The principles of the proposed strategy are described in detail in this study. Taking a cascaded H-bridge seven-level inverter as an example, simulation and experimental results verify that the proposed strategy, in general, has a potential future application on electric ships.

Design and development of photovoltaic solar system based single phase seven level inverter

For solar photovoltaic (PV) systems, an upgraded triple gain seven-level inverter that works both independently and while connected to the grid is proposed. The two-stage configuration of the system is boost cascaded. The first stage has a one switch improved gain converter (OSIGC) to increase and normalize the input direct current (DC) voltage, and the second stage includes a unique seven level alternating current (AC) is produced via a multilevel inverter (MLI) design with triple voltage gain. The proposed OSIGC is appropriate for a broad range of conversions. The voltage gain in MLI was achieved using switched capacitor techniques. The DC-DC converter can achieve a maximum voltage gain of twelve and the MLI can achieve a maximum voltage gain of three, resulting in a DC-DC-AC voltage that can reach 36. Maximum power point tracking (MPPT) technique based on modified perturb and observe (PO) is used in OSIGC to maximise PV module power utilisation, and MLI control utilises sinusoidal pulse width modulation (SPWM) realistically. For the purpose of analysing the suggested system, a 200 Watt prototype statel is created. With a total harmonic distortion (THD) of 0.181%, up to 92.12% of the converter system’s overall efficiency is possible.

Switched-Capacitor-Based Seven-Level Inverter With Reduced Component Count and Current Stress

Switched-Capacitor-Based Seven-Level Inverter With Reduced Component Count and Current Stress

Performance Analysis of Simplified Seven-Level Inverter using Hybrid HHO-PSO Algorithm for Renewable Energy Applications

Performance Analysis of Simplified Seven-Level Inverter using Hybrid HHO-PSO Algorithm for Renewable Energy Applications

An open circuit fault-tolerant seven-level inverter with symmetric sources and reduced switch count

In this study, a new structure of symmetrical multilevel inverter is proposed. The proposed structure offers fewer controlled switches, power diodes, DC sources voltage stress across switches and losses compared with classical and a few recently proposed topologies in the literature. This paper presents a fault-tolerant (FT) seven-level inverter to provide uninterrupted supply to the connected load under open circuit fault in any single switch of the presented configuration. This configuration uses only six unidirectional and one bidirectional switch for any switch fault-tolerant operation. The phase opposition disposition sinusoidal pulse width modulation (POD-SPWM) and phase disposition sinusoidal pulse-width modulation (PD-SPWM) scheme are used for proper DC link utilisation in seven-level output voltage. The proposed symmetrical 7-level topology requires fewer power components and offers reduced voltage total harmonic distortion (THD) compared to other multi-level inverter (MLI) topologies. This MLI is investigated in MATLAB and validated using hardware in the loop platform of OPAL-RT. The obtained results are presented to demonstrate the successful FT operation under any single switch open circuit fault.

Scalar Control of Single-Phase Induction Motor Using PV Fed Modified Seven Level H-Bridge Inverter with Improved Sinusoidal PWM Technique

Scalar Control of Single-Phase Induction Motor Using PV-Fed Modified Seven-Level H-Bridge Inverter with Improved Sinusoidal PWM Technique" proposes an advanced modulation technique for controlling a modified H-Bridge solar photovoltaic (PV) fed seven-level inverter, designed to drive a single-phase 230V, 1/2 HP capacitor start-run induction motor (IM). This paper introduces an innovative H-bridge seven-level inverter topology achieved by optimizing the number of switches necessary to generate seven distinct voltage levels. The induction motor's speed is regulated using a scalar control approach. Pulse width modulation (PWM) signals, crucial for controlling the switches in the seven-level inverter, are generated using a combination of three identical sine wave signals acting as reference signals. These signals have an offset equal to the amplitude of the triangular carrier signal. The proposed modulation technique is validated through simulation in the MATLAB/Simulink® environment. Results demonstrate that the seven-level inverter efficiently suppresses harmonics by over 50% compared to three and five-level inverters without the need for an external LC filter. Additionally, the proposed technique significantly reduces the voltage stress across switches by 35%, even with a reduced number of switches utilized.

Efficiency of Series APF based on Nine-level NPC Inverter Compared to Seven-level Configuration

This article presents the performance comparison of Series Active Power Filter (Series APF) based on seven and nine multi-level Neutral Point Clamped (NPC) inverters using the same control scheme. The Series APF is one of the most efficient and effective modern custom power devices used in power distribution networks to compensate voltage harmonic and all voltage disturbances. The conventional configuration based on voltage source inverter (VSI) operated at very high switching frequency presents several drawbacks and limited for low power applications. To overcome these problems and improve the output voltage different multi-level are used in various power application in particular Flying Capacitor (FC), Cascade H-Bridge (CHB) and multi-level (NPC) inverters. In this study seven and nine-level (NPC) inverters are proposed for active power filtering system; these inverters present diverse advantages include the capability to reduce the harmonic content, decrease the voltage or current ratings of the semiconductors and mainly they can work at low switching frequency. To generate switching pulses Multi-Carrier Level-Shifted Pulse Width Modulation (MC-LSPWM) control technique is adopted with modified P-Q control strategies. To verify the accuracy and the performance of the proposed Series APF models, simulation is performed using MATLAB-Simulink platform and SimPowerSystem Toolbox. The obtained results show the superiority of series APF based on nine-level in term of THDv reduction compared to the systems with seven-level inverter topology.

Design of a multi-level inverter for solar power systems with a variable number of levels technique

<p>Overall harmonic distortion and losses will grow during an energy conversion process, while power stability will be reduced. Multilevel inverter technologies have recently become very popular as low-cost alternatives for a variety of industrial purposes. The design's minimal benefits include reduced component losses, decreased switching and conduction losses, along with enhanced output voltage and current waveforms. Also, a reduction of the harmonic components of the current and output voltage of the inverter are the most important requirements in multilevel inverters. A seven-level inverter design is presented in this paper that is simulated using MATLAB/Simulink. The inverter converts the DC voltage from three photovoltaic (PV) systems into AC voltage at seven levels. During an outage of one of the PV systems, the inverter will make a switching reduction and supply the AC voltage as a five-level inverter. The inverter’s total harmonic distortion (THD) when it performs as a five-level or seven-level inverter is 4.19% or 1.13% respectively. The modulation technique used is phase disposition via four carriers and a single reference signal at the fundamental frequency.</p>

Reduced Device Count for Self Balancing Switched-Capacitor Multilevel Inverter Integration with Renewable Energy Source

In this study, a new switched-capacitor-based seven-level inverter topology with a photovoltaic system is presented. The proposed topology requires a smaller number of devices and has the ability to self-balance the voltage across the capacitor. The proposed topology configuration is simple and has the ability to extend to higher levels of voltage. This multilevel inverter topology is suitable for low- and medium-voltage applications with photovoltaic (PV) system integration. To improve the PV system efficiency as an input of a DC–DC boost converter, a Fuzzy logic-based maximum power point controller technique is used. A PV system with a DC–DC boost converter integrates with the proposed seven-level inverter topology. The anti-predatory particle swarm optimization (APSO) technique is used to solve the non-linear transduction equations of the seven-level PV switched-capacitor-based multilevel inverter (7L−PV−SCMLI) topology. The proposed APSO is described to minimize the harmonics in the multilevel inverter (MLIs), which is a complex optimization problem involving a non-linear transcendental equation. Furthermore, APSO can be applied in order to solve non-linear transcendental equations for all symmetrical and asymmetrical MLIs that have equal and non-equal DC sources. The APSO-based selected harmonic elimination (SHE) technique obtained the best switching angle value, and the optimized obtained switching angles reduced the total harmonic distortion (THD) of 7L−PV−SCMLI.

Quasi-Resonant Switched-Capacitor-Based Seven-Level Inverter With Reduced Capacitor Spike Current

This article proposes a novel seven-level multilevel inverter (MLI) with integrated output voltage boosting functions. The inverter uses switched capacitors (SCs), a key component of a voltage-boosting approach, to achieve the goal of increasing the output voltage at the load end. Additionally, the MLI has the ability to automatically balance the capacitor voltages. The proposed inverter is more cost-effective and has lower conduction losses than those of its rivals since it has fewer components than competing designs. An inductor is used in the capacitor charging loop to both minimize dc source current spikes and enable quicker charging of the capacitor, thereby increasing the capacitor’s lifespan. This article provides a number of waveforms, including output voltage and current, under various loading conditions and modulation indices. A laboratory model is also employed to support the viability of the proposed topology. The performance of the system is verified using MATLAB/Simulink. At long last, the maximum achievable experimental efficiency of 98.77% and total harmonic distortion (THD) for output voltage and current were 20.44% and 0.54%, respectively, at 300 V and 1.2 kW load.

New power equalization modulation strategy for CHB seven-level inverters

New power equalization modulation strategy for CHB seven-level inverters

A Seven-Level Inverter With Natural Balance and Boosting Capability

This paper introduces a new active-neutral-point clamped (ANPC) seven-level inverter with a switched-capacitor technique. The introduced inverter generates a seven-level ac output voltage with a maximum voltage-boosting gain of 1.5. The higher output voltage does not imply high voltage across the switches, as the maximum blocking voltage of the switches does not exceed the input voltage. The dc-link capacitor voltages are naturally balanced, and the flying capacitor achieves self-balancing through the series-parallel connection of the input voltage source, without the need for auxiliary control methods. Additionally, compared to major traditional seven-level inverters such as NPC, FC, and hybrid topologies, the proposed topology reduces the dc voltage requirement by 33.3%, eliminating the need for an intermediate dc-boosting stage and making the introduced inverter a good candidate for applications such as photovoltaic panels and full-cells systems, both characterized by a low input voltage. The operation and performance of the proposed topology are validated through simulation and experimental results.

Genetic Algorithm Based 7-Level Step-Up Inverter with Reduced Harmonics and Switching Devices

This paper presents a unique voltage-raising topology for a single-phase seven-level inverter with triple output voltage gain using single input source and two switched capacitors. The output voltage has been boosted up to three times the value of input voltage by configuring the switched capacitors in series and parallel combinations which eliminates the use of additional step-up converters and transformers. The selective harmonic elimination (SHE) approach is used to remove the lower-order harmonics. The optimal switching angles for SHE is determined using the genetic algorithm. These switching angles are combined with a level-shifted pulse width modulation (PWM) technique for pulse generation, resulting in reduced total harmonic distortion (THD). A detailed comparison has been made against other relevant seven-level inverter topologies in terms of the number of switches, drivers, diodes, capacitors, and boosting facilities to emphasize the benefits of the proposed model. The proposed topology is simulated using MATLAB/SIMULINK and an experimental prototype has been developed to validate the results. The Digital Signal Processing (DSP) TMS320F2812 board is used to generate the switching pulses for the proposed technique and the experimental results concur with the simulated model outputs.

A New Boost Topology Seven-Level Inverter of High Voltage Gain Ability and Continuous Input Current With MPPT for PV Grid Integration

A New Boost Topology Seven-Level Inverter of High Voltage Gain Ability and Continuous Input Current With MPPT for PV Grid Integration