Instruction Set Research Articles

Unpacking Chinese young learners’ L2 learning motivation: Does CLIL make a difference?

AbstractThis study aimed to compare the English language learning motivation of two cohorts of Chinese primary school learners in a Content and Language Integrated Learning (CLIL) and a non‐CLIL instructional setting. A total of 270 learners from third, fourth and fifth grades in the CLIL programme (N = 184) and the non‐CLIL programme (N = 86) participated in this study. Data were collected through a young learners’ L2 motivation questionnaire. Results indicated that CLIL learners overall displayed a significantly higher level of L2 motivation than their non‐CLIL counterparts in the Ideal L2 Self domain and L2 Learning Experience. However, students in the non‐CLIL programme overall rated themselves higher in the Ought‐to L2 Self domain. When comparing L2 motivation levels between CLIL and non‐CLIL sub‐groups in different grades, we found that the non‐CLIL subsamples’ mean motivational scores witnessed a continuous decline with the increase of grade in the scales of Ideal L2 Self, Ought‐to L2 Self and Parental Expectations. Regarding Cultural Interest and L2 Learning Experience, CLIL students in both the fourth‐ and fifth‐grade cohorts exhibited a significantly higher level of motivation than their non‐CLIL peers. This study provides empirical evidence supporting the implementation of CLIL programme as a potential strategy to boost young learners’ motivation towards L2 learning.

Chemical modification patterns for microRNA therapeutic mimics: a structure-activity relationship (SAR) case-study on miR-200c.

microRNA (miRNA) mimics are an emerging class of oligonucleotide therapeutics, with a few compounds already in clinical stages. Synthetic miRNAs are able to restore downregulated levels of intrinsic miRNAs, allowing for parallel regulation of multiple genes involved in a particular disease. In this work, we examined the influence of chemical modifications patterns in miR-200c mimics, assessing the regulation of a selection of target messenger RNAs (mRNA) and, subsequently, of the whole transcriptome in A549 cells. We have probed 37 mimics and provided an initial set of instructions for designing miRNA mimics with potency and selectivity similar to an unmodified miRNA duplex. Additionally, we have examined the stability of selected mimics in serum. Finally, the selected two modification patterns were translated to two other miRNAs, miR-34a and miR-155. To differing degrees, these designs acted on targetmRNAs in a similar manner to the unmodified mimic. Here, for the first time, we describe a structured overview of 'miRNA mimics modification templates' that are chemically stabilised and optimised for use in an in vitro set up and highlight the need of further sequence specific optimization when mimics are to be used beyond in vitro tool experiments.

AUTOMATION OF PETROLEUM STORAGE TANK LEAKAGE THROUGH PRODUCT TRANSFER CONTROL USING PROGRAMMABLE LOGIC CONTROLLER

Industrial storage tanks have always been a critical part of the petrochemical industry due to their capacity to either act as a buffer to other plant processes or simply to store enormous amounts of fluids for a long period of time in a controlled environment. These petroleum storage tanks are supposedly constructed to follow specific sets of instructions guided by the American Petroleum Industry from the type of material used up to the welding procedure. But due to inefficient construction, unmaintained and uninspected problems, welding defects, and environmental concerns among others, a leak in a storage tank can occur and will be a major problem as this can cause fire, explosion, and environmental hazards. Additionally, due to tensions between Ukraine and the Russian government and the succeeding Russian ban on oil imports, the cost of 1 barrel of oil rises at an alarming since 2020. With that in mind, an automation procedure is proposed by the researchers, to save as much of this oil from leaking and being unusable and to reduce the causes of further accidents. This paper not only seeks to use an existing tank layout, with currently installed level indicator transmitters, motor-operated control valves, and other equipment, but also to introduce flammable gas detectors that could detect the leaked petroleum on the ground and would initiate the automation procedure. The automation setup was realized by flowcharts, PLC, and ladder logic simulation using Picosoft software. Automation procedures are analyzed wherein the tanks are being filled, the trucks are being loaded, a leaking tank has its contents pumped to another tank, and a leaking tank has its contents pumped to the truck loading station. Results show that a minimum number of 8.89 barrels of oil saved could breakeven the cost of an estimated amount of $80-90 dollars per barrel of oil can be saved by the proposed automation.

Implementation of 64-Bit RISC Processor Using Vedic Multiplier

Abstract: In this project, 64 bit RISC processor designed with Vedic multiplier design. Reduced Instruction Set Computer (RISC) is a design which presents better performances, higher speed of operation and favors the smaller and simpler set of instructions. In addition to multiplier which is implemented using vedic mathematics we are also proposing an adder which is mux- based full adders for building higher bit adders in an area and speed efficient which is implemented in addition as well as for compression in vedic mathematic to obtain the output. A 64 bit RISC processor designed in this paper is capable of executing more number of instructions with simple design, using the Verilog Hardware Description Language (HDL) and the design is simulated in the Xilinx Vivado 2018.3. The main achievement in this work is that the multiplier unit in Arithmetic and Logic Unit (ALU) and Multiplier and Accumulator (MAC) is implemented using Vedic Sutras. The main principle used in Vedic mathematics is to reduce the typical calculation of conventional mathematics to very simple one and hence reduce the overall computational complexity. Vedic Multiplier design is based on “Urdhva Triyakbhyam” which is among the 16 Vedic Sutras and MUX-Based Full Adders The proposed RISC processor is very simple and capable of executing 14 instructions. The achievement in this work is that savings in power in case of MAC and ALU is achieved compared to conventional ALU and MAC respectively. Also the delay is reduced in MAC and ALU in comparison with conventional ALU and MAC correspondingly. These Vedic MAC and ALU are then integrated with other blocks in processor and 64-bit Vedic processor is developed. This reduces the delay and saves area compared to conventional processor. Hence the improvement in speed of operation, and less area utilization are the key features of designed RISC processor.

ANALISIS VALIDITAS PENGEMBANGAN MODUL PEMBELAJARAN PENGELASAN SMAW BERBASIS PROYEK (PROJECT BASED LEARNING)

A teaching module is a set of tools, media, methods, instructions and learning guidelines that are prepared and planned to suit the student's development phase. The following research aims to examine the feasibility of a product from developing a project-based SMAW Welding Module (PjBl) for Mechanical Engineering Vocational Education students, Faculty of Teacher Training and Education, Sultan Ageng Tirtayasa University. This research was carried out using a quantitative approach. The following research is part of research and development using the Borg and Gall method, namely Develop Preliminary Form of Product Testing using the Expert Judgment validity test. The research results were analyzed descriptively quantitatively. The research results showed that the feasibility of the module content reached 87% in the very good and very feasible category, the feasibility of the learning presentation reached 92% in the very good and very appropriate category, the appropriateness of the language reached 89% and was in the very good and very feasible category and finally based on feasibility. Graphics reached 93% so it is included in the very good and very worthy category. Overall, the conclusion is drawn that the validity of the Project-based SMAW Welding Module (PjBl) is in the very good and very feasible category and can be continued to the Preliminary Field Testing stage.

Message Binary Matrix Reshaping and Rotating Left to Encrypt-Decrypt Secret Message

Secret messages are the most circulated via communication environments digital data, these messages may be secret, private, and the communication environment may unsafe, so they need protection from being hacked. In this paper research a simple method of message cryptography will be proposed, the method will use one round and simplified set of instruction to apply message encryption-decryption. The method will use a simple private key to determine the reshaping factor and the number of rotating left digits. The message binary matrix will be reshaped to a number of columns equal the reshaping factor, and each columns will be rotated left for a selected number of digits to apply message encryption-decryption. The reshaping factor will be tested to show the best choice of the reshaping factor, which will provide the best performance, the message length will be tested and some recommendations will be provided. The quality of the proposed method will tested by implementing various messages and examining the quality parameters values to prove that the proposed method will satisfy the quality requirements of good crypto system.

Kalis: a modern implementation of the Li & Stephens model for local ancestry inference in R

BackgroundApproximating the recent phylogeny of N phased haplotypes at a set of variants along the genome is a core problem in modern population genomics and central to performing genome-wide screens for association, selection, introgression, and other signals. The Li & Stephens (LS) model provides a simple yet powerful hidden Markov model for inferring the recent ancestry at a given variant, represented as an N×N\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$N \ imes N$$\\end{document} distance matrix based on posterior decodings.ResultsWe provide a high-performance engine to make these posterior decodings readily accessible with minimal pre-processing via an easy to use package kalis, in the statistical programming language R. kalis enables investigators to rapidly resolve the ancestry at loci of interest and developers to build a range of variant-specific ancestral inference pipelines on top. kalis exploits both multi-core parallelism and modern CPU vector instruction sets to enable scaling to hundreds of thousands of genomes.ConclusionsThe resulting distance matrices accessible via kalis enable local ancestry, selection, and association studies in modern large scale genomic datasets.

Parallel Implementation of Lightweight Secure Hash Algorithm on CPU and GPU Environments

Currently, cryptographic hash functions are widely used in various applications, including message authentication codes, cryptographic random generators, digital signatures, key derivation functions, and post-quantum algorithms. Notably, they play a vital role in establishing secure communication between servers and clients. Specifically, servers often need to compute a large number of hash functions simultaneously to provide smooth services to connected clients. In this paper, we present highly optimized parallel implementations of Lightweight Secure Hash (LSH), a hash algorithm developed in Korea, on server sides. To optimize LSH performance, we leverage two parallel architectures: AVX-512 on high-end CPUs and NVIDIA GPUs. In essence, we introduce a word-level parallel processing design suitable for AVX-512 instruction sets and a data parallel processing design appropriate for the NVIDIA CUDA platform. In the former approach, we parallelize the core functions of LSH using AVX-512 registers and instructions. As a result, our first implementation achieves a performance improvement of up to 50.37% compared to the latest LSH AVX-2 implementation. In the latter approach, we optimize the core operation of LSH with CUDA PTX assembly and apply a coalesced memory access pattern. Furthermore, we determine the optimal number of blocks/threads configuration and CUDA streams for RTX 2080Ti and RTX 3090. Consequently, in the RTX 3090 architecture, our optimized CUDA implementation achieves about a 180.62% performance improvement compared with the initially ported LSH implementation to the CUDA platform. As far as we know, this is the first work on optimizing LSH with AVX-512 and NVIDIA GPU. The proposed implementation methodologies can be used alone or together in a server environment to achieve the maximum throughput of LSH computation.

Comprehensive analysis of energy efficiency and performance of ARM and RISC-V SoCs

Over the past few years, ARM has been the dominant player in embedded systems and System-on-Chips (SoCs). With the emergence of hardware platforms based on the RISC-V architecture, a practical comparison focusing on their energy efficiency and performance is needed. In this study, our goal is to comprehensively evaluate the energy efficiency and performance of ARM and RISC-V SoCs in three different systems. We will conduct benchmark tests to measure power consumption and overall system performance. The results of our study are valuable to developers and researchers looking for the most appropriate hardware platform for energy-efficient computing applications. Our observations suggest that RISC-V Instruction Set Architecture (ISA) implementations may demonstrate lower average power consumption than ARM, but this does not automatically imply a superior performance per watt ratio for RISC-V. The primary focus of the study is to evaluate and compare these ISA implementations, aiming to identify potential areas for enhancing their energy efficiency. Furthermore, to ensure the practical applicability of our findings, we will use the Computational Fluid Dynamics software OpenFOAM. This step serves to validate the relevance of our results in real-world scenarios. It allows us to fine-tune execution parameters based on the insights gained from our initial study. By doing so, we aim not only to provide meaningful conclusions but also to investigate the transferability of our results to practical applications. Our analysis will also scrutinize the capabilities of these SoCs when handling nonsynthetic software workloads, thereby broadening the scope of our evaluation.

Dynamic Voltage and Frequency Scaling as a Method for Reducing Energy Consumption in Ultra-Low-Power Embedded Systems

Dynamic voltage and frequency scaling (DVFS) is a technique used to optimize energy consumption in ultra-low-power embedded systems. To ensure sufficient computational capacity, the system must scale up its performance settings. The objective is to conserve energy in times of reduced computational demand and/or when battery power is used. Fast Fourier Transform (FFT), Cyclic Redundancy Check 32 (CRC32), Secure Hash Algorithm 256 (SHA256), and Message-Digest Algorithm 5 (MD5) are focused functions that demand computational power to achieve energy-efficient performance. Selected operations are analyzed from the energy consumption perspective. In this manner, the energy required to perform a specific function is observed, thereby mitigating the influence of the instruction set or system architecture. For stable operating voltage scaling, an exponential model for voltage calculation is presented. Statistical significance tests are conducted to validate and support the findings. Results show that the proposed optimization technique reduces energy consumption for ultra-low-power applications from 27.74% to up to 47.74%.

MOSAIC: Maximizing ResOurce Sharing in Behavioral Application SpecIfic ProCessors

This work presents a method that can quickly determine which hardware accelerators (HWaccs) should be mapped together onto an Application-Specific Instruction Set Processor (ASIP), such that the resources shared among them are maximized. This work in particular targets HWaccs generated from untimed behavioral descriptions for High-Level Synthesis (HLS). Although HLS is a single process synthesis method, our approach is able to force resource sharing among the HWaccs by combining their behavioral descriptions together into a single description based on their potential to share resources. These shared resources include functional units (FUs) like multipliers, adders, and dividers, and also registers. In particular, our proposed flow leads up to 48% in area savings and on average 30%. Because an exhaustive enumeration of all possible combinations can lead to long runtimes, we propose a fast heuristic that leads to comparable results (only 6% worse on average), while being much faster (on average 500×).

Teaching computer architecture by designing and simulating processors from their bits and bytes.

Teaching computer architecture (Comp-Arch) courses in undergraduate curricula is becoming more of a challenge as most students prefer software-oriented courses. In some computer science/engineering departments, Comp-Arch courses are offered without the lab component due to resource constraints and differing pedagogical priorities. This article demonstrates how students working in teams are motivated to study the Comp-Arch course and how instructors can increase student motivation and knowledge by taking advantage of hands-on practices. The teams are asked to design and implement a 16-bit MIPS-like processor with constraints as a specific instruction set, and limited data and instruction memory. Student projects include following three phases, namely, design, desktop simulator implementation, and verification using hardware description language (HDL). In the design phase, teams develop their Comp-Arch to implement specified instructions. A range of designs resulted, e.g., (a) a processor with extensive user-defined instructions resulting in longer cycle times (b) a processor with a minimal instruction set but with a faster clock cycle time. Next, teams developed a desktop simulator in any programming language to execute instructions on the architecture. Finally, students engage in Verilog Hardware Description Language (HDL) projects to simulate and verify the data-path designed during the initial phase. Student feedback and their current understanding of the project were collected through a questionnaire featuring varying Likert scale questions, some with a ten-point scale, and others with a five-point scale. Results of the survey show that the hands-on approach increases students' motivation and knowledge in the Comp-Arch course, which is centered around computer system design principles. This approach can also be effectively extended to related courses, such as Microprocessor Design, which delves into the intricacies of creating and implementing microprocessors or central processing units (CPUs) at the hardware level. Furthermore, the present study demonstrates that interactions, specifically through peer reviews and public presentations, between students in each phase increases their knowledge and perspective on designing custom processors.

Understanding Teachers’ Lived Experiences of Instructional Collaboration in Inclusive and Mainstream Settings: A Transcendental Phenomenological Approach

ABSTRACT This project investigates teachers’ lived experiences of instructional collaboration in mainstream and inclusive education settings, looking both at the factors that special and general education teachers believe hinder instructional collaboration, and those that teachers identify as critical to facilitating it. The study draws upon a transcendental phenomenological approach, with initial in-depth and follow-up interviews with nine special and general education teachers from the southern region of Saudi Arabia. The data analysis generated several themes and a number of sub-themes that helped provide a deeper understanding of the phenomenon. These themes were school culture, work pressure, and facilitating factors. Thus, examining the experiences of teachers in inclusive instructional collaboration settings revealed various factors that influence the successful implementation of this practice. Recommendations for future directions that may contribute to strengthening instructional collaboration in schools are discussed in the paper.

Improving Performance of Massive Text Real-Time Classification for Document Confidentiality Management

For classified and sensitive electronic documents within the scope of enterprises and organizations, in order to standardize and strengthen the confidentiality management of enterprises and meet the actual needs of secret text classification, a document automatic classification optimization method based on keyword retrieval and the kNN classification algorithm is proposed. The method supports keyword classification management, provides users with keywords of multiple risk levels, and then combines a matching scanning algorithm to label keywords of different levels. The text with labels is used as the training set of the kNN algorithm to classify the target text and realize the classification protection of text data. Aimed at solving the shortcomings of large feature vector dimension, low classification efficiency, and low accuracy in existing kNN text classification methods, an optimization method is proposed using a feature selection algorithm and a kNN algorithm based on an AVX instruction set to realize real-time classification of massive texts. By constructing a keyword dictionary and an optimized feature vector, parallel calculation of the feature vector weight and distance vector is realized, and the accuracy and efficiency of text classification are improved. The experimental results show that the multi-classification effect of the feature selection algorithm used in this paper, tf-DE, is better than that of the traditional tf-idf algorithm, and the classification effect of kNN is comparable to that of the support vector machine (SVM) algorithm. With the increase in feature vector dimensions, the classification effect of the text classification algorithm is improved and the classification time also increases linearly. The AVX-256 acceleration method takes about 55% of the time of the original version, thus verifying the effect of multi-classification of massive texts for document confidentiality management.

Application-level Validation of Accelerator Designs Using a Formal Software/Hardware Interface

Ideally, accelerator development should be as easy as software development. Several recent design languages/tools are working toward this goal, but actually testing early designs on real applications end-to-end remains prohibitively difficult due to the costs of building specialized compiler and simulator support. We propose a new first-in-class, mostly automated methodology termed “3LA” to enable end-to-end testing of prototype accelerator designs on unmodified source applications. A key contribution of 3LA is the use of a formal software/hardware interface that specifies an accelerator’s operations and their semantics. Specifically, we leverage the Instruction-level Abstraction (ILA) formal specification for accelerators that has been successfully used thus far for accelerator implementation verification. We show how the ILA for accelerators serves as a software/hardware interface, similar to the Instruction Set Architecture for processors, that can be used for automated development of compilers and instruction-level simulators. Another key contribution of this work is to show how ILA-based accelerator semantics enables extending recent work on equality saturation to auto-generate basic compiler support for prototype accelerators in a technique we term “flexible matching.” By combining flexible matching with simulators auto-generated from ILA specifications, our approach enables end-to-end evaluation with modest engineering effort. We detail several case studies of 3LA, which uncovered an unknown flaw in a recently published accelerator and facilitated its fix.

Opening, deepening, and widening dialogic space in argument classrooms

ABSTRACT Given the importance of teaching and learning argumentation, across disciplines for participation in academic and civil discourse, this article examines how dialogic space is created and sustained in classrooms where argument is taught and learned and, when it is created, what affordances it brings to learning argumentation. Dialogic space is a shared space of mutual resonance where we see, feel, or think things from at least 2 points of view at once. While any instructional setting has the potential to create dialogic space, this potential is not always realized. Using data from previously published research on classroom discourse around argumentation in secondary English language arts classrooms, I present how dialogic space can be opened, deepened, and widened as well as how teachers can engage students in argumentation within this space. I conclude by briefly discussing the contexts and affordances of creating dialogic space in argument classrooms.

Real-Time Performance Benchmarking of RISC-V Architecture: Implementation and Verification on an EtherCAT-Based Robotic Control System

RISC-V offers a modular technical approach combined with an open, royalty-free instruction set architecture (ISA). However, despite its advantages as a fundamental building block for many embedded systems, the escalating complexity and functional demands of real-time applications have made adhering to response time deadlines challenging. For real-time applications of RISC-V, real-time performance analysis is required for various ISAs. In this paper, we analyze the real-time performance of RISC-V through two real-time approaches based on processor architectures. For real-time operating system (RTOS) applications, we adopted FreeRTOS and evaluated its performance on HiFive1 Rev B (RISC-V) and STM3240G-EVAL (ARM M). For real-time Linux, we utilized Linux with the Preempt-RT patch and tested its performance on VisionFive 2 (RISC-V), MIO5272 (x86-64), and Raspberry Pi 4 B (ARM A). Through these experiments, we examined the response times on the real-time mechanisms of each operating system. Additionally, in the Preempt-RT experiments, scheduling latencies were evaluated by means of the cyclictest. These are very important parameters for implementing real-time applications comprised of multi-tasking. Finally, in order to show the real-time capabilities of RISC-V practically, we implemented motion control of a six-axis collaborative robot, which was performed on the VisionFive 2. This implementation provided a comparative result of RISC-V’s performance against the x86-64 architecture. Ultimately, the results indicated that the real-time performance of RISC-V for real-time applications was feasible. A noticeable achievement of this research is its first implementation of an EtherCAT master on RISC-V designed for real-time applications. The successful implementation of the EtherCAT master on RISC-V shows real-time capabilities for a wide range of real-time applications.

Latency-Constrained Neural Architecture Search Method for Efficient Model Deployment on RISC-V Devices

The rapid development of the RISC-V instruction set architecture (ISA) has garnered significant attention in the realm of deep neural network applications. While hardware-aware neural architecture search (NAS) methods for ARM, X86, and GPUs have been extensively explored, research specifically targeting RISC-V remains limited. In light of this, we propose a latency-constrained NAS (LC-NAS) method specifically designed for RISC-V. This method enables efficient network searches without the requirement of network training. Concretely, in the training-free NAS framework, we introduce an RISC-V latency evaluation module that includes two implementations: a lookup table and a latency predictor based on a deep neural network. To obtain real latency data, we have designed a specialized data collection pipeline for RISC-V devices, which allows for precise end-to-end hardware latency measurements. We validate the effectiveness of our method in the NAS-Bench-201 search space. Experimental results demonstrate that our method can efficiently search for latency-constrained networks for RISC-V devices within seconds while maintaining high accuracy. Additionally, our method can easily integrate with existing training-free NAS approaches.

Understanding the perceptions of memorable messages about academic performance among students of color in the United States*

ABSTRACT This study addresses students of color (SOC) perceptions of memorable messages (MMs) related to their academic ability. A survey of 165 undergraduate students who identified as people of color vividly recalled both positively and negatively valenced messages. Our analysis identified four distinct positive themes embedded within the MMs: praise, encouragement, advice, and support, and four negative themes: criticism, discouragement, reprimand, and accusation. The study also showed that many SOC used positive MMs as microaffirmations to combat threats to their identity, and perceived negative MMs as racial microaggressions that trigger a lack of confidence and/or doubt in their academic ability. We conclude with a set of practical recommendations for constructing equity-minded communication in instructional settings that promotes SOC success.

Design and hazard solving of five-stage pipeline RISC-V processor structure

Benefiting from its late arrival, the RISC-V architecture capitalizes on the maturity of computer architecture technology achieved through years of development. This allows the RISC-V design to sidestep issues that have been exhaustively examined during the evolution of computer architecture over time. Adhering to a specific sequence for executing instructions with a CPU results in extended processing durations. However, in a pipelined architecture, the execution of one instruction doesn't disrupt the synchronized progression of other instructions. The introduction of a pipeline structure can improve processor speed, performance, throughput, and so on. In this paper, the pipeline structure is divided into five stages: fetch, decode, execute, memory and write back. It uses registers to solve the possible hazards of pipelining. The central processing unit employs the RISC-V RV32I foundational integer instruction set architecture. This paper used Verilog language to design, and Vivado simulation environment to simulate the design. The pipeline structure is simulated successfully, including R, I, B, and J type instructions, and the structure hazard, control hazard, data hazard, and other three hazards are also successfully solved.