Server Processors Research Articles

Energy efficient permanence‐based community detection algorithm

SummaryDetecting an accurate community structure is a crucial task in network analysis. With the increasing popularity of social networking sites, it is essential to have a community detection algorithm that is not only efficien but also cost‐effective for running in data centers. There are several metrics for estimating the accuracy of community detection. However, previous research has shown that permanence, a vertex‐centric metric, provides the most precise estimate of a community structure compared to other approaches. Despite this, no study has been conducted on parallelizing a permanence‐based community detection algorithm and analyzing its energy efficiency. This article introduces Amoeba, a task parallel implementation of a permanence‐based community detection algorithm designed for multicore processors. It uses dynamic tasking to schedule the inherent irregular computation, and it can dynamically adapt the total number of parallel threads, which results in improved energy efficiency. We evaluated Amoeba using several real‐world and artificial graphs on a multicore server processor. Our experimental results show that Amoeba achieves a geometric mean speedup of 15.3 over its sequential implementation, and due to thread adaptability, it achieves energy savings of 12.4% and a speedup of 6% over its nonadaptive implementation.

The Security and Protection System of Electromechanical Equipment in Smart Campus using the Improved Data Mining Algorithm

In order to improve the maintenance and management efficiency of campus electromechanical equipment and reduce or even avoid the safety risks brought by campus electromechanical equipment, this work uses the data mining algorithm to design the security and protection system of campus electromechanical equipment. First, this work constructs the campus electromechanical equipment classification model using the Bayesian algorithm of data mining algorithm and designs a simulation experiment to verify the effect of the classification model. Then, the security and protection system for the campus electromechanical equipment is designed. It includes the system business process, system function design, system core module’s function design and system implementation. Finally, a simulation experiment is designed to verify the system’s performance. The results show that: (1) Bayesian algorithm is superior to the K-Nearest Neighbor (KNN) algorithm in both classification effect and running time. (2) When the browser concurrency in the system increases, the server processor and memory usage also increases, but the value meets the expected requirements. It shows that the system has a certain browser concurrency-bearing capacity. Moreover, as the browser concurrency of the system increases, the response time of the test also increases, but the value meets the expected requirements. This work aims to improve the maintenance efficiency of campus electromechanical equipment and provide a reference for the safety protection work of electromechanical equipment in other enterprises or units.

OptimML: Joint Control of Inference Latency and Server Power Consumption for ML Performance Optimization

Power capping is an important technique for high-density servers to safely oversubscribe the power infrastructure in a data center. However, power capping is commonly accomplished by dynamically lowering the server processors’ frequency levels, which can result in degraded application performance. For servers that run important machine learning (ML) applications with Service-Level Objective (SLO) requirements, inference performance such as recognition accuracy must be optimized within a certain latency constraint, which demands high server performance. In order to achieve the best inference accuracy under the desired latency and server power constraints, this paper proposes OptimML, a multi-input-multi-output (MIMO) control framework that jointly controls both inference latency and server power consumption, by flexibly adjusting the machine learning model size (and so its required computing resources) when server frequency needs to be lowered for power capping. Our results on a hardware testbed with widely adopted ML framework (including PyTorch, TensorFlow, and MXNet) show that OptimML achieves higher inference accuracy compared with several well-designed baselines, while respecting both latency and power constraints. Furthermore, an adaptive control scheme with online model switching and estimation is designed to achieve analytic assurance of control accuracy and system stability, even in the face of significant workload/hardware variations.

SGXFault: An Efficient Page Fault Handling Mechanism for SGX Enclaves

Trusted Execution Environments (TEEs) such as Intel SGX are becoming a commonplace for the security in server processors. Intel SGX provides the guarantees of confidentiality, integrity and replay attack protection for a specific region of memory. However, the downside of it is the performance bottleneck due to the context switching overhead and the page faults for the larger memory footprint applications. In this paper, we propose a scheme <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">SGXFault</i> which ensures for major part of the execution, the pages are available in the secure memory when needed. We do this decision at the last level cache (LLC) by locking the blocks of the frequent pages to the LLC using Cache Lockdown mechanism. In addition to this, we do a page-level prediction based prefetching when there is a miss in the LLC. Using the combination of both the approaches, we are able to outperform baseline Intel SGX and recent competing scheme by around 18.6% and 17.8% respectively.

AVX-TSCHA: Leaking information through AVX extensions in commercial processors

Modern x86 processors support an AVX instruction set to boost performance. However, this extension set may also cause security issues. We discovered that there are vulnerable properties in the implementation of the masked load/store instructions. First, these instructions can suppress exceptions caused by invalid or inaccessible memory access. Second, the execution time of these instructions leaks the current state of the page mappings, permissions, and TLB states.Based on this, we present a novel AVX timing side-channel attack that can defeat address space layout randomization. We demonstrate the significance of our side-channel attack by showing User and Kernel ASLR breaks on the recent Intel and AMD processors in various environments, including cloud computing systems (Amazon AWS, Google GCP, and Microsoft Azure), an SGX enclave (a fine-grained ASLR break), and major OSes (Linux, Windows, and macOS). Our attack can identify the Linux kernel's base address in 0.29 ms as well as those of loaded kernel modules in 2.24 ms, with a near-zero error rate. We further demonstrate that our attack can be used to infer user behavior, such as mouse movements and data transmissions over the network. Our evaluation results on multiple mobile, desktop, and server processors (a total of 26 Intel and AMD CPUs) show that 1) the AVX timing side-channel works on the vast majority of Intel processors (from the Sandy Bridge microarchitecture) as well as AMD processors (from the Zen microarchitecture onward) and 2) our KASLR breaks are very fast and reliable. To the best of our knowledge, our attack is the first to demonstrate a KASLR break on both the recent Intel Alder Lake and AMD Zen 3 CPUs. We highlight that more robust isolation or fine-grained randomization should be adopted to mitigate our presented attacks successfully.

Compound Memory Models

Today's mobile, desktop, and server processors are heterogeneous, consisting not only of CPUs but also GPUs and other accelerators. Such heterogeneous processors are starting to expose a shared memory interface across these devices.Given that each of these individual devices typically supports a distinct instruction set architecture and a distinct memory consistency model, it is not clear what the memory consistency model of the heterogeneous machine should be. In this paper, we answer this question by formalizing "compound" memory models: we present a compositional operational model describing the resulting model when devices with distinct consistency models are fused together. We instantiate our model with the compound x86TSO/PTX model -- a CPU enforcing x86TSO and a GPU enforcing the PTX model. A key result is that the x86TSO/PTX compound model retains compiler mappings from the language-based (scoped) C memory model. This means that threads mapped to the x86TSO device can continue to use the already proven C-to-x86TSO compiler mapping, and the same for PTX.

Server processor heat sink analysis and modifications to improve its thermal performance

Heat generation in the electronic components of high-performance computing servers is a matter of concern. Heat generation adversely affects the performance of these servers, certain temperature limits are required for these server processors and other electronic components to work within suitable conditions. Furthermore, in order to improve CPU performance and functioning, the heat flux in today's processor packages is increasing day by day, even as server CPUs and other components shrink in size. The air-cooling technique is the most broadly utilized and efficient technique of the present accessible electronic cooling advances. In data centers, heat sinks with forced air are utilized to keep server processors and other electronic components cool. The cooling systems of electronic gadgets are a growing field of research. The aim of this work is to contribute to this research field by investigating the effects of inlet air properties on server processor heat sink thermal performance with a heat load of 140 W. The heat sink performance depends on various parameters. The influence of various geometries of lateral perforation on heat sink fin walls was numerically analysed in this study to improve the thermal performance of the server processor plate fin heat sink. The CFD Solver is used for analysing the performance of heat sink and the effect of lateral perforation shapes on heat sink fins. The three shapes of perforation are considered as square, circular, and hexagonal types, with the same cross-sectional area and pitch of inline arrangement. In comparison to plate fin heat sinks, the numerical results demonstrate that a laterally perforated finned heat sink has a lower base temperature and a low thermal resistance. The use of a perforated heat sink also saves material and reduces the weight of the heat sink.

Earthquake Event Recognition on Smartphones Based on Neural Network Models.

Using sensors embedded in smartphones to study earthquake early warning (EEW) technology can effectively reduce the high construction and maintenance costs of traditional EEW systems. However, due to the impact of human activities, it is very difficult to accurately detect seismic events recorded on mobile phones. In this paper, to improve the detection accuracy of earthquakes on mobile phones, we investigated the suitability of different types of neural network models in seismic event detection. Firstly, we collected three-component acceleration records corresponding to human activities in various scenarios such as walking, running, and cycling through our self-developed mobile application. Combined with traditional strong-motion seismic event records fusing typical mobile phone accelerometer self-noise, all records were used for establishing the training and testing dataset. Finally, two types of neural network models, fully connected and convolutional neural networks, were trained, validated, and tested. The results showed that the accuracy rates of the neural network models were all over 98%, and the precision rate for seismic events and the recall rate for non-earthquake events could both reach 99%, indicating that the introduction of neural networks into the earthquake recognition on smartphones can significantly enhance the accuracy of seismic event recognition. Therefore, we can exceedingly reduce the amount of data transmitted to the processing server, further lowering the load on the server processor and effectively increasing the lead time at each target site for an EEW system.

More than Meets One Core: An Energy-Aware Cost Optimization in Dynamic Multi-Core Processor Server Consolidation for Cloud Data Center

The massive number of users has brought severe challenges in managing cloud data centers (CDCs) composed of multi-core processor that host cloud service providers. Guaranteeing the quality of service (QoS) of multiple users as well as reducing the operating costs of CDCs are major problems that need to be solved. To solve these problems, this paper establishes a cost model based on multi-core hosts in CDCs, which comprehensively consider the hosts’ energy costs, virtual machine (VM) migration costs, and service level agreement violation (SLAV) penalty costs. To optimize the goal, we design the following solution. We employ a DAE-based filter to preprocess the VM historical workload and use an SRU-based method to predict the computing resource usage of the VMs in future periods. Based on the predicted results, we trigger VM migrations before the hosts move into the overloaded state to reduce the occurrence of SLAV. A multi-core-aware heuristic algorithm is proposed to solve the placement problem. Simulations driven by the VM real workload dataset validate the effectiveness of our proposed method. Compared with the existing baseline methods, our proposed method reduces the total operating cost by 20.9~34.4%.

Modern server ARM processors for supercomputers: A64FX and others. Initial data of benchmarks

A comparative analysis of the performance of ARM server processors used on supercomputers or also aimed at high-performance computing (HPC) is given. Fujitsu A64FX, Marvell ThunderX2 and Huawei Kunpeng 920 were selected for the initial performance analysis. The HPC performance review focuses primarily on benchmarks and applications for the A64FX, which supports longer vectors than other ARM processors and has higher peak performance. The performance of the A64FX is compared against corresponding data for Intel Xeon Skylake and Cascade Lake, and AMD EPYC with Zen 2 and 3 (Roma and Milan), as well as Nvidia V100 and A100 GPUs. A short set of potential pros and cons of the A64FX microarchitecture has been formulated. Comparison of performance data obtained using different compilers for A64FX. Features have been formed when A64FX usually gives advantages in performance over x86-64, and when it concedes to x86-64.It is clear that the use of A64FX in supercomputers can grow further. There is an assumption that x86-64 hegemony in HPC will decrease, in particular, due to the increased use of server ARM processors. But the analysis of A64FX and new AArch64 processors expected in the near future showed that A64FX will not necessarily lead in this process.

COCKTAIL: Multicore Co-Optimization Framework With Proactive Reliability Management

High performance computing (HPC) servers aim to meet an increase in the number and complexity of tasks and, consequently, to address the energy efficiency challenge. In addition to energy efficiency, it is essential to manage lifetime limitations of power-hungry components of servers (e.g., cores and cache), hence avoiding server failure before its lifetime period. Traditional approaches focus on either using hybrid caches to reduce the leakage power of traditional static random-access memory (SRAM) cache, and thus increase the energy efficiency, or the trade-off between the lifetime and performance of multi-core processors. However, these approaches fall short in terms of flexibility and applicability for HPC tasks in terms of multi-parametric optimization including quality-of-service (QoS), lifetime reliability, and energy efficiency. As a result, in this paper we propose COCKTAIL, a holistic strategy framework to jointly optimize the energy efficiency of multi-core server processors and tasks performance in the HPC context, while guaranteeing the lifetime reliability. First, we analyze the best cache technology among traditional SRAM and resistive random access memory (RRAM), within the context of hybrid cache architectures, to improve the energy efficiency and manage cache endurance limits with respect to tasks requirements. Second, we introduce a novel efficient proactive queue optimization policy to reorder HPC tasks for execution considering their end time and possible reliability effects on the use of the hybrid caches. Third, we present a dynamic model predictive control (MPC)-based reliability management method to maximize task performance, by controlling the frequency, temperature, and target lifetime of the server processor. Our results demonstrate that, while consuming similar energy, COCKTAIL provides up to 60% QoS improvement when compared to latest state-of-the-art energy optimization and reliability management techniques in the HPC context. Moreover, our strategy guarantees a design lifetime longer than 5 years for the whole HPC system.

Kunpeng 920: The First 7-nm Chiplet-Based 64-Core ARM SoC for Cloud Services

Kunpeng 920 is the second generation server processor designed by HiSilicon based on ARM architecture. Kunpeng 920 is able to achieve cost efficiency for various workloads through using a variety of chiplets and hybrid process technologies. The unique recomposition(s) of these flexible chipsets allows new designs to be created. The Kunpeng series processors combine technology innovations from various levels to improve efficiency, eliminate bottlenecks, and deliver value and performance. Its key features are as follows: The Kunpeng 920 core is specifically designed with superscalar architecture with the support of vector extension to provide leading features for high-performance computing applications; the coherent cache subsystem is created to integrate multicores into single chiplet (e.g., 7-nm process node) with a ring design that is ultralow-latency (<; 15 ns), nonblocking and bufferless; a dedicated parallel small-IO block is developed to achieve high-bandwidth (e.g., 400 GB/s) interdie connection for 2-D package solutions; IO die is redesigned (e.g., 16-nm process) so that the latest standard interface (e.g., PCI4.0) can be leveraged to scale up the System on a Chip (SoCs) and connect them with other IO devices; two or four Kunpeng 920 can work together as single symmetric multiprocessor system with cache coherent nonuniform memory access fabric.

A Design Method for Low-cost and SOPC-based Flexible Lifting Control System

To efficiently reduce the development and production costs of the intelligent lifting control system, we introduce a design method for the intelligent lifting system with client-server architecture. We replace DSP processor core or DSP (Digital Signal processor) core with Nois II soft-core processor so that the design and production costs can be effectively cut. By replacing DSP processor or DSP processor core with Nois II soft-core processor, the design and production costs can be significantly reduced. In our design, loop vector control units work as a server processor, and a central computing unit with four independent multipliers and two adders is employed, with the implementation method based on a state machine. The experimental results prove effective in reducing resource requirements for FPGA (Field Programmable Gate Array), show that the proposed method can be successfully applied to the implementation of a complete intelligent flexible lifting control system on a low-end Altera Cyclone FPGA, and servo motor control achieves better dynamic performance

Open Source network boot server for low-cost computer network learning

Universities in developing countries must have innovative ways of educating students to anticipate higher education costs. Computer network courses require server and client computers that are not cheap in terms of hardware and software. The most vulnerable computer hardware is the Hard Disk Drive (HDD), while the very expensive operating system license cost often forces universities to keep using outdated operating systems. This study aims to build open source network boot server by using PXE, DNSMASQ, TFTP, Casper and NFS. The PXE, DNSMASQ, TFTP, Casper and NFS will work together to become Open Source Network Boot Server (OSNBS). We conducted a simulation to measure the client boot speed from the network by using five clients and two versions of the uBuntu operating system image that have the capability of being a tool for computer networking courses. In addition, the processor server and hard disk server will be further monitored and analyzed. The simulation were carried out using virtualization on a desktop computer. We found that all clients successfully booted from the network. The latest uBuntu operating system image can efficiently improve the use of server resources for the processor and hard drive. In addition, the use of open source operating systems and existing hardware have also significantly reduced IT expenditure. This finding reinforces that OSNBS is suitable for low-cost computer network learning.

Marvell ThunderX3: Next-Generation Arm-Based Server Processor

Marvell ThunderX3 is the third-generation Arm-based server processor from Marvell. This article describes the architecture of ThunderX3, going into details of core microarchitecture. ThunderX3 is distinctive among mainstream processors in supporting four SMT threads. The article describes the threading microarchitecture of ThunderX3 and highlights threading benefits. The article also touches on the on-chip interconnect and L3-cache and the power management subsystem. Initial benchmark results from silicon show 30%+ single thread and up to 3X socket level performance gains over the prior generation resulting in industry-leading single thread and socket level performance.

A 2.46M Reads/s Seed-Extension Accelerator for Next-Generation Sequencing Using a String-Independent PE Array

Advances in DNA-sequencing technology have far outpaced Moore's law, imposing significant challenges on the computationally intensive secondary analysis in the sequencing pipeline. An accelerator for seed extension, a critical and computationally intensive step in genome sequencing, is proposed. The accelerator, implementing a string-independent automata, consists of a triangular array of $25\times 2$ custom-designed processing elements. It performs 2.46 million reads per second (MRPS), achieving a $1581\times $ improvement in power efficiency and $165.5\times $ smaller silicon footprint compared to a system setting with dual-socket Xeon E5-2697 v3 server processors.

Fast LSTM by dynamic decomposition on cloud and distributed systems

Long short-term memory (LSTM) is a powerful deep learning technique that has been widely used in many real-world data-mining applications such as language modeling and machine translation. In this paper, we aim to minimize the latency of LSTM inference on cloud systems without losing accuracy. If an LSTM model does not fit in cache, the latency due to data movement will likely be greater than that due to computation. In this case, we reduce model parameters. If, as in most applications we consider, the LSTM models are able to fit the cache of cloud server processors, we focus on reducing the number of floating point operations, which has a corresponding linear impact on the latency of the inference calculation. Thus, in our system, we dynamically reduce model parameters or flops depending on which most impacts latency. Our inference system is based on singular value decomposition and canonical polyadic decomposition. Our system is accurate and low latency. We evaluate our system based on models from a series of real-world applications like language modeling, computer vision, question answering, and sentiment analysis. Users of our system can use either pre-trained models or start from scratch. Our system achieves 15 $$\times $$ average speedup for six real-world applications without losing accuracy in inference. We also design and implement a distributed optimization system with dynamic decomposition, which can significantly reduce the energy cost and accelerate the training process.

Bridging the Architecture Gap: Abstracting Performance-Relevant Properties of Modern Server Processors

We describe a universal modeling approach for predicting single- and multicore runtime of steady-state loops on server processors. To this end we strictly differentiate between application and machine models: An application model comprises the loop code, problem sizes, and other runtime parameters, while a machine model is an abstraction of all performance-relevant properties of a CPU. We introduce a generic method for determining machine models and present results for relevant server-processor architectures by Intel, AMD, IBM, and Marvell/Cavium. Considering this wide range of architectures, the set of features required for adequate performance modeling is surprisingly small. To validate our approach, we compare performance predictions to empirical data for an OpenMP-parallel preconditioned CG algorithm, which includes compute- and memory-bound kernels. Both single- and multicore analysis shows that the model exhibits average and maximum relative errors of 5% and 10%. Deviations from the model and insights gained are discussed in detail.

A Dynamic Control System for Server Processor Direct Liquid Cooling

Direct liquid cooling enables the development of IC, especially processors in servers, toward higher density, which demands more efficient means of heat removal. To exploit the capability, the control system that dynamically balances between cooling power and energy consumption is critical to operational safety and cost. This article presents the design, implementation, and characteristic of a dynamic control system for server processor direct liquid cooling in a high-density data center. The controller was trained and deployed in an online–offline structure. The loss function to train this model was built based on the model predictive control (MPC) principle. To simplify the complex physical model, a hybrid model with a nonlinear steady-state term and a linearized transient term was extracted. We used both averaged overheat and ratio of pumping power consumption to evaluate the performance of controllers. Benchmark tests on open- and closed-loop controllers were conducted. The results showed the advantages of the deep explicit MPC (DEMPC) in terms of cooling effectiveness and energy efficiency. The normalized pumping energy consumption of DEMPC reached $2.3\times 10^{-4}$ with the mean overheat level of −0.96 °C and the overheat time percentage of 6.5%. Comparing with open-loop control that has similar normalized energy costs, the mean overheat level was reduced by 1.2 °C and the time percentage of overheat was reduced by eight times. Meanwhile, normalized energy consumption was reduced by 21.7% than closed-loop proportional control who has a similar average overheat level and overheat time percentage.

Application-driven Cache-Aware Roofline Model

In the coming exascale era, the complexity of modern applications and hardware resources imposes significant challenges for boosting the efficiency via execution fine-tuning. To abstract this complexity in an intuitive way, recent application analysis tools rely on insightful modeling, e.g., Intel® Advisor with Cache-aware Roofline Model. However, these approaches mainly consider the maximum architecture capabilities, which may limit their usability when characterizing real-world applications. To address this issue, a novel Cache-Aware Roofline Model for more accurate performance modeling of multi-cores is proposed, which realistically resembles application requirements. The proposed fine-grain modeling relies on micro-benchmarking to decouple the attainable performance of the micro-architecture for different utilization scenarios and for a diverse set of functional units and memory levels. Memory sub-system traffic simulation, dynamic and static analyses are also used to derive the requirements of the applications. Experimental results for a real multi-core system with an Intel server processor and for a set of 13 kernels from exascale proxy applications, show that the proposed models provide more accurate application characterization, optimization hints and bottleneck detection in comparison to the state-of-the-art models.