Semiconductor Manufacturing Systems Research Articles

3717 ニューラルネットワークを用いた半導体生産システムのリアルタイムスケジューリング : ボトルネック機械に着目した簡易モデルによる学習(S66-2 生産システムの新展開(基礎理論)(2),S66 生産システムの新展開(基礎理論))

In this paper, we apply a neural network to the real-time scheduling of a semiconductor manufacturing system. Because it is very difficult to train the neural network using the model of large-scale semiconductor manufacturing systems, we use a simplified model for training. Numerical experiments show the effectiveness of the proposed method.

Single-station performance evaluation and improvement in semiconductor manufacturing: A graphical approach

The relationships between key indicators of manufacturing system performance, such as cycle time (CT), throughput (TH), utilization, work-in-process (WIP), and the variability factor (to be defined shortly in the text), are complicated and difficult to quantify. In most cases, manufacturing managers cannot optimize one characteristic without adversely affecting another. For example, in order to reduce inventory and shrink time-to-market, one may need to lower the WIP level to reduce CT; however, too much WIP reduction can lead to unexpected station starvation (stoppage) and, thus, degrade TH. Low utilization of expensive equipment is also unacceptable, especially for advanced semiconductor manufacturing. This challenge caused difficulties for Chinese companies to keep up with the pace of China's development in becoming a global manufacturing center. To assist manufacturing managers in improving manufacturing system performance, we developed a graph decision aid for single-station semiconductor manufacturing systems.

Internal transport in automated semiconductor manufacturing systems

This paper summarizes the main results presented by the author in his PhD thesis (Montoya-Torres 2005), supervised by Stephane Dauzeere-Peres, Jean-Pierre Campagne and Helene Marian, and defended on 29 November 2005 at the Ecole des Mines de Saint-Etienne and Universite Jean-Monnet. The thesis is written in French and is available upon request from the author. This work deals with a real-life transportation problem in the semiconductor industry. It proposes a new approach by integrating tactical and operational decisions for the control of the automated transport system. At the tactical level, the problem is modeled using integer linear programming models inspired from Location Theory. At the operational level, the solution obtained from the tactical optimization is coupled with a discrete-event computer simulation program and some policies for transportation operations are implemented and compared.

A study on the weighted composite dispatching rule in modular production systems

Scheduling semi-conductor manufacturing process systems is a complicated and difficult job, due to such characteristics as re-entry into manufacturing processes, high uncertainty of processes, and products and technologies changing rapidly. The researchers have carried out many studies to find efficient techniques for semi-conductor manufacturing systems with a view to accomplishing the goals of systems, such as saving cycling time and increasing production quantity per unit time. The production flow in the semi-conductor industry has the most unique characteristics, which makes it difficult to plan production and to schedule semi-conductor manufacturing. Currently, the scheduling methods in semi-conductor assembly processes follow the dispatching rule on a simple first come first serve (FCFS) basis, and a backlog is operated as a buffer based on the daily production quantity. In this study, therefore, we will apply various dispatching rules on a real-time basis and verify the effect and result of exact scheduling through simulation, based on the assumption that competitive advantages in production come from efficient inventory control and exact scheduling.

2102 ニューラルネットワークによる半導体生産システムのリアルタイムスケジューリング(OS2 生産スケジューリング)

In this paper, we apply a neural network to the real-time scheduling of a semiconductor manufacturing system. Because it is very difficult to train the neural network using large-scale semiconductor manufacturing systems, we use a small-scale model of the manufacturing system for training. In order to compensate for the discrepancy between the models, a target-cycle-time tunable after training is used for scheduling. Numerical experiments show that the proposed method outperforms the dispatching rule proposed in the literature.

2107 半導体生産システムにおける遺伝的機械学習を用いた適応的ロット投入(OS2 生産スケジューリング)

2107 半導体生産システムにおける遺伝的機械学習を用いた適応的ロット投入(OS2 生産スケジューリング)

1011 ニューラルネットワークを用いた半導体生産システムのリアルタイムスケジューリング(生産加工・工作機械III,生産システムII)

1011 ニューラルネットワークを用いた半導体生産システムのリアルタイムスケジューリング(生産加工・工作機械III,生産システムII)

Run-to-Run Overlay Control of Steppers in Semiconductor Manufacturing Systems Based on History Data Analysis and Neural Network Modeling

This paper presents a new run-to-run control scheme to reduce overlay misalignment errors in steppers and demonstrates the feasibility of the scheme by real-time experimental tests. The overlay misalignment error mainly depends on two factors: one is the internal dynamics of photo processes and steppers and the other is the process history of lots, such as base equipment and reticles. Based on these observations, a new control scheme was designed to find the stepper inputs minimizing the misalignment errors based on history data analysis and neural network models. Moreover, we demonstrated that the proposed control scheme reduces the spec-out ratios as well as the number of engagements of the send-ahead wafer process, which thereby results in the increase of product yield in semiconductor manufacturing.

An Extended Event Graph With Negative Places and Tokens for Time Window Constraints

We introduce places with negative holding times and tokens with negative token counts into a timed event graph in order to model and analyze time window constraints. We extend the enabling and firing rules for such an extended event graph named a negative event graph (NEG). We develop necessary and sufficient conditions based on the circuits for which the NEG is live, that is, an infinite sequence of feasible firing epochs exist for each transition. We prove that the minimum cycle time is the same as the maximum circuit ratio of the circuits with positive token counts. We also show that when there exists circuits with negative token counts, the maximum cycle time is bounded and the same as the minimum circuit ratio of such circuits. A scheduling example for a robot-based cluster tool with wafer residency time constraints for semiconductor manufacturing is explained. Note to Practitioners-Scheduling and control problems for modern man-made systems, including automated manufacturing systems such as cluster tools for semiconductor manufacturing, microcircuits, and real-time software systems, are usually modeled as discrete event systems. Such systems often have strict time constraints on timings of some events. Our results can be used for identifying whether there can be a feasible schedule that satisfies all time constraints, computing the range of the feasible cycle times, and determining a steady schedule with the minimum cycle time. By using the feasibility condition, we also can accommodate the system configuration, the task times, and the task sequence so that the system can satisfy the time constraints while meeting the target cycle time. Such practice is already used for real cluster tool engineering. We have more results on implementing a real-time scheduler and controller for time constrained systems.

Dispatching of overhead hoist vehicles in a fab intrabay using a multimission-oriented controller

The semiconductor manufacturing system has become one of the most important manufacturing systems in recent years. Intrabay automation for wafer transport is in high demand in a 300 mm foundry fab. The control of the transport system plays an important roles in manufacturing efficiency and the satisfaction of production strategy. In general, efficiency is the most important issue that has appeared in most research of automated transport systems. However, how to dynamically adjust the transport policy to meet the production strategy and to increase the transport efficiency as well seems to be more crucial to modern semiconductor manufacturing systems. In this paper, a fuzzy-logic-based multimission-oriented overhead vehicle dispatcher is developed. The vehicle dispatching rule is assigned in real-time according to the statistics of the manufacturing performance. In this manner, the dispatching rules can be adjusted according to possible high-risk lots so that most of the production strategies can be satisfied. If all of the lots meet the prescribed production strategies, then the nearest-job-first rule can be used to offer higher transport efficiency. In addition, the proposed vehicle dispatcher is also capable of deadlock-free operation, collision avoidance, and blockage prevention. Finally, this paper uses AutoMod simulation software to construct and evaluate the manufacturing models. By evaluating the simulation results, the proposed intelligent multimission-oriented vehicle dispatcher performs better performance than the others, and all of the production strategies are satisfied .

An approach to regulating machine sharing in reconfigurable back-end semiconductor manufacturing

By complying with the operational philosophy of virtual production lines, a back-end semiconductor manufacturing system can be controlled and managed with better reconfigurability. However, due to the absence of a fully-integrated information system and the gaining popularity of distributed computing, machine reconfiguration decisions are made by machine controllers on the shop floor where heterarchical control architecture is typically used. This research investigates how non-cooperative game theory could be applied for facilitating the decision process reconfiguration decision-making at the machine controller level as machines are competed by multiple jobs streams. This paper presents how material flow traffic can be better regulated in a reconfigurable manufacturing environment. A study using an industrial pilot system is discussed to demonstrate the applicability of the proposed approach, in which heuristics are used to determine the game specification.

Virtual production line based WIP control for semiconductor manufacturing systems

The explosive growth of data acquisition and increasing number of machining processes makes extremely difficult to deliver precise information to the proper users at the right time by relying on a centralized work-in-process (WIP) control system in manufacturing. This article presents a potentially practical solution to a manageable and well-distributed WIP control system by addressing issues such as real time performance, scalability, and reconfigurability. By taking advantage of the advances in distributed computing technologies multiple WIP control instances performing different subsets of control and management responsibilities can be spawned from a server repository, running on geographically dispersed networked computers. These spawned WIP control instances are coordinated and synchronized using the concept of virtual production lines (VPLs). WIP control algorithms for implementing real time “pull” operations, leveraging WIP levels, and resolving resource sharing are proposed. Certain validation has been conducted in an industrial testbed to confirm the applicability of the proposed VPL-based WIP control solution.

半導体生産システムにおける強化学習を用いた適応的製品投入計画(ソフト人工物II)

Semiconductor manufacturing systems are typical example of complex manufacturing systems because of the number of the facility and the complex process flow of the products. Effective lot release scheduling is needed to realize efficient facility utilization and flexibility for multi-product production in such complex manufacturing systems. This paper proposes an adaptive lot release method applying the lot release scheduler using reinforcement learning. The scheduler acquires suitable rules that decide lot release timing based on the state of the WIP (Work-In-Process) distribution in the production floor. Computer simulations are also executed to confirm the effectiveness of the proposed method.

ERCN* Merged Nets for Modeling Degraded Behavior and Parallel Processes in Semiconductor Manufacturing Systems

This paper presents a new class of well-behaved Petri nets called resource control net (ERCN*) merged nets that generalize the class of ERCN merged nets proposed in a previous paper by Xie and Jeng. ERCN merged nets can model parallel and synchronized processes in semiconductor manufacturing such as lot split and lot merging, which occurs frequently in a research and development (R&D) semiconductor fab (semiconductor plant) for engineering purposes. However, processing cycles for each resource type must include the initial state of the resource type. In other words, no local processing cycles are allowed. This makes the modeling of degraded behavior in semiconductor manufacturing such as rework, failure, and maintenance difficult. In the current work, this constraint is relaxed under the extended free-choice (EFC) or asymmetric choice (AC) condition. Specifically, for each operation place with degrading outgoing arcs, the FC or AC condition is satisfied. In addition, degraded behavior is modeled as blocks within ERCNs. We show that conditions for liveness and reversibility of an ERCN* merged net correspond to the absence of unmarked siphons. The well-behaved conditions can be transformed into inequalities of the initial marking. Examples are shown to illustrate the proposed methodology.

多品種半導体生産システムにおけるレイアウトの自己組織化(ソフト人工物II)

多品種半導体生産システムにおけるレイアウトの自己組織化(ソフト人工物II)

Virtual production lines design for back-end semiconductor manufacturing systems

This paper introduces the virtual production line (VPL) concept, which initiates a new method to model the shop floor from both control and management point of view. Heuristic algorithms are presented to dynamically configure a large system into many VPLs, which ensure the line balance and efficiency, and accurately predicate the completion time for each work-order. The proposed methodology and algorithms are demonstrated through a simplified back-end semiconductor manufacturing system.

Parallel machine scheduling with earliness–tardiness penalties and additional resource constraints

This research considers the problem of scheduling jobs on parallel machines with noncommon due dates and additional resource constraints. The objective is to minimize the total absolute deviation of job completion times about the corresponding due dates. All job processing times are assumed to be the same. This problem is motivated by restrictions that occur in the handling and processing of jobs in certain phases of semiconductor manufacturing and other production systems. We examine two special cases. For the first of these, the number of additional resource types and the resource requirements per job are arbitrary. The problem is formulated as a zero–one integer linear program and the Lagrangian relaxation approach is used to obtain tight lower bounds. In the second case, there exist one single type of additional resource and the resource requirements per job are zero or one. This problem is shown to be equivalent to the asymmetric assignment problem. Scope and purpose This paper considers the problem of scheduling jobs on parallel machines where jobs have different due dates and may require, besides machines, certain additional limited resources for their handling and processing. The objective is to minimize the total absolute deviation of job completion times about the corresponding due dates. This objective function is consistent with the just-in-time production philosophy which espouses the notion that earliness as well as tardiness should be penalized. Two problems are addressed. In the first of these, the number of different types of additional resources and resource requirements per job are arbitrary. The problem is formulated as a zero–one integer linear program and the Lagrangian relaxation approach is used. In the second problem, there exists one single type of additional resource and the resource requirements per job are zero or one. This problem can be reformulated as an assignment problem.

Selection of dispatching rules on multiple dispatching decision points in real-time scheduling of a semiconductor wafer fabrication system

Semiconductor wafer fabrication involves one of the most complex manufacturing processes ever used. To control such complex systems, it is a challenge to determine appropriate dispatching strategies under various system conditions. Dispatching strategies are classified into two categories: a vehicle-initiated dispatching policy and a machine-initiated dispatching policy. Both policies are important to improve the system performance, especially for the real time control of the system. However, there has been little research focusing on combining them under various situations for the semiconductor manufacturing system. In addition, it is shown that no single dispatching strategy consistently dominates others in all situations. Therefore, the goal of this study is to develop a scheduler for selection of dispatching rules for dispatching decision variables in order to obtain the desired performance measures given by a user for each production interval. For the proposed methodology, simulation and competitive neural network approaches are used. The results of the study indicate that applying our methodology to obtaining a dispatching strategy is an effective method considering the complexity of semiconductor wafer fabrication systems.

Determining operating criterion of batch processing operations for wafer fabrication

All semiconductor manufacturing systems involve batch processing operations. These operations can have a significant impact on product cycle times. Semiconductor manufacturers are often interested in batch processing policies that minimize the sum of the weighted cycle time of all products, where the weights indicate the priority levels of products. A well-known minimum batch size (MBS) policy is generally recognized as an effective policy. However, there is no guideline in determining the minimum batch sizes to start batch processing operations for this policy. This paper illustrates the use of an analytical queuing model to determine these minimum batch sizes. Illustrations of the effectiveness of the approach are provided through a comparison simulation study of various batch processing policies of a real-world semiconductor manufacturer with multiple products and with small to medium volumes. The comparison results suggest that using an analytical queuing model to determine batch sizes for the MBS policy gives a better minimum sum of the weighted cycle time of all products than the other policies considered.

A simulation based analysis of cycle time distribution, and throughput in semiconductor backend manufacturing

This paper presents a preliminary analysis of the relationship between selected input and output variables in semiconductor backend manufacturing system, using a data driven discrete event simulation model. This study is of interest and importance for a better understanding of the controllable input variables in an effort to reduce factory cycle time and distribution. Our analysis quantifies the effect of varying the input variables of lot release controls, heuristic machine dispatching rules, elimination of selected processes, material handling time, set-up time, and machine up time on selected output variables of throughput, cycle time and cycle time spread. Simulation model of a semiconductor site based in Singapore is used as the base case and the effects are quantified against the base model.