Semiconductor Intellectual Property Research Articles

Value Creation Analysis: Semiconductor Intellectual Property Business Models and Dynamic Capabilities

Semiconductor intellectual property (SIP) represents a crucial component of integrated circuit design activities. However, many small SIP firms fail to create value and adopt a viable business model. This article aims to investigate the value creation mechanism within the SIP business by drawing on the business model and dynamic capabilities views of the firm. First, the authors classify the forms and types of SIP from a technology and market perspective. Analyzing ten leading SIP firms, three SIP business models based on resources, competencies, and strategies are then identified. Dynamic capabilities are then linked to the selection and implementation of classified business models. Findings of the study suggest that existing SIP business models primarily favor large vendors. Keystone business model is proposed as a possible successful business model for small vendors. Consequently, this article provides insights and opportunities for leveraging the SIP ecosystem and business model innovation for small firms in the industry.

The European Factor: From ARM to Atos

Reports on ARM, a 30-year-old U.K.-based semiconductor Intellectual Property (IP) company that started as Advanced RISC Machines Ltd., a joint venture that included former U.K. company Acorn Computers, Apple Computers (now Apple Inc.),1 and VLSI Technology (a US company later bought by Phillips for USD 1 billion and now part of the Philips spin-off NXP Semiconductors). ARM was bought in 2016 by the Japanese conglomerate and investing company Softbank Group, which also has a main stake in US Sprint and also has significant T-Mobile stock via the merger of Sprint and T-Mobile that was completed in April 2020. In September 2020, NVIDIA announced that it is buying ARM,2 but it may take time to complete since it is running into some licensing issues regarding its subsidiary ARM-China. Unlike Intel, AMD, and Freescale, ARM does not produce any computer chips, but licenses its architecture designs and product ecosystem to other vendors.

CAS-Lock: A Security-Corruptibility Trade-off Resilient Logic Locking Scheme

Logic locking has recently been proposed as a solution for protecting gatelevel semiconductor intellectual property (IP). However, numerous attacks have been mounted on this technique, which either compromise the locking key or restore the original circuit functionality. SAT attacks leverage golden IC information to rule out all incorrect key classes, while bypass and removal attacks exploit the limited output corruptibility and/or structural traces of SAT-resistant locking schemes. In this paper, we propose a new lightweight locking technique: CAS-Lock (cascaded locking) which nullifies both SAT and bypass attacks, while simultaneously maintaining nontrivial output corruptibility. This property of CAS-Lock is in stark contrast to the well-accepted notion that there is an inherent trade-off between output corruptibility and SAT resistance. We theoretically and experimentally validate the SAT resistance of CAS-Lock, and show that it reduces the attack to brute-force, regardless of its construction. Further, we evaluate its resistance to recently proposed approximate SAT attacks (i.e., AppSAT). We also propose a modified version of CAS-Lock (mirrored CAS-Lock or M-CAS) to protect against removal attacks. M-CAS allows a trade-off evaluation between removal attack and SAT attack resiliency, while incurring minimal area overhead. We also show how M-CAS parameters such as the implemented Boolean function and selected key can be tuned by the designer so that a desired level of protection against all known attacks can be achieved.

A Hardware Efficient Watermarking Technique Based on LFSR

Watermarking has been used for many years to protect data in the form of images, text etc. With the increasing use of semiconductor Intellectual Property(IPs) by industries to develop various products, this concept of watermarking has been applied by semiconductor industries as well to protect the VLSI designs which use these semiconductor IPs. There are many watermarking techniques for IP protection of VLSI designs, out of which watermarking of Finite State Machine(FSM) based design is research area. Watermarking technique implemented in this paper uses a Linear Feedback Shift Register (LFSR) to watermark a FSM based design. The LFSR based watermarking is applied successfully on a sequence detector and is compared with other FSM watermarking techniques. The simulation and synthesis of LFSR based watermarking is performed using ModelSim and Xilinx ISE tool respectively. Results show improvement in Hardware utilization as compared to other FSM watermarking techniques available in literature.

Covert Gates: Protecting Integrated Circuits with Undetectable Camouflaging

Integrated circuit (IC) camouflaging has emerged as a promising solution for protecting semiconductor intellectual property (IP) against reverse engineering. Existing methods of camouflaging are based on standard cells that can assume one of many Boolean functions, either through variation of transistor threshold voltage or contact configurations. Unfortunately, such methods lead to high area, delay and power overheads, and are vulnerable to invasive as well as non-invasive attacks based on Boolean satisfiability/VLSI testing. In this paper, we propose, fabricate, and demonstrate a new cell camouflaging strategy, termed as ‘covert gate’ that leverages doping and dummy contacts to create camouflaged cells that are indistinguishable from regular standard cells under modern imaging techniques. We perform a comprehensive security analysis of covert gate, and show that it achieves high resiliency against SAT and test-based attacks at very low overheads. We also derive models to characterize the covert cells, and develop measures to incorporate them into a gate-level design. Simulation results of overheads and attacks are presented on benchmark circuits.

Identification of interrelationship of key customers’ needs based on structural model for services/capabilities provided by a Semiconductor-Intellectual-Property Mall

The semiconductor industry is shifting towards innovation and acquisition of intellectual property. Semiconductor-Intellectual-Property (SIP) design, a new industry, is also rapidly growing. This challenges both providers and users to develop infrastructure and standard interfaces. Establishing an SIP Mall to provide a full array of SIP business services is a new concept used to promote growth of the SIP industry. Many foundries and governments have been involved in setting up SIP Malls; however, the major services needed for an SIP Mall to attract SIP providers and SIP users must still be clarified. In this paper, the DEMATEL (DEcision MAking Trial and Evaluation Laboratory) method was used to discover and illustrate the key services needed to attract SIP users and SIP providers to an SIP Mall. Research enabled the derivation of the interrelated services and the structural interrelationship between them using the DEMATEL method. Overall, four key services were found to be vital for an SIP Mall to attract customers and to allocate resources efficiently.

Identification of a threshold value for the DEMATEL method using the maximum mean de-entropy algorithm to find critical services provided by a semiconductor intellectual property mall

To deal with complex problems, structuring them through graphical representations and analyzing causal influences can aid in illuminating complex issues, systems, or concepts. The DEMATEL method is a methodology which can confirm interdependence among variables and aid in the development of a chart to reflect interrelationships between variables, and can be used for researching and solving complicated and intertwined problem groups. The end product of the DEMATEL process is a visual representation—the impact-relations map—by which respondents organize their own actions in the world. In order to obtain a suitable impact-relations map, an appropriate threshold value is needed to obtain adequate information for further analysis and decision-making. In the existing literature, the threshold value has been determined through interviews with respondents or judged by the researcher. In most cases, it is hard and time-consuming to aggregate the respondents and make a consistent decision. In addition, in order to avoid subjective judgments, a theoretical method to select the threshold value is necessary. In this paper, we propose a method based on the entropy approach, the maximum mean de-entropy algorithm, to achieve this purpose. Using a real case to find the interrelationships between the services of a Semiconductor Intellectual Property Mall as an example, we will compare the results obtained from the respondents and from our method, and show that the impact-relations maps from these two methods could be the same.

Design of an Interconnect Architecture and Signaling Technology for Parallelism in Communication

The need for efficient interconnect architectures beyond the conventional time-division multiplexing (TDM) protocol-based interconnects has been brought on by the continued increase of required communication bandwidth and concurrency of small-scale digital systems. To improve the overall system performance without increasing communication resources and complexity, this paper presents a cost-effective interconnect architecture, communication protocol, and signaling technology that exploits parallelism in board-level communication, resulting in shorter latency and higher concurrency on a shared bus or link: the proposed source synchronous CDMA interconnect (SSCDMA-I) enables dual concurrent transactions on a single wire line as well as flexible input/output (I/O) reconfiguration. The SSCDMA-I utilizes 2-bit orthogonal CDMA coding and a variation of source synchronous clocking for multilevel superposition; a single 3-level SSCDMA-I line operates as if it consists of dual virtual time-multiplexed interconnects, which exploits communication parallelism with a reduced number of pins, wires, and complexity. The unique multiple access capability of the SSCDMA-I improves real-time communication between multiple semiconductor intellectual property (IP) blocks on a shared link or bus by reducing the bus contention interference from simultaneous traffic requests and by taking advantage of shorter request latency. The prototype transceiver chip is implemented in 0.18-m CMOS and the 10-cm test PC board system achieves an aggregate data rate of 2.5 Gb/s/pin between four off-chip (2Tx-to-2Rx) I/Os.

Opening up the black box [IP encryption

Since semiconductor intellectual property (IP) first emerged on the integrated circuit (IC) design scene over a decade ago, it has offered the promise of shaving months off of development time while allowing for the inclusion of many more functions in a design. At the heart of the problem is the need by IP providers to protect their development investment. Few IC designers can afford to pay the often high price for access to IP source code, so IP suppliers provide significantly less costly 'black box', or encrypted, versions for use with specific design tools. The problem with this is not only that the IP vendor is saddled with the cumbersome task of maintaining multiple IP core versions for various tool sets, but, more importantly, that it is an incomplete solution. To address the need for a means to protect IP from piracy while making it easier for the IF supplier to deploy and the IC designer to use, Synplicity has developed and introduced an open IP encryption/decryption methodology. It takes advantage of features in the most recent release of Verilog and commonly used encryption mechanisms in a new usage model that could become an industry standard.

A clock-tuning circuit for system-on-chip

System-on-chip (SoC) design depends heavily on effective reuse of semiconductor intellectual property (IP). Clock distribution has become a problem for integrating IP cores into a single synchronous SoC, because of different clock delays in the IP cores. We propose an on-chip clock-tuning circuit, which enhances design flexibility. Programmable delays are inserted in the clock distribution network, such that clock alignment and synchronization are achieved. Design iterations are eliminated with the use of the tuning circuit, saving design effort, and cost. The method is also applicable to compensating for unbalanced clock trees. Hierarchical clock tuning can be implemented and can take advantage of the hierarchical structure of the SoC. Skew analysis has shown that the added programming unit outperforms other clock design options. The method was implemented in a commercial chip, and demonstrated good functionality with high productivity of the design flow.

Defying hard times [semiconductor intellectual property business

The article discusses the challenges facing the semiconductor intellectual property business from the perspective of ARC International. ARC has been working hard to strengthen its position as a one-stop-shop SIP supplier with a highly distinctive processor technology. It is operating in a crowded and highly competitive market. ARC gains an edge on its rivals by virtue of its Tangent reconfigurable processor and by positioning itself as a supplier of integrated system solutions. Using the ARChitect point-and-click configuration tool, customers can fine-tune the parameters of their processor, for example by selecting the size of the data and instruction caches. There is also the opportunity to make customer-specific additions to the instruction set, an option taken up in around 20% of designs. Following a programme of acquisitions, ARC now complements its processor cores with a range of application-specific SIP products supporting USB, Ethernet and 802.11 wireless LANs.

Set-top box system-on-chip design methodology

Reviews how the methodology for semiconductor intellectual property (IP) reuse for system-on-chip (SoC) designs has evolved from its first introduction. It has gone from an approach based largely on IP reuse to a state of-the-art design flow based on soft and hard IP blocks and floorplanning tools. This flow will be illustrated in one complex SoC present in the broadband communication market today, which is a set-top box IC containing a proprietary 64-bit processor and some general-purpose blocks, along with dedicated functions specifically designed by STMicroelectronics. Management of a design of this SoCs complexity is based on a top-down, block-based design style, including automatic floorplanning. This design style makes use of the classic divide-and-conquer strategy and enables a concurrent development process, guaranteeing timing convergence and correct chip assembly.

Generic architecture and semiconductor intellectual property cores for advanced encryption standard cryptography

A generic architecture for implementing the advanced encryption standard (AES) encryption algorithm in silicon is proposed. This allows the instantiation of a wide range of chip specifications, with these taking the form of semiconductor intellectual property (IP) cores. Cores implemented from this architecture can perform both encryption and decryption and support four modes of operation: (i) electronic codebook mode; (ii) output feedback mode; (iii) cipher block chaining mode; and (iv) ciphertext feedback mode. Chip designs can also be generated to cover all three AES key lengths, namely 128 bits, 192 bits and 256 bits. On-the-fly generation of the round keys required during decryption is also possible. The general, flexible and multi-functional nature of the approach described contrasts with previous designs which, to date, have been focused on specific implementations. The presented ideas are demonstrated by implementation in FPGA technology. However, the architecture and IP cores derived from this are easily migratable to other silicon technologies including ASIC and PLD and are capable of covering a wide range of modern communication systems cryptographic requirements. Moreover, the designs produced have a gate count and throughput comparable with or better than the previous one-off solutions.