Semiconductor Capacitor Structures Research Articles

Atomic layer deposition of Y2O3 as high-k dielectrics by using a heteroleptic yttrium precursor and water

Atomic layer deposition (ALD) of Y2O3 thin films was performed on Si substrate by pulsing an unconventional heteroleptic yttrium precursor Y(MeCp)2(Me2Pz) and H2O alternatively. The thin film grew 0.26–0.28 Å per cycle at relatively low temperature of 195–225 °C in a self-limiting manner with negligible nucleation delay, and is close to stoichiometric (O/Y = 1.48, C, 2.56 at%; N, 1.81 at%) in as-deposited form. Integration of the post-annealed ALD Y2O3 film in a metal oxide semiconductor (MOS) capacitor structure exhibits representative electrical properties including a high dielectric constant k of 11.4, high electrical breakdown field of 6.1 MV cm−1 and low leakage current density of 9.1 × 10−8 A cm−2 at − 2 MV cm−1.

Synaptic Plasticity Modulation of Neuromorphic Transistors through Phosphorus Concentration in Phosphosilicate Glass Electrolyte Gate.

This study proposes a phosphosilicate glass (PSG)-based electrolyte gate synaptic transistor with varying phosphorus (P) concentrations. A metal oxide semiconductor capacitor structure device was employed to measure the frequency-dependent (C-f) capacitance curve, demonstrating that the PSG electric double-layer capacitance increased at 103 Hz with rising P concentration. Fourier transform infrared spectroscopy spectra analysis facilitated a theoretical understanding of the C-f curve results, examining peak differences in the P-OH structure based on P concentration. Using the proposed synaptic transistors with different P concentrations, changes in the hysteresis window were investigated by measuring the double-sweep transfer curves. Subsequently, alterations in proton movement within the PSG and charge characteristics at the channel/PSG electrolyte interface were observed through excitatory post-synaptic currents, paired-pulse facilitation, signal-filtering functions, resting current levels, and potentiation and depression characteristics. Finally, we demonstrated the proposed neuromorphic system's feasibility based on P concentration using the Modified National Institute of Standards and Technology learning simulations. The study findings suggest that, by adjusting the PSG film's P concentration for the same electrical stimulus, it is possible to selectively mimic the synaptic signal strength of human synapses. Therefore, this approach can positively contribute to the implementation of various neuromorphic systems.

Investigating the effect of aluminum oxide fixed charge on Schottky barrier height in molybdenum oxide-based selective contacts

A tunneling atomic layer deposited (ALD) AlOx layer was inserted in a Si|SiOx|AlOx|MoOx|metal tunnel diode structure to investigate the impact of fixed interface charge on Schottky barrier height. ALD AlOx provides a synthesis-tunable fixed charge and can provide excellent field effect passivation at the SiOx|AlOx interface. A large (>1 × 1012 q.cm−2) negative fixed charge density was expected to decrease Schottky barrier height on p-type silicon and increase Schottky barrier height on n-type silicon by up to 0.4 eV based on an electrostatic model. Fixed charge density and interface trap state density were measured using a thick layer of AlOx in metal oxide semiconductor capacitor structures (MOSCAPs); Schottky barrier height and specific contact resistivity were measured using a tunneling-active layer of AlOx in contacted structures with MoOx. In some samples, HfOx interface layers were inserted between AlOx and silicon to quench the fixed negative charge. The Schottky barrier height was found to vary with processing conditions but did not have a strong correlation with expected fixed charge density. Thus, while fixed charge may play a role in determining the Schottky barrier height, other parameters also have significant affect. Further work is needed to minimize contact resistivity and elucidate other factors impacting the Schottky barrier height.

Observation of MOSFET-like behavior of a TFT based on amorphous oxide semiconductor channel layer with suitable integration of atomic layered deposited high-k gate dielectrics

A series of different high κ dielectrics such as HfO2, ZrO2, and Al2O3 thin films were studied as an alternative material for the possible replacement of traditional SiO2. These large areas, as well as conformal dielectrics thin films, were grown by the atomic layer deposition technique on a p-type silicon substrate at two different deposition temperatures (150 and 250 °C). Atomic force microscopic study reveals that the surface of the films is very smooth with a measured rms surface roughness value of less than 0.4 nm in some films. After the deposition of the high κ layer, a top metal electrode was deposited onto it to fabricate metal oxide semiconductor capacitor (MOSCAP) structures. The I–V curve reveals that the sample growth at high temperatures exhibits a high resistance value and lower leakage current densities. Frequency-dependent (100 kHz to 1 MHz) C–V characteristics of the MOSCAPs were studied steadily. Furthermore, we have prepared a metal oxide semiconductor field-effect transistor device with Al-doped ZnO as a channel material, and the electrical characteristic of the device was studied. The effect of growth temperature on the structure, surface morphology, crystallinity, capacitance, and dielectric properties of the high κ dielectrics was thoroughly analyzed through several measurement techniques, such as XRD, atomic force microscopy, semiconductor parameter analysis, and ultraviolet-visible spectroscopy.

(Invited, Digital Presentation) Exploring the Potential and Limits of Gallium Oxide Electronics: In-Situ Dielectrics, Heterointegration and High-k Field Plates

The intrinsic properties of beta phase Gallium Oxide such as the high breakdown field strength makes it a very attractive material for next generation electronics. Rapid progress has been made over the last few years in pushing the performance of Gallium Oxide-based vertical Schottky diodes and lateral field effect transistors and impressive figure of merit has been reported. However, the device performance is farther from the expected performance based on intrinsic properties. Exploration of the intrinsic potential is rather limited by several factors such as the quality of dielectrics and dielectric/semiconductor interfaces, electric field management challenges due to the lack of p-type material, to name a few. In this work, we will highlight a few approaches to tackle some of these challenges.(1) In-situ dielectrics: High quality dielectric-semiconductor interfaces are critical for reliable high-performance transistors. We report in situ metal–organic chemical vapor deposition of Al2O3 on β-Ga2O3 as a potentially better alternative to the most commonly used atomic layer deposition (ALD) [1]. The growth of Al2O3 is performed in the same reactor as Ga2O3 using trimethylaluminum and O2 as precursors without breaking the vacuum at a growth temperature of 600 °C. The fast and slow near interface traps at the Al2O3/β-Ga2O3 interface are identified and quantified using stressed capacitance–voltage (CV) measurements on metal oxide semiconductor capacitor (MOSCAP) structures. The density of shallow and deep level initially filled traps (Dit) are measured using ultraviolet-assisted CV technique. The average Dit for the MOSCAP is determined to be 6.4 × 1011 cm−2eV−1. The conduction band offset of the Al2O3/ Ga2O3 interface is also determined from CV measurements and found out to be 1.7 eV which is in close agreement with the existing literature reports of ALD Al2O3/Ga2O3 interface. The current–voltage characteristics are also analyzed and the average breakdown field is extracted to be approximately 5.8 MV cm−1.(2) Field management using High-K field Plate: We report a vertical (001) β-Ga2O3 field-plated (FP) Schottky barrier diode (SBD) with a novel extreme permittivity dielectric field oxide [2] . A thin drift layer of 1.7μm was used to enable a punch-through (PT) field profile and very low differential specific on-resistance (Ron-sp) of 0.32 mΩ-cm2. The extreme permittivity field plate oxide facilitated the lateral spread of the electric field profile beyond the field plate edge and enabled a breakdown voltage (Vbr) of 687 V. The edge termination efficiency increases from 13.2%for non-field plated structure to 61% for high permittivity field plate structure. The high permittivity field plated SBD demonstrated a record high Baliga's figure of merit (BFOM) of 1.47 GW/cm2 showing the potential of Ga2O3 power devices for multi-kilovolt class applications.(3) p-type III-nitride/Ga2O3 integration for field management: This work presents the simulation and analysis of a novel Ga 2 O 3 vertical Schottky diode with three different guard ring (GR) configurations to reduce the peak electric field at the metal edges [3]. Highly doped p-type GaN, p-type nonpolar AlGaN, and polarization-doped graded p-AlGaN are simulated and analyzed as the GR material, which forms a heterojunction with the Ga 2 O 3 drift layer. GR with nonpolar graded p-AlGaN with a bandgap larger than Ga 2 O 3 is found to show the best performance in terms of screening the electric field at the metal edges. The proposed GR configuration is also compared with a reported Ga 2 O 3 Schottky diode with no GR and a structure with high-resistive nitrogen-doped GR. The optimized design is predicted to have a breakdown voltage as high as 6.2 kV and a specific ON-resistance of 3.55 mΩ-cm 2, which leads to an excellent power figure of merit of 10.8 GW/cm 2.The approaches discussed here can offer a pathway towards understanding the true potential and limitations of Gallium Oxide for extreme electric field devices. We acknowledge funding support from NSF (DMR-1931652) and the AFOSR MURI program (FA9550-18-1-0507).

Large-Area Uniform 1-nm-Level Amorphous Carbon Layers from 3D Conformal Polymer Brushes. A "Next-Generation" Cu Diffusion Barrier?

A reliable method for preparing a conformal amorphous carbon (a-C) layer with a thickness of 1-nm-level, is tested as a possible Cu diffusion barrier layer for next-generation ultrahigh-density semiconductor device miniaturization. A polystyrene brush of uniform thickness is grafted onto 4-inch SiO2 /Si wafer substrates with "self-limiting" chemistry favoring such a uniform layer. UV crosslinking and subsequent carbonization transforms this polymer film into an ultrathin a-C layer without pinholes or hillocks. The uniform coating of nonplanar regions or surfaces is also possible. The Cu diffusion "blocking ability" is evaluated by time-dependent dielectric breakdown (TDDB) tests using a metal-oxide-semiconductor (MOS) capacitor structure. A 0.82nm-thick a-C barrier gives TDDB lifetimes 3.3× longer than that obtained using the conventional 1.0nm-thick TaNx diffusion barrier. In addition, this exceptionally uniform ultrathin polymer and a-C film layers hold promise for selective ion permeable membranes, electrically and thermally insulating films in electronics, slits of angstrom-scale thickness, and, when appropriately functionalized, as a robust ultrathin coating with many other potential applications.

Radio frequency power controlled [formula omitted] crystal phase transition from monoclinic to cubic

Rare earth oxides such as Gadolinia (Gd2O3) are extensively explored for buried oxide (BOX) application as a replacement for silicon dioxide (SiO2) in silicon-on-insulator (SOI) substrates. Of all the proposed methods, molecular-beam-epitaxy-based techniques have shown perfectly single-crystalline growth of Gd2O3. We present a radio frequency (RF) magnetron sputter based low-cost technique to grow single-crystalline Gd2O3 on Si (111) substrate. We show a gradual phase transition of the Gd2O3 layer from monoclinic to cubic by engineering the Gd2O3 deposition rate–i.e., tuning the RF power. We present a comparison amongst three samples as follows: (a) monoclinic; (b) monoclinic+cubic; (c) cubic at three different RF powers keeping the rest of the process conditions such as chamber pressure, Argon flow rate, etc., fixed. Further, we present a detailed structural characterization of all the three samples using a high-resolution X-ray diffraction system. Using the ω−2θ and pole-figure measurements we show a highly textured monoclinic Gd2O3 layer formation with (-402) crystal orientation in experiment (a). In experiment (c) we show phase transition of Gd2O3 from monoclinic to cubic by tuning the RF power. Finally, with experiment (b), we demonstrate that the aforementioned phase transition is a gradual phenomenon by highlighting a coexistence of both the monoclinic and cubic phases at an intermediate RF power. To ensure the electrical characteristics of the grown dielectric we present a metal oxide semiconductor capacitor structure fabrication for the monoclinic and the cubic Gd2O3 layers and benchmark the interface trap density, and dielectric constant against state-of-the-art literature. We show an improvement in the interface trap density, and reduction in the hysteresis from monoclinic to cubic phase transition due to an improved epitaxial relation between cubic Gd2O3 and Si(111) substrate. Such low-cost methods of growing single-crystalline Gd2O3 layer has the potential to replace the SiO2 BOX layer, and significantly bring down the manufacturing cost of the existing SOI wafer technology.

In Situ Dielectric Al2O3/β‐Ga2O3 Interfaces Grown Using Metal–Organic Chemical Vapor Deposition

AbstractHigh quality dielectric‐semiconductor interfaces are critical for reliable high‐performance transistors. This paper reports the in situ metal–organic chemical vapor deposition of Al2O3 on β‐Ga2O3 as a potentially better alternative to the most commonly used atomic layer deposition (ALD). The growth of Al2O3 is performed in the same reactor as Ga2O3 using trimethylaluminum and O2 as precursors without breaking the vacuum at a growth temperature of 600 °C. The fast and slow near interface traps at the Al2O3/β‐Ga2O3 interface are identified and quantified using stressed capacitance–voltage (CV) measurements on metal oxide semiconductor capacitor (MOSCAP) structures. The density of shallow and deep level initially filled traps (Dit) are measured using ultraviolet‐assisted CV technique. The average Dit for the MOSCAP is determined to be 6.4 × 1011 cm−2eV−1. The conduction band offset of the Al2O3/ Ga2O3 interface is also determined from CV measurements and found out to be 1.7 eV which is in close agreement with the existing literature reports of ALD Al2O3/Ga2O3 interface. The current–voltage characteristics are also analyzed and the average breakdown field is extracted to be approximately 5.8 MV cm−1. This in situ Al2O3 dielectric on β‐Ga2O3 with improved dielectric properties can enable Ga2O3‐based high‐performance devices.

A Resonantly Driven, Electroluminescent Metal Oxide Semiconductor Capacitor with High Power Efficiency.

Electroluminescence can be generated from a wide variety of emissive materials using a simple, generic device structure. In such a device, emissive materials are deposited by various means on a metal oxide semiconductor capacitor structure across which alternating current voltage is applied. However, these devices suffer from low external efficiencies and require the application of high voltages, thus hindering their practical usage and raising questions about the possible efficiencies that can be achieved using alternating current driving schemes in which injection of bipolar charges does not occur simultaneously. We show that appropriately chosen reactive electrical components can be leveraged to generate passive voltage gain across the device, allowing operation at input voltages below 1 V for devices across a range of gate oxide thicknesses. Furthermore, high power efficiencies are observed when using thermally activated delayed fluorescence emitters deposited by a single thermal evaporation step, suggesting that the efficiency of a light-emitting device with simplified structure can be high.

Capacitance matching by optimizing the geometry of a ferroelectric HfO2-based gate for voltage amplification

The voltage amplification of a ferroelectric layer was studied for advanced complementary metal–oxide–semiconductor (CMOS) applications. To match the capacitance for negative-capacitance field-effect transistors (NC-FETs), a method of adjusting the MOS capacitance is proposed by optimizing the width (W) and height/depth (H) in two types of ferroelectric gate-stack 2D metal-oxide semiconductor capacitor (MOSCAP) structures: a fin-like structure and a trench structure. The capacitance of the semiconductor was modeled to match that of the ferroelectric films to obtain hysteresis-free operation (ΔVT = VT, for –VT,rev ~ 0) and achieve voltage amplification (AV). The optimized conditions are found to be H = 19.3 nm and 24.3 nm to achieve the criterion with AV > 50 for the fin-like and trench structure, respectively. Subsequently, the structure was extended to a three-dimensional (3D) fin-shaped field-effect transistor (FinFET) to evaluate the effects of varying geometrical parameters such as the fin spacing (FS). Tuning FS can not only enhance the on-current but also decrease the subthreshold swing in the off-current region. For the FET, the use of the optimum FS value of 30 nm helps the FinFETs achieve capacitance matching with AV > 30. The subthreshold swing of the NC-FinFET is improved by about 47% for HFinFET/WFinFET ~ 3 and Fs/HFinFET ~ 1.2 as compared with the conventional FinFET. The concept of coupling the polarized Hf-based oxide in NC-FETs that is demonstrated to be feasible herein is thus practicable using current CMOS architectures.

Morphological and electrical study of porous TiO2 films with various concentrations of Pluronic F-127 additive

Porous TiO2 thin films were synthesized by dip-coating method on silicon substrates. Pluronic F-127 (F127), a structure-directing agent, was used to promote the evolution of pores during the synthesis of TiO2 thin films. The concentration of F127 was varied from 0.3 to 3.75 mM. FESEM micrograph has confirmed the presence of porous morphology, whereas XRD and Raman studies have revealed the formation of the anatase phase of the sample. Capacitance–voltage (C–V) measurement was carried out using TiO2 based metal oxide semiconductor (MOS) capacitor structure, where F127 was incorporated in the oxide layer. The oxide charge density was found to be increased with the concentration of F127 co-polymer. Interface trap density has a maximum value of 6.6 × 1012 eV−1 cm−2 after the addition of 3 mM of F127. It was found out that the 3 mM of F127 has better memory effect during the resistive switching study.

On the Threshold Voltage and Performance of ZnO-Based Thin-Film Transistors with a ZrO2 Gate Dielectric

In the past few years, thin-film transistor (TFT) technology has experienced a rapid transition from amorphous silicon- (a-Si:H) and polysilicon-based TFTs to zinc oxide (ZnO)-based TFTs, and because of this transition, transparent TFTs have become a reality. In ZnO TFTs, which operate in accumulation mode, the threshold voltage has remained ambiguous due to the existence of grain boundary traps in the polycrystalline semiconducting channel. This paper provides an analytical relationship of threshold voltage with grain boundary trap density by assuming the grain boundary is a continuous one-dimensional line charge. A high density of grain boundary traps leads to a high threshold voltage. However, its effect can be minimized by employing a high-κ gate dielectric. In this work, we have demonstrated the reduction of threshold voltage in a ZnO TFT by using ZrO2 as a gate dielectric. A study of a ZnO/ZrO2 interface is reported by fabricating a metal–insulator–semiconductor capacitor structure. This interface is studied using capacitance–voltage (C–V) and current–voltage (I–V) characteristics. The ZnO TFT with a ZrO2 gate dielectric exhibits a low subthreshold slope (131 mV decade−1), low gate leakage current density (2.94 × 10−7 A cm−2) and low threshold voltage (1.2 V). However, it also exhibits a counterclockwise hysteresis of −1.4 V, which is attributed to the existence of oxygen vacancies.

Well-ordered nanoparticle arrays for floating gate memory applications

A non-volatile floating gate memory device containing well-ordered Au nanoparticles (NPs) is fabricated as a metal–oxide–semiconductor capacitor structure. With superior control on the size, shape and position of nanoparticles, the presented nano-floating gate memory (NFGM) device possesses almost perfect precision of device geometry. The well-ordered Au NPs embedded within the memory device exhibit large memory window at low operation voltages (8.8V @ ± 15V), fast operation time (<10−4 s) and good retention (up to 107 s). In this work, the structural properties of the NFGM device are correlated with the examined electrical properties. The current results are compared with the other studies in the literature to emphasis the advantages of the precise ordering and geometry of the NPs.

Nonvolatile memory based on redox-active ruthenium molecular monolayers

A monolayer of diruthenium molecules was self-assembled onto the silicon oxide surface in a semiconductor capacitor structure with a “click” reaction for nonvolatile memory applications. The attachment of the active molecular monolayer was verified by x-ray photoelectron spectroscopy. The prototypical capacitor memory devices in this work employed a metal/oxide/molecule/oxide/Si structure. With the intrinsic redox-active charge-storage properties of diruthenium molecules, these capacitor memory devices exhibited fast Program and Erase speed, excellent endurance performance with negligible degradation of the memory window after 105 program/erase cycles, and very good 10-year memory retention. These experimental results indicate that the redox-active ruthenium molecular memory is very promising for use in nonvolatile memory applications.

Dynamic Charging Mechanism of Organic Electrochemical Devices Revealed with In Situ Infrared Spectroscopy

The steps responsible for device charging in organic electrochemical transistors were investigated using in situ infrared spectroscopy. Metal–electrolyte-dielectric–organic semiconductor capacitor structures were fabricated on infrared waveguides and measured using the total internal reflection sampling method. Upon the application of a voltage, charges were induced in the device, creating polaron absorption features in the mid-infrared region. The dynamics of the device charging were investigated by varying the channel length, dielectric layer thickness, and organic semiconductor layer thickness. Device charging was independent of the channel length but depended strongly on the semiconductor and dielectric layer thicknesses, indicating that the movement of ions is the primary determining factor for device charging kinetics. A quantitative model is developed combining an resistor-capacitor (RC) circuit model for the dielectric layer and a mixed ion–carrier diffusion model for the organic semiconductor lay...

Crystalline SrZrO3 deposition on Ge (001) by atomic layer deposition for high-k dielectric applications

Heteroepitaxial growth of crystalline SrZrO3 (SZO) on Ge (001) by atomic layer deposition is reported. Ge (001) surfaces are pretreated with 0.5-monolayers (ML) of Ba and an amorphous ∼3-nm SZO layer is grown from strontium bis(triisopropylcyclopentadienyl), tetrakis (dimethylamido) zirconium, and water at 225 °C. This ∼3-nm layer crystallizes at 590 °C and subsequent SZO growth at 225 °C leads to crystalline films that do not require further annealing. The film properties are investigated using X-ray photoelectron spectroscopy, x-ray diffraction, aberration-corrected electron microscopy, and capacitance-voltage measurements of metal-oxide semiconductor capacitor structures. Capacitance-voltage measurements of the SrZrO3/Ge heterojunctions reveal a dielectric constant of 30 for SrZrO3 and a leakage current density of 2.1 × 10−8 A/cm2 at 1 MV/cm with an equivalent oxide thickness of 0.8 nm. Oxygen plasma pretreatment of Ge (001), Zintl layer formation with 0.5 ML Ba, and atomic deuterium post-growth treatment were explored to lower interface trap density (Dit) and achieved a Dit of 8.56 × 1011 cm−2 eV−1.

Water assisted atomic layer deposition of yttrium oxide using tris(N,N'-diisopropyl-2-dimethylamido-guanidinato) yttrium(iii): process development, film characterization and functional properties.

We report a new atomic layer deposition (ALD) process for yttrium oxide (Y2O3) thin films using tris(N,N′-diisopropyl-2-dimethylamido-guanidinato) yttrium(iii) [Y(DPDMG)3] which possesses an optimal reactivity towards water that enabled the growth of high quality thin films. Saturative behavior of the precursor and a constant growth rate of 1.1 Å per cycle confirm the characteristic self-limiting ALD growth in a temperature range from 175 °C to 250 °C. The polycrystalline films in the cubic phase are uniform and smooth with a root mean squared (RMS) roughness of 0.55 nm, while the O/Y ratio of 2.0 reveal oxygen rich layers with low carbon contaminations of around 2 at%. Optical properties determined via UV/Vis measurements revealed the direct optical band gap of 5.56 eV. The valuable intrinsic properties such as a high dielectric constant make Y2O3 a promising candidate in microelectronic applications. Thus the electrical characteristics of the ALD grown layers embedded in a metal insulator semiconductor (MIS) capacitor structure were determined which resulted in a dielectric permittivity of 11, low leakage current density (≈10−7 A cm−2 at 2 MV cm−1) and high electrical breakdown fields (4.0–7.5 MV cm−1). These promising results demonstrate the potential of the new and simple Y2O3 ALD process for gate oxide applications.

Interface characterization of atomic layer deposited high-k on non-polar GaN

The interface properties between dielectrics and semiconductors are crucial for electronic devices. In this work, we report the electrical characterization of the interface properties between atomic layer deposited Al2O3 and HfO2 on non-polar a-plane (112¯0) and m-plane (11¯00) GaN grown by hybrid vapor phase epitaxy. A metal oxide semiconductor capacitor (MOSCAP) structure was used to evaluate the interface properties. The impact of annealing on the interface properties was also investigated. The border trap in the oxide, characterized by the capacitance-voltage (C-V) hysteresis loop, was low. The interface state density (Dit), extracted using the ac conductance method, is in the range of 0.5 × 1012/cm2 eV to 7.5 × 1011/cm2 eV within an energy range from 0.2 eV to 0.5 eV below the conduction band minimum. The m-plane GaN MOSCAPs exhibited better interface properties than the a-plane GaN MOSCAPs after annealing. Without annealing, Al2O3 dielectrics had higher border trap density and interface state density compared to HfO2 dielectrics. However, the annealing had different impacts on Al2O3 dielectrics as compared to HfO2. Our results showed that the annealing degraded the quality of the interface in HfO2, but it improved the quality of the interface in Al2O3 devices. The annealing also reduced the positive trapped oxide charge, resulting in a shift of C-V curves towards the positive bias region.

High-k/GaN interface engineering toward AlGaN/GaN MIS-HEMT with improved Vth stability

Metal–insulator–semiconductor (MIS) capacitor structures were fabricated on AlGaN/GaN two-dimensional electron gas heterostructure material in order to investigate important aspects of the gate module of a corresponding MIS-high electron mobility transistor device. The process sequence started with an initial wet chemical surface treatment of the as-grown semiconductor material followed by an atomic layer deposition of Al2O3 (high-k first). The electrical analysis focused on the gate leakage current as well as on the shift of the threshold voltage (Vth) upon bias stress in the off- and the on-state regions. The high-k first samples showed much better Vth stability compared to lithographically processed samples, in which the high-k deposition was performed after ohmic contact formation and just before the gate electrode metallization. These results reflect a superior quality of the high-k/GaN interface for the processed structures according to the high-k first approach.

Investigation of thermal atomic layer deposited TiAlX (X = N or C) film as metal gate

TiAlX (X=N or C) films are developed by thermal atomic layer deposition (ALD) technique as metal gate. The TiAlX films are deposited by using four different combinations of precursors: A: TiCl4–NH3–TMA–NH3, B: TiCl4–TMA–NH3, C: TiCl4–NH3–TMA and D: TiCl4–TMA. The physical characteristics of the TiAlX films such as chemical composition, growth rate, resistivity and surface roughness are estimated by X-ray photoemission spectroscopy, scanning electron microscope, four point probe method and atomic force microscopy respectively. Additionally, the electrical characteristics of the TiAlX films are investigated by using metal–oxide–semiconductor (MOS) capacitor structure. It is shown that NH3 presence in the reaction makes the film more like TiAlN(C) while NH3 absence makes the film more like TiAlC. The TiAlC film deposited by TiCl4–TMA has effective work function close to mid-gap of Si, which is rather potential for low power FinFET device application.