Self-timed Adder Research Articles

ALUSGDI: Low power arithmetic logic unit based sliced processor using GDI and MGDI

In recent years, many digital logic circuits in terms of transistors such as Pass Transistor Logic (PTL), Complementary Metal Oxide Semiconductor (CMOS) logic and etc. have been used for implementing DSP algorithms. Gated Diffusion Input (GDI) logic is also another method for implementing digital circuits. In this work, GDI logic style is used in the proposed ALU based Filter Bank. The ALU unit of the proposed filter bank is designed by modified GDI logic. Power consumption of the entire design is also reasonably reduced using recursive parallel self-timed adder. GDI logic has three terminals which are Common Gate (G), PMOS (P)/NMOS (N) and output terminal. The number of transistors is reduced when compared to Complementary Metal Oxide Semiconductor (CMOS) logic. Hence, the reduced number of transistors eliminates the switching activity and power dissipation. The GDI logic consumes 65% less area and 91.4% less power when compared to CMOS logic. The modified GDI logic provides 77.5% area reduction when compared to CMOS logic. The experimental results obtained using the proposed ALU based Sliced Processor by employing GDI logic compared with the traditional filter bank techniques. ALU based filter bank design speeds up significantly through GDI concepts when compared to the interpolated filter bank and the design is implemented in 65 nm CMOS technology.

Implementation of Recursive Formulation for Parallel Self-Timed Adder using Verlog Logic

Implementation of Recursive Formulation for Parallel Self-Timed Adder using Verlog Logic

Parallel Self-Timed Adder with Lookahead-Carry Generator

Parallel self-timed adder (PASTA) is a newly introduced asynchronous adder. It shows appreciable average-case performance without any special speedup circuitry or look-ahead schema, but its worst-case performance is almost similar to that of ripple carry adder. It is therefore an important research issue to find a technique to improve its worst-case performance without any significant compromise in its other performances. This paper investigates the possibility of such performance improvement of the basic architecture of PASTA by changing its carry propagation schema. The existing ripple fashioned carry propagation schema is replaced by four different lookahead-carry generators. Four different implementations of PASTA with four different types of lookahead-carry generators are presented. The carry propagation delays of the proposed implementations are compared with that of the basic implementation of PASTA. More impressive worst case performances are found for the proposed implementations. The amount of improvement is minimum 45.25% and maximum 61.09%. The proposed designs are regular and do not have any practical limitations of fan-ins or fan-outs. Simulation-based results validate the practicality as well as the superiority of the proposed architecture over the existing architecture of PASTA.

Design of Parallel Self-Timed Adder with Recursive Research

This speedy suggests a parallel single-rail selfcoordinated snake. It relies upon on a algorithmic description for showing multibit twofold growth. The hobby is parallel for the ones bits that require now not trouble with any supply chain unfold. in the course of this way, the arrange achieves power execution over irregular quantity situations and not using a excellent dashing hardware or appearance-ahead sample. A proper all of the way right down to earth usage is given on a give up discovery unit. The execution is fashionable and doesn't have any pragmatic rules of excessive fanouts. A high fan-in door is wanted however nonetheless it really is ineluctable for kinky reason and is overseen by way of manner of associating the transistors in parallel. Recreations were finished creating use of AN commercial enterprise commonplace tool cabinet that ensure the common sense and prevalence of the projectedmethod over current nonconcurrent adders

Design of Parallel Self-Timed Adder

Design of Parallel Self-Timed Adder

Recursive Approach to the Design of a Parallel Self-Timed Adder

This brief presents a parallel single-rail self-timed adder. It is based on a recursive formulation for performing multibit binary addition. The operation is parallel for those bits that do not need any carry chain propagation. Thus, the design attains logarithmic performance over random operand conditions without any special speedup circuitry or look-ahead schema. A practical implementation is provided along with a completion detection unit. The implementation is regular and does not have any practical limitations of high fanouts. A high fan-in gate is required though but this is unavoidable for asynchronous logic and is managed by connecting the transistors in parallel. Simulations have been performed using an industry standard toolkit that verify the practicality and superiority of the proposed approach over existing asynchronous adders.

SELF-TIMED SECTION-CARRY BASED CARRY LOOKAHEAD ADDERS AND THE CONCEPT OF ALIAS LOGIC

This paper makes two important contributions to the domain of self-timed computer arithmetic. Firstly, a gate-level synthesis of self-timed carry lookahead (CLA) adders based on the notion of section-carry is discussed. Three types of CLA adder architectures have been conceived and both homogeneous and heterogeneous delay-insensitive (DI) data encoding schemes are considered. In general, for higher-order additions, the self-timed CLA adder is found to result in reduced latency than the carry ripple version by 38.6%. However, the latter occupies less area and dissipates less power than the former by 37.8% and 17.4%, respectively. Secondly, a new concept of alias logic is introduced in this work which is useful for delay optimization of iterative circuit specifications — here; this concept is applied to effect latency reduction in self-timed CLA adders. By incorporating alias logic, the propagation delay of the intermediate carries in a CLA structure is further minimized to the tune of 27.2% on average, whilst accompanied by marginal area and power penalties of the order of just 2% and 1.5%, respectively.

A Novel High-Speed 54×54 bit Multiplier

A new 54×54-bit multiplier using high-speed carry-lookahead adder has been fabricated by CMOS technology. This paper presents a self-timed carry-lookahead adder in which the logic complexity was a linear function of n, the number of inputs, and the average computation time was proportional to the logarithm of the logarithm of n. To the best of our knowledge, our adder has the best area-time efficiency. A novel 4-2 compressor, featuring pass-transistor multiplexers, has been developed. The proposed circuits have a speed advantage over conventional CMOS circuits because the number of critical-path gate stages was minimized due to the high logic functionality of pass- transistor multiplexers. The total number of transistors of the proposed multiplier core was 42579 and The multiplication time was 3.4 ns at a 1.3 V power supply.

An efficient self-timed adder realized using conventional CMOS standard cells

Usually, efficient self-timed adders are realized using the dynamic differential cascode voltage switch logic. This allows the end-completion to be easily detected, but it makes circuit design and testing very complex, compelling the production of full-custom layouts and leading to a very long time before marketing. This paper presents a new 56-bit high-speed self-timed adder realized with conventional AMS 0.35 μm CMOS standard cells. The proposed circuit uses overlapped execution circuits, which exploit the initialization time that always elapses between two consecutive addition operations. Compared to several self-timed adders existing in the literature, the addition circuit proposed here shows brilliant advantages in terms of speed-performance, silicon area occupancy and power dissipation.

Completion-detecting carry select addition

Logic analysis, circuit implementation and verification of a novel self-timed adder scheme based on carry select (CS) logic are presented. The preliminary analysis of the variable-time behaviour of CS logic justifies the design of self-timed CS adders, and identifies the best choice for the block size to optimise the average performance. The logic design and full-custom circuit implementation is described of a completion-detecting CS adder by means of precharged CMOS logic. The correct asynchronous operation of the circuit is verified by means of layout level SPICE simulation referring to a 0.35 μm CMOS process. The worst-case addition time is comparable with the fastest fixed-time adders, which is a considerable result for a completion-detecting technique. The hardware overhead can be limited to 23% over a conventional CS adder. SPICE simulation estimates an average detected addition time of 1.6 ns for a 64 bit adder, including the precharge time.

Self-timed Manchester chain carry propagate adder

The authors present a self-timed adder that uses two Manchester chains to propagate carries in a two-rail code. With the inclusion of buffers in the chains, the adder meets the timing conditions typical of an asynchronous design based in the ‘bundled-data, bounded-delay’ model and is significantly faster than self-timed adders with restoring logic and similar complexity.

Auxiliary functions for completion detection inself-timed systems

A technique employing an auxiliary function to enable the detection of completion in logic functions is described. The derivation of such auxiliaries is demonstrated using an extension of transition logic principles. The technique is evaluated through the implementation of a self-timed adder.