Self-aligned Silicide Research Articles

Process optimization of titanium self-aligned silicide formation through evaluation of sheet resistance by design of experiment methodology

A low-resistivity titanium silicide (TiSi2) is crucial as a gate and source/drain material in microelectronic device fabrication, offering notable properties to enhance device performance. This study aims to experimentally determine the optimum process parameters, including arsenic doping dosage, titanium thickness, and two-step rapid thermal process (RTP) temperature, for the sheet resistance of titanium self-aligned silicide process using a design of experiment methodology. The results demonstrate that both the thickness of the titanium and the temperature of the RTP play crucial roles in determining the sheet resistance of TiSi2. Statistical analysis reveals that increasing the titanium thickness or the temperature of the first-step RTP (RTP-1) could reduce the sheet resistance. Additionally, an optimal second-step RTP (RTP-2) temperature is critical to yield low-resistivity TiSi2 by completely converting C49- to C54-phase. The optimum process conditions for obtaining low sheet resistance are a titanium thickness of 32–35 nm, RTP-1 temperature of 720–750 °C for 75 s, and RTP-2 temperature of 860 °C for 20 s. Moreover, surface amorphization of the polysilicon by arsenic ion implantation before the deposition of Ti/TiN films also plays a crucial role in the formation of C54-TiSi2. The lowest sheet resistance achieved was 3.91 Ω/sq with an arsenic dosage of 1 × 1014 cm−2. The optimum condition was adopted for forming a submicron polysilicon gate, providing a promising approach for designing the process parameters for titanium self-aligned silicide formation to achieve low resistance in nanoscale electronic devices.

On the influence of Ni(Pt)Si thin film formation on agglomeration threshold temperature and its impact on 3D imaging technology integration

Ni(10 at.% Pt) monosilicide is used as contact in microelectronics but suffers from degradation at relatively low temperatures due to agglomeration. Recent results obtained on 28 nm-FDSOI (Fully Depleted Silicon On Isolator) microelectronics devices have demonstrated severe yield loss after an anneal at 550 °C/2 h linked to Ni(Pt)Si film dewetting. Such agglomeration thermal budget is 100 °C lower than the ones measured on blanket wafers with in-situ or ex-situ four-point probe measurements. In this context, the aim of this paper is to investigate the effect Ni(Pt)Si formation process on the Ni(Pt)Si agglomeration using different approaches as (i) the classical one in which one anneal is applied to form silicide and leads also to agglomeration, (ii) the silicide formation through the standard SALICIDE process, “Self-Aligned Silicide”, and a subsequent anneal to induce agglomeration, and (iii) the standard SALICIDE process for silicide formation followed by an encapsulation of the top silicide surface by a SiN layer as applied in devices, and submitted finally to the agglomeration anneal. Our work demonstrated that the film thermal stability is influenced by the sequencing of the Selective Etch (SE) in the formation process and whether it is formed by a single or a double anneal. For single anneal, the thermal budget needed to agglomerate Ni(Pt)Si film is higher i.e., agglomeration occurs at around 700 °C/30 s in single anneal as compared to double anneal at around 550 °C/30 s. Another conclusion of this work is that four-point probe measurements are not sensitive enough to well estimate the real starting point of agglomeration phenomenon which is detrimental for devices (holes formation at the triple junctions). Some additional characterizations such as tilted Scanning Electron Microscopy (tilted SEM) are deeply needed for an accurate determination of agglomeration thermal budget. This study allows clarifying the main parameters leading to agglomeration: the film thickness and the grain size appear to be the more important ones.

Self-aligned-TiSi2 bottom contact with APM cleaning and post-annealing for sputtered-MoS2 film

Electrical contact characteristics between self-aligned titanium silicide (TiSi2) and sputtered-molybdenum disulfide (MoS2) films were newly demonstrated. In contrast with metal contacts, the surface of the TiSi2 bottom-contact was cleaned by using an ammonia and hydrogen peroxide mixture (APM) before MoS2 deposition, because the TiSi2 film has high oxidation resistance. In order to extract the contact resistance, a transmission line model device was fabricated. A two-order reduction in the contact resistance was achieved by a post-annealing at 650 °C in forming gas ambient (3% H2 in N2). This reduction was attributed to selective titanium diffusion from bottom contact into the MoS2 film. The TiSi2 contact is thus speculated as a candidate for a practical contact material in MoS2 devices.

Low-Temperature Self-Aligned-Silicide-Capable Transistor Process Using Solid-Phase-Epitaxy and Lift-Off for Hybrid Substrates

Details of a large-area-compatible sub-600 °C process for the fabrication of high mobility field-effect transistors on single crystalline silicon are presented. It is shown that lift-off and solid-phase-epitaxy (SPE) can be used in conjunction with plasma enhanced chemical vapor deposition (PECVD) to create MOSFET transistors with mobilities comparable to other high-performance techniques. Furthermore, use of an amorphous silicon/silicon oxynitride (SiOxNy) sacrificial bilayer is shown to make the process capable of self-aligned silicidation. The topography of the deposition is studied using cross-sectional scanning electron microscopy (SEM). It is shown that a successful lift-off can be achieved through the proper design of the sacrificial bilayer despite the high degree of step coverage generally exhibited by PECVD films. Cross-sectional transmission electron microscopy (TEM) is used to reveal the microstructure of the epitaxy and silicidation. Current-voltage characteristics of the fabricated transistors are presented and the field effect mobility of electrons on the fabricated devices is reported. The developed process is particularly useful in applications where high mobility transistors need to be built on silicon/nonsilicon hybrid platforms that exclude high processing temperatures.

Enhanced thermoelectric properties of cobalt silicide-silicon heterostructured nanowires

Silicon nanowires (SiNWs) have attracted attention as promising high efficiency thermoelectric materials by significantly improving the thermoelectric efficiency of silicon. Here, we have fabricated cobalt silicide/silicon heterostructure on both ends of nanowires using self-aligned silicide (salicide) process. By forming cobalt silicide (CoSi2) layer on SiNWs, the thermal conductivity of SiNWs with diameters of 200, 350, and 500 nm decrease to 25.1, 31.3, and 38.1 W·m−1·K−1, respectively, which is about 8% reduction on average. Since the phonon nanoinclusion scattering is influenced by the density of the nanoinclusions, the thermal conductivity tends to decrease as the volume fraction of CoSi2 in SiNWs increases. The Seebeck coefficient of the heterostructured nanowires increases to 255 μV/K, which is mainly attributed to the low-energy charge carrier filtering effect due to the Schottky barrier at the CoSi2/Si interfaces. The measurements show that the figure-of-merit ZT of the heterostructured nanowires is improved by 10% on average compared with the conventional SiNWs. Consequently, the CoSi2/Si heterostructured nanowires enhance the thermoelectric properties of SiNWs effectively by suppressing phonon transport and improving electron flow.

Cobalt germanide contacts: growth reaction, phase formation models, and electrical properties

State of the art of cobalt germanide contacts to semiconductor devices is reviewed in this article. First, evolution of contacts is covered from the dawn of the transistor to present day. The history of contact has three stages: (a) elemental metals as direct contacts to the semiconductor with focus on aluminum, (b) self-aligned silicide contacts, and, recently, (c) the paradigm shift that emphasizes the interface contact resistivity. The second section outlines the current role of germanium in the semiconductor industry and the reasons cobalt germanide is an ideal contact material to germanium and silicon germanium semiconductor devices. Fundamental physical properties of cobalt germanides are presented next. Models for phase formation sequence are, then, detailed. This is followed by a comprehensive survey of the experimental results of formation of cobalt germanides. Those results are discussed and reconciled. Factors affecting the resulting phases and their quality are identified and some optimum choices for the experimental parameters are pointed based on the survey. After that, electrical properties of the contact are discussed. The role of germanium crystal orientation in ohmic and Schottky properties of the contact is analyzed. Fermi level pinning (FLP) plays a role mainly on metal/(100) n-type Ge interfaces. The role of FLP is minimal on p-type Ge and other crystalline orientations. Schottky barrier heights (SBH’s) for cobalt and cobalt germanide contacts reported in the literature are surveyed. Mechanisms of FLP and methods adopted by the industry to depin the fermi level at the interface are outlined. The electrical properties section is concluded with a subsection that focuses on the effect of the crystallinity of the contact material on its electrical behavior. Crystalline cobalt germanides are expected to have lower interface resistivities compared to those calculated based on the SBH survey. The role of heat during Co deposition to obtain epitaxial germanides is pointed. Finally, current challenges and future trends of cobalt germanide contacts are summarized.

Investigation of a Self-Aligned Cobalt Silicide Process for Ohmic Contacts to Silicon Carbide

Previous studies showed that cobalt silicide can form ohmic contacts to p-type 6H-SiC by directly reacting cobalt with 6H-SiC. Similar results can be achieved on 4H-SiC, given the similarities between the different silicon carbide polytypes. However, previous studies using multilayer deposition of silicon/cobalt on 4H-SiC gave ohmic contacts to n-type. In this study, we investigated the cobalt silicide/4H-SiC system to answer two research questions. Can cobalt contacts be self-aligned to contact holes to 4H-SiC? Are the self-aligned contacts ohmic to n-type, p-type, both or neither? Using x-ray diffraction, it was found that a mixture of silicides (hbox {Co}_2hbox {Si} and CoSi) was reliably formed at 800^circ C using rapid thermal processing. The cobalt silicide mixture becomes ohmic to epitaxially grown n-type (1times 10^{19} hbox {cm}^{-3}) if annealed at 1000^circ C, while it shows rectifying properties to epitaxially grown p-type (1times 10^{19} hbox {cm}^{-3}) for all tested anneal temperatures in the range 800–1000^circ C. The specific contact resistivity (rho _mathrm{C}) to n-type was 4.3 times 10^{-4} mathrm {Omega },hbox {cm}^{2}. This work opens the possibility to investigate other self-aligned contacts to silicon carbide.

Growth of self-aligned PtSi silicide nanowires and nanoclusters on p-type Si (111) by molecular beam epitaxy

In this report Molecular Beam Epitaxy (MBE) is shown to produce self-aligned platinum silicide (PtSi) nanoclusters and nanowires on Si (111) substrate near the eutectic point (T=978°C and 67at.% Si) of the platinum silicon system. With an added silicon source in the MBE annealing chamber, the formation of two different silicon steps (straight and wave-like) is reported. The steps determine the position and the shape of the thermomigrating PtSi droplets. Nanoclusters preferentially form in the triple point of the wave-like steps while nanoclusters that form on the straight steps combine and grow into silicide nanowires.

High Power Self-Aligned, Trench-Implanted 4H-SiC JFETs

The process technology for the fabrication of 4H-SiC trenched-implanted-gate 4H–SiC vertical-channel JFET (TI-VJFET) has been developed. The optimized TIVJFETs have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. A source-pillars sidewall oxidation and subsequent removal of the metallization from the top of the sidewall oxide ensured isolation between gate and source. Optimum planarization of the source pillars top has been performed by cyclotene spin coating and etch back. The effect of the channel geometry on the electrical characteristics has been studied by varying its length (0.3 and 1.2μm) and its width (1.5-5μm). The voltage blocking exhibits a triode shape, which is typical for a static-induction transistor (SIT) operation. The transistors exhibited high ON current handling capabilities (Direct Current density >1kA/cm2 ) and values of RON ranging from 6 - 12 mΩ•cm2 depending on the channel length. Maximum voltage blocking was 800V limited by the edge termination. The maximum voltage gain was 51. Most transistors were normally-on. Normally-off operation has been observed for transistors lower than 2μm channel width (mask level) and deep implantation.

Channel width effect on the operation of 4H-SiC vertical JFETs

SiC JFETs may have the lowest overall losses of switching devices and can operate at temperatures over 400 °C. Over different junction field-effect transistor (JFET) designs, the trenched and implanted (TI) gate vertical JFET (TI-VJFET) is very attractive since it may have the lowest on-resistance and its fabrication does not require epitaxial overgrowth or multiple angled implantation. 4H-SiC TI-VJFETs have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. Different design factors, including channel width, channel length, and mesa height, are considered. The effect of the channel geometry on the electrical characteristics has been studied by varying their width (1.5–5 µm). The specific ON resistance (RON) of the fabricated devices, at VGS = 0 V, varied from 12.5 to 6.2 mΩ cm2 with increasing the channel width. The effect of the channel width was more tremendous on the breakdown voltage of the transistors passing from 80 to 500 V, showing the importance of the static-induction effect (saddle point potential influenced by drain potential) on the transistor blocking characteristics. Indeed, the blocking voltage gain is varying from 50 to single digit values when increasing the channel width. The physical reason is that the blocking gain to first order depends exponentially on the channel dimensions as the drain-source current is exponentially related to the saddle point potential.

Impact Ionization in SOI MESFETs at the 32-nm Node

Silicon metal–semiconductor FETs (MESFETs) have been fabricated using a 32-nm silicon-on-insulator (SOI) CMOS technology. The MESFET gates are formed during the self-aligned silicide step and show almost ideal Schottky behavior at low drain voltages. However, an anomalous peak in the reverse gate leakage current appears for drain voltages ≥2 V. The anomalous gate current is attributed to impact ionization generating excess holes that exit the channel through the Schottky contact. An analytical model is used to extract the electron impact ionization rate, $\alpha $ , which agrees with three earlier data sets over nearly four orders of magnitude.

Technological enhancers effect on Ni0.9Co0.1 silicide stability for 3D sequential integration

Abstract3D sequential integration is a promising alternative to conventional scaling down approach: by stacking transistors level on top of each other, benefits on device density and performance are achieved. However, although the thermal processing of top transistors is currently restricted in order to avoid bottom CMOS degradation, it has been highlighted that Ni0.80Pt0.10 silicide source/drain (S&D) contact remains the most sensitive element to the thermal budget, especially on raised Si0.7Ge0.3:B S&D for pMOS transistors. In this context, a complete and systematic study on self‐aligned silicide (SALICIDE) process has been proposed: alternative metallization as well as source and drain surface pre‐treatments have been carried out. Indeed, a novel Ni‐based silicide, the Ni0.9Co0.1 provides a better stability on unpatterned 300 mm wafers. This stability has been further improved when combined with epitaxial silicon capping layer (Si‐Cap) and Si0.7Ge0.3:B S&D pre‐amorphization implant (PAI) using Ge beam. For the first time, a successful Ni0.9Co0.1 SALICIDE implementation has been demonstrated on pMOS planar FDSOI transistor with both PAI and Si‐Cap. Moreover, the presence of Si‐Cap contributes to reduce silicide roughness and limits Ge partition that damage Si0.7Ge0.3:B S&D. (© 2016 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Synthesis and thermal stability of Pt3Si, Pt2Si, and PtSi films grown by e-beam co-evaporation

Platinum silicide thin films formed via solid–solid reaction of Pt–Si interfaces play an important role as interconnects in microelectronics. This “self-aligned” silicide formation, however, is diffusion-limited and only Pt2Si and PtSi phases form. Also, their usefulness in electronic applications at high temperatures is limited due to agglomeration effects. Here, e-beam co-evaporation is presented as a means of fabricating well-defined films of Pt3Si as well as the Pt2Si and PtSi phases familiar to conventional, self-aligned silicide technology. Pt–Si films with a range of compositions (silicon atomic fractions of XSi = 0.00–0.77) were grown on r-sapphire substrates by co-deposition of independently controlled Pt and Si evaporant fluxes at 400 °C. Phase, morphology, and electronic properties were analyzed upon deposition and after vacuum annealing for 48 h at 1000 °C. As-deposited films with XSi < 0.70 are polycrystalline and at higher Si concentrations are fully amorphous. Valence spectra from Pt, Pt2Si, and PtSi films confirm previous reports and a valence spectrum is presented for the stoichiometric Pt3Si phase; these data provide experimental support for recently proposed revisions to the standard transition metal–silicon bonding model. As-deposited films, nominally 200 nm thick, are electrically conductive in the range 0.1–4.0 × 106 S/m and remain so after vacuum annealing for 48 h at 1000 °C. The phase, morphological, and electrical stabilities are attributed to the finely grained as-deposited morphologies of co-evaporated Pt silicide films, which hinder agglomeration at 1000 °C for much greater times than do morphologies of traditional, self-aligned silicides grown via solid-state reaction.

Selection of the first Ni silicide phase by controlling the Pt incorporation in the intermixed layer

During the deposition of a Ni film on a Si substrate, an intermixed layer usually forms at the Ni/Si interface. In this work, the influence of Pt incorporation in this intermixed layer on the phase formation sequence and especially on the first phase formation is studied by in situ-XRD measurements and atom probe tomography (APT). Four different samples were elaborated where the intermixed layer was modified by deposition of a 3 nm of Ni or Ni(10 at% Pt) on the Si substrate prior to the deposition of Ni(10 at%Pt) or Ni film respectively. These results show that the formation of the first phase changes between δ-Ni2Si and θ-Ni2Si depending on the Pt concentration integrated in the intermixed layer. Using this selection method to control the formation of the first phase, can impact the self-aligned silicide process used by the industry.

4H-SiC VJFETs with Self-Aligned Contacts

Trenched-implanted-gate 4H–SiC vertical-channel JFET (TI-VJFET) have been fabricated with self-aligned nickel silicide source and gate contacts using a process sequence that greatly reduces process complexity as it includes only four lithography steps. The effect of the channel geometry on the electrical characteristics has been studied by varying its length (0.3 and 1.2μm) and its width (1.5-5μm). The transistors exhibited high current handling capabilities (Direct Current density 330A/cm2). The output current reduces with the increase of the measurements temperature due to the decrease of the electron mobility value. The voltage breakdown exhibits a triode shape, which is typical for a static-induction transistor operation.

Formation CMOS Schemes on GaAs with Self-Aligned Nitride and Silicide Gates

Advanced integrated logic circuits on GaAs are mainly based on the using of n-channel field-effect transistors with gate Schottky (MESFET). To create the complementary MESFET integrated circuits the main problem is quite small Schottky barrier height (&lt; 0,5 eV) on p-type gallium arsenide. One way to solve this problem is to use a nitride or silicide tungsten compounds to form gates given the thickness and composition.&#x0D; This paper highlights the features of the formation of complementary high-speed logic circuits on the p-GaAs with self-aligned gate based on nitride or silicide of tungsten obtained by reduced pressure horizontal reactor "Izotron 4" and of RF magnetron sputtering equipment "Oratorio-5." This technology can also be used to form a Schottky contact to n- channel MESFET.&#x0D; Since the manufacturing process of MESFET self-aligned gate provides using refractory gate material as a mask for the multiply ion implantation, the Schottky contact must withstand subsequent high-temperature heat treatment required to activate implanted impurities. In this connection, the action of high-temperature photonic and resistive heating on the barrier height of Schottky contact formed by nitride (silicide) tungsten (WNx, WSix) GaAs was also studied.&#x0D;

Vertical finFET with Salicide Contact for Potential Power Applications

We report a vertically diffused finFET with high-κ gate dielectric and metal gate for potential power applications. Electron beam lithography and deep silicon reactive ion etching (RIE) were utilized to form the fins, followed by atomic layer deposition of Al2O3 high-k dielectric and TiN to form the metal gate. Self-aligned silicide (salicide) was formed on the top of the fins to lower the contact resistance. The devices exhibit excellent performance with steep sub-threshold swing (SS), low drain-induced barrier lowering (DIBL) and a high ION/IOFF ratio. The breakdown voltage test (BVDSS) was also characterized for potential power applications.

Ni(Pt)-silicide contacts on CMOS devices: Impact of substrate nature and Pt concentration on the phase formation

Ni silicides used as contacts in source/drain and gate of advanced CMOS devices were analyzed by atom probe tomography (APT) at atomic scale. These measurements were performed on 45nm nMOS after standard self-aligned silicide (salicide) process using Ni(5at.% Pt) alloy. After the first annealing (RTA1), δ-Ni2Si was the only phase formed on gate and source/drain while, after the second annealing (RTA2), two different Ni silicides have been formed: NiSi on the gate and δ-Ni2Si on the source and drain. This difference between source/drain and gate regions in nMOS devices has been related to the Si substrate nature (poly or mono-crystalline) and to the size of the contact. In fact, NiSi seems to have difficulties to nucleate in the narrow source/drain contact on mono-crystalline Si. The results have been compared to analysis performed on 28nm nMOS where the Pt concentration is higher (10at.% Pt). In this case, θ-Ni2Si is the first phase to form after RTA1 and NiSi is then formed at the same time on source (or drain) and gate after RTA2. The absence of the formation of NiSi from δ-Ni2Si/Si(100) interface compared to θ-Ni2Si/Si(100) interface could be related to the difference of the interface energies. The redistributions of As and Pt in different silicides and interfaces were measured and discussed. In particular, it has been evidenced that Pt redistributions obtained on both 45 and 28nm MOS transistors correspond to respective Pt distributions measured on blanket wafers.

Selective Nickel Silicide Wet Etchback Chemistry for Low Temperature Anneal Process

The salicide (self-aligned silicide) technology involves selective wet etching step of non-reacted metal with respect to metal silicides. It was introduced in MOSFET fabrication due to the increase of the source, drain and gate resistances with the reduction of device dimensions. The introduction of a low resistive silicide layer on these areas has become mandatory to meet device specifications. NiSi has been widely considered for sub-65nm technology nodes due to its low resistivity, low silicon consumption and low formation temperature [1-2]. The two step annealing sequence is common in the industry for nickel silicide application to control the reverse linewidth effect. However, since Ni is the diffusing element in the NiSi reaction, a first high temperature rapid thermal anneal (RTA) will inadvertently result in Ni lateral diffusion under the spacer towards the gate causing electrical shorts. Indeed, a first low temperature anneal could seriously limit the nickel lateral diffusion and prevent this phenomenon. Minimizing thermal budget by means of reducing the temperature has also been proven to lower junction leakage current [3].

X-ray and electron response of 4H-SiC vertical interdigitated Schottky photodiodes

We report on the X-ray and electron performance of a low voltage reverse biased 4H-SiC vertical Schottky photodiode, based on the pinch-off surface effect, obtained by means of self-aligned Nickel Silicide (Ni2Si) interdigitated contacts. Although these photodiodes were original designed for UV detection their open Schottky contact is attractive for soft X-ray and low energy electron detection. The open electrode structure of the device allows the incident radiation to reach the active layer with minimal absorption. The photon counting spectroscopy response for soft X-rays is reported and compared to those predicted from a Monte Carlo model for SiC devices. We also show these devices can detect beta particles from 3H and 14C radioisotope sources with a combined energy range 1–156 keV.