Self-aligned Gate Process Research Articles

Demonstration of a lateral p-NiO/n-GaN JFET fabricated by selective-area regrowth

In this paper, we demonstrated experimentally a lateral GaN-based junction field effect transistor (JFET). A selective area regrowth of p-NiO on the as-grown n-GaN channel layer was developed by magnetron sputtering at room temperature to form the p–n junction. A self-aligned gate process and a post metal annealing process were employed to improve the device performances. The measured results show that the annealed JFET exhibits an ON/OFF ratio exceeding 106 and a higher breakdown voltage up to 814 V without any terminal structure. The breakdown voltage is determined by the reverse breakdown of parasitic PN junction between gate and drain. Further, the threshold voltage of the p-NiO/n-GaN JFET exhibits excellent temperature stability in the range of 300–500 K.

High Output Power Density of 2DHG Diamond MOSFETs With Thick ALD-Al2O3

This article reports on the high operation voltage large-signal performance of two-dimensional hole gas diamond metal-oxide semiconductor field-effect transistors (MOSFETs) with thick atomic-layer-deposition (ALD)-Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> formed on high purity polycrystalline diamond with a (110) preferential orientation. MOSFETs with a 1- μm gate-length having a gate oxide layer of 200-nm-thick Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , formed by ALD and asymmetric structures, to withstand high-voltage operations. The large-signal performances were evaluated at a quiescent drain voltage of greater than -60 V for the first time in diamond field-effect transistor (FET). As a result, an output power density of 2.5 W/mm under class-A operation at 1 GHz, which is higher than that of diamond FETs fabricated by a self-aligned gate process, was obtained. Moreover, an output power density of 1.5 W/mm was exhibited by the MOSFET when biased at a quiescent drain voltage of -40 V under class-AB operation at 3.6 GHz using an active load-pull system. This is the highest recorded value for diamond FETs at a frequency greater than 2 GHz, owing to the high-voltage operation. These results indicate that diamond p-FETs under high-voltage operations are the most suitable for high-power amplifiers with complementary circuits.

Suppression of leakage current in carbon nanotube field-effect transistors

Carbon nanotube field-effect transistor (CNT FET) has been considered as a promising candidate for future high-performance and low-power integrated circuits (ICs) applications owing to its ballistic transport and excellent immunity to short channel effects (SCEs). Still, it easily suffers from the ambipolar property, and severe leakage current at off-state originated from gate-induced drain leakage (GIDL) in CNT FETs with small bandgap. Although some modifications on device structure have been experimentally demonstrated to suppress the leakage current in CNT FETs, there is still a lack of the structure with excellent scalability, which will hamper the development of CNT FETs toward a competitive technology node. Here, we explore how the device geometry design affects the leakage current in CNT FETs, and then propose the possible device structures to suppress off-state current and check their availability through the two-dimensional (2D) TCAD simulations. Among all the proposed structures, the L-shaped-spacer CNT FET exhibits significantly suppressed leakage current and excellent scalability down to sub-50 nm with a simple self-aligned gate process. According to the simulation results, the 50 nm gate-length L-shaped-spacer CNT FET exhibits an off-state current as low as approximately 1 nA/µm and an on-current as high as about 2.1 mA/µm at a supply voltage of −1 V and then can be extended as a universal device structure to suppress leakage current for all the narrow-bandgap semiconductors based FETs.

Thin channel β-Ga2O3 MOSFETs with self-aligned refractory metal gates

We report the first demonstration of self-aligned gate (SAG) β-Ga2O3 metal-oxide-semiconductor field-effect transistors (MOSFETs) as a path toward eliminating source access resistance for low-loss power applications. The SAG process is implemented with a subtractively defined and etched refractory metal, such as Tungsten, combined with ion-implantation. We report experimental and modeled DC performance of a representative SAG device that achieved a maximum transconductance of 35 mS mm−1 and an on-resistance of ∼30 Ω mm with a 2.5 μm gate length. These results highlight the advantage of implant technology for SAG β-Ga2O3 MOSFETs enabling future power switching and RF devices with low parasitic resistance.

Synthesis of thermally stable HfOxNy as gate dielectric for AlGaN/GaN heterostructure field-effect transistors**Project supported by the National Key Research and Development Program of China (Grant No. 2017YFB0403000).

In this paper, we adopted thermally stable HfOxNy as gate dielectric for TiN/HfOxNy/AlGaN/GaN heterostructure field-effect transistors (HFETs) application. It demonstrated that the surface morphologies, composition, and optical properties of the HfOxNy films were dependent on oxygen flow rate in the O2/N2/Ar mixture sputtering ambient. The obtained metal–oxide–semiconductor heterostructure field-effect transistors by depositing HfO2 and HfOxNy dielectric at different oxygen flow rates possessed a small hysteresis and a low leakage current. After post deposition annealing at 900 °C, the device using HfOxNy dielectric operated normally with good pinch-off characteristics, while obvious degradation are observed for the HfO2 gated one at 600 °C. This result shows that the HfOxNy dielectric is a promising candidate for the self-aligned gate process.

Synthesis of titanium nitride for self-aligned gate AlGaN/GaN heterostructure field-effect transistors.

In this study, titanium nitride (TiN) is synthesized using reactive sputtering for a self-aligned gate process. The Schottky barrier height of the TiN on n-GaN is around 0.5 to 0.6 eV and remains virtually constant with varying nitrogen ratios. As compared with the conventional Ni electrode, the TiN electrode presents a lower turn-on voltage, while its reverse leakage current is comparable with that of Ni. The results of annealing evaluation at different temperatures and duration times show that the TiN/W/Au gate stack can withstand the ohmic annealing process at 800°C for 1 or 3 min. Finally, the self-aligned TiN-gated AlGaN/GaN heterostructure field-effect transistors are obtained with good pinch-off characteristics.

Nanosecond pulsed field emission from single-gate metallic field emitter arrays fabricated by molding

Electrically gated pulsed field emission from molybdenum field emitter arrays was studied. Single-gate field emitter array devices supported by metallic substrates were fabricated by a combination of molding and a self-aligned gate process. Devices were tested in a low-inductance cathode holder compatible with the high-acceleration electric field of a pulsed diode gun. Pulsed field emission down to 1.1 ns was observed for single-gate devices with 1.2×103–1.2×105 emitter tips with 5 μm array pitches. Integrating the field emitter arrays in a high-voltage pulsed diode gun, the authors demonstrated nanosecond field emission at an acceleration field of 30 MV/m at the cathode surface and acceleration of the field emission electron beam up to 300 keV. In addition, transverse beam emittance of the single-gate devices was measured with two different array sizes.

Low damage fully self-aligned replacement gate process for fabricating deep sub-100 nm gate length GaAs metal-oxide-semiconductor field-effect transistors

This article describes a process flow which has enabled the first demonstration of functional, fully self-aligned, 40 nm gate length replacement gate enhancement mode GaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with GaxGdyOz as high-κ dielectric, Pt/Au metal gate stack, and SiN sidewall spacers. The flow uses blanket metal and dielectric deposition and low damage dry etch modules. As a consequence, no critical dimension lift-off processes are required. As a gate replacement approach has been developed, the process is suitable for easily incorporating different gate metals, opening the way to work function engineering to control threshold voltage and so is a significant step forward to the demonstration of high performance “siliconlike” III-V MOSFETs.

(Invited) Germanium on Sapphire Technology

Silicon-on-sapphire (SOS) substrates have been proven to offer significant advantages in the integration of passive and active devices in RF circuits. Germanium on insulator technology is a candidate for future higher performance circuits. Thus the advantages of employing a low loss dielectric substrate other than a silicon-dioxide layer on silicon will be even greater. This paper covers the production of germanium on sapphire (GeOS) substrates by wafer bonding. The quality of the germanium back interface is studied and a tungsten self-aligned gate process MOST process has been developed. High low field mobilities of 450-500 cm2/V-s have been achieved for p-channel MOSTs produced on GeOS substrates. Thick germanium on alumina (GOAL) substrates have also been produced.

Self-Aligned-Gate ZnO TFT Circuits

We report combining plasma-enhanced atomic layer deposition (PEALD) ZnO thin-film transistors (TFTs) with a gate-self-aligned process to fabricate high-speed circuits. The speed of our previous PEALD circuits (22 ns/stage) was largely limited by the parasitic capacitance between the gate and drain, and a selfaligned-gate process provides higher speed devices and circuits. In this letter, a backside exposure process was used to fabricate gate-self-aligned TFTs with a mobility of 20 cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> /V · s. The seven-stage self-aligned-gate PEALD ZnO TFT ring oscillators had a propagation delay of 9.8 ns/stage at a supply voltage of 18 V. These ring oscillators are similar in performance to the best reported saturated-load oxide-semiconductor circuits but with much longer channel length (> 5× longer).

50-nm Self-Aligned and “Standard” T-gate InP pHEMT Comparison: The Influence of Parasitics on Performance at the 50-nm Node

Continued research into the development of III-V high-electron mobility transistors (HEMTs), specifically the minimization of the device gate length, has yielded the fastest performance reported for any three terminal devices to date. In addition, more recent research has begun to focus on reducing the parasitic device elements such as access resistance and gate fringing capacitance, which become crucial for short gate length device performance maximization. Adopting a self-aligned T-gate architecture is one method used to reduce parasitic device access resistance, but at the cost of increasing parasitic gate fringing capacitances. As the device gate length is then reduced, the benefits of the self-aligned gate process come into question, as at these ultrashort-gate dimensions, the magnitude of the static fringing capacitances will have a greater impact on performance. To better understand the influence of these issues on the dc and RF performance of short gate length InP pHEMTs, the authors present a comparison between In0.7Ga0.3As channel 50-nm self-aligned and standard T-gate devices. Figures of merit for these devices include transconductance greater than 1.9 S/mm, drive current in the range 1.4 A/mm, and fT up to 490 GHz. Simulation of the parasitic capacitances associated with the self-aligned gate structure then leads a discussion concerning the realistic benefits of incorporating the self-aligned gate process into a sub-50-nm HEMT system

SiGe on Insulator MOSFET Integrated with Schottky Source/Drain and HfO[sub 2]∕TaN Gate Stack

We demonstrate high Ge percentage thin silicon germanium on insulator (SGOI) p-channel metal-oxide-semiconductor field-effect transistor (MOSFET) using Ni-germanosilicide Schottky source/drain (S/D) and HfO 2 /TaN gate stack integrated with conventional self-aligned top gate process. Unlike high-temperature S/D activation needed for conventional transistor, low Ni-germanosilicide S/D formation temperature contributes to the excellent capacitance-voltage characteristic and low gate leakage current. SGOI structure suppresses the junction leakage problem, resulting in good agreement between the source current and drain current. In addition, extracted peak hole mobility is comparable to that of conventional bulk Ge p-MOSFET with HfO 2 /TaN gate stack.

Schottky Source/Drain Transistor on Thin SiGe on Insulator Integrated with HfO2/TaN Gate Stack

AbstractWe report thin SGOI (Silicon Germanium on Insulator) with 65% Ge concentration p- MOSFET (Metal-Oxide-Semiconductor-Field-Effect-Transistor) using Ni-germanosilicide Schottky S/D (source/drain) and HfO2/TaN gate stack integrated with conventional self-aligned top gate process. Unlike high temperature S/D activation needed for conventional transistor, low Ni-germanosilicide S/D formation temperature contributes to the excellent capacitance-voltage characteristic, low gate leakage current and hence, well-behaved transistor performance. In addition, SOI structure suppresses the junction leakage problem, resulting in good agreement between the source current and drain current of the MOSFET.

Novel technologies for the realisation of GaAs pHEMTs with 120 nm self-aligned and nanoimprinted T-gates

To address the major issues of increasing device frequency performance and reducing fabrication costs of 100 nm scale gate length III–V HEMT devices, two novel technologies developed for GaAs pHEMT are reported, namely: (i) A low resistance, non-annealed Ohmic contact technology based on a thin metallisation and highly doped In 0.2GaAs/GaAs cap layer which is compatible with a self-aligned gate process. (ii) A succinic acid based gate recess etch which selectively etches the In 0.2GaAs/GaAs cap required for the non-annealed ohmic contact technology, stopping on a 5-nm Al 0.3GaAs etch stop layer. Incorporating both of these processes, self-aligned T-gate and nanoimprinted T-gate devices have been realised. Completed self-aligned T-gate GaAs pHEMT devices of 120 nm gate length exhibited an f T and f max of 135 and 180 GHz, respectively, while nanoimprint 120 nm GaAs pHEMT devices demonstrated excellent DC characteristics, including a transconductance of 450 mS/mm.

Fabrication of T gate structures by nanoimprint lithography

Nanoimprint lithography is capable of patterning substrates with high definition patterns at relatively high patterning speeds. In this article we describe the fabrication of high resolution “T” gate resist profiles by imprint lithography. The fabrication of high resolution stamping tools and the imprinting process itself are critical to the success or failure of this technique and they are described in the article. Two different techniques were used to fabricate stamping tools. The first involved pattern definition by high resolution electron beam lithography followed by electroforming. The second involved pattern definition by electron beam lithography followed by a two stage silicon etching process. Imprinted T gate resist profiles with footwidths less than 100 nm in length were obtained on gallium arsenide substrates for the purpose of producing metallized gates for a self-aligned gate process.

Potential applications of surface channel diamond field-effect transistors

In order to realize high frequency and high power diamond devices, diamond FETs on the hydrogen-terminated diamond surface conductive layer have been fabricated. The fabricated diamond MESFETs show high breakdown voltage and output capability of 1 W mm −1. High transconductance diamond MESFET utilizing a self-aligned gate FET fabrication process has been operated in high frequency for the first time. In the 2 μm gate MESFETs, the obtained cut off frequency f T and maximum frequency of oscillation f max are 2.2 and 7 GHz, respectively. It is expected that the diamond MESFET with 0.5 μm gate length fabricated by self-aligned gate process shows 8 GHz of f T and 30 GHz of f max.

11 dB 0–50 GHz coplanar distributed amplifierIC based on0.25 µm non-recessed self-aligned gate GaAs P-HEMTs

A cascode distributed amplifier IC has been designed and fabricated using a 0.25 µm non-recessed self-aligned gate (SAG) GaAs P-HEMT and coplanar IC technology. Through the SAG process and an optimised epitaxial layer structure, excellent device performance has been obtained without gate recessing, and the device yield and uniformity were high enough for IC applications. The fabricated seven-stage cascode distributed amplifier IC has an 11 dB gain and a 3 dB bandwidth of 50 GHz with excellent uniformity in the IC characteristics. The gain-bandwidth product obtained (180 GHz) is comparable or even superior to that of the previous distributed amplifiers based on a shorter-length, recessed gate GaAs P-HEMT.

SiGe p -channel MOSFETs with tungsten gate

A self-aligned SiGe p-channel MOSFET tungsten gate process with 0.1 µm resolution is demonstrated. Interface charge densities of MOS capacitors realised with the low pressure sputtered tungsten process are comparable with thermally evaporated aluminium gate technologies (5 × 1010 cm–2 and 2 × 1011 cm–2 for W and Al, respectively). Initial results from 1 µm gate length SiGe p-channel MOSFETs using the tungsten-based process show devices with a transconductance of 33 mS/mm and effective channel mobility of 190 cm2/Vs.

DC and RF characteristics of 0.25 µm non-recessedgate GaAs P-HEMTfabricated by self-aligned gate process

A 0.25 µm non-recessed gate GaAs P-HEMT has been fabricated by using a self-aligned gate process and Pd/Ni/Ge ohmic contact. Despite the non-recessed gate structure, the device showed excellent DC and RF characteristics (average gm,max = 395 mS/mm, fT = 75 GHz and fmax = 190 GHz) with a considerable improvement in device yield and uniformity. The RF performances of the fabricated device are comparable or even superior to those of previously reported quarter-micrometre recessed gate GaAs P-HEMTs.

A novel self-aligned T-shaped gate process for deep submicron Si MOSFET's fabrication

T-shaped gate electrode is highly desired for high-speed FET fabrication since it can significantly reduce the gate resistance. In this study, we propose and demonstrate a self-aligned method of forming T-shaped gate which is suitable for ULSI Si-MOSFET's fabrication. This method employs CMP planarization, BOE selective etching and poly-Si sidewall spacer techniques to form the T-shaped poly-Si gate structure. Ti and Co silicidation were also incorporated to demonstrate the effectiveness of this process. Our experimental results indicate that the proposed process not only reduces the parasitic gate resistance, but also improves the thermal stability of the gate structure.