Selective Silicon Deposition Research Articles

Area selective deposition of silicon by plasma enhanced chemical vapor deposition using a fluorinated precursor

An Area Selective Deposition (ASD) process using Plasma-Enhanced Chemical Vapour Deposition (PECVD) is demonstrated. Using a plasma chemistry containing a fluorinated silicon precursor (SiF4), no deposition is observed on an aluminum oxide (AlOX) surface area, whereas a thin film of silicon is deposited on a silicon nitride (SiNX) surface area, while both areas are located on the same crystalline silicon substrate. The thin film deposition is characterized using spectroscopic ellipsometry, scanning electron microscopy, and atomic force microscopy, showing that 10 nm of silicon is deposited on the SiNx in 4 min. The growth on the SiNX is characterized by small grains and a rough surface, consistent with microcrystalline silicon, while no deposition or etching is observed for the AlOX surface.

Selective Deposition of Silicon at Room Temperature Using DC Microplasmas

This paper reports deposition of silicon at elevated and room temperatures in spatially localized areas of a microchip by plasma-enhanced chemical vapor deposition using microplasmas. The microplasmas are generated by providing dc power to thin-film Ti electrodes patterned on the microchip. Electrode arrangements include configurations in which multiple cathode elements share a single anode. At the operating pressures used, the plasma glow is confined to the region directly over the energized cathodes only, and the deposition is localized to these regions. A silane ambient allows Si to be deposited at 6.7-15.9 nm/min using cathode power densities of 3.65-9.35 W/cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , with the substrate heated to 300degC. At room temperature, deposition rates up to 4.2 nm/min are realized. Also described is a plasma-coupling technique that permits isolated metal pads to be powered by plasma spreading from a proximate cathode at certain levels of power and pressure. This permits controlled variations of silicon thickness in a subarray of unbiased electrodes, simplifying the powering scheme.

Low-temperature selective deposition of silicon on silicon nitride by time-modulated disilane flow and formation of silicon narrow wires

The low-temperature (410 °C) selective deposition of Si on silicon nitride has been achieved by means of the time-modulated flow of disilane while a very small amount of Si is deposited on SiO2. Very narrow (21 nm width and 28 nm thick) Si wires have been fabricated using the selective deposition. The resistivity of the Si wires fabricated by the selective deposition is much smaller (∼1/5) than that fabricated by the conventional reactive ion etching followed by annealing. This technique will be applicable to the formation of a polycrystalline silicon gate with small resistivity for the high-performance ultrasmall metal–oxide–semiconductor transistors and quantum effect devices.

Effects of Oxygen during Selective Silicon Epitaxial Growth Using Disilane and Chlorine

Using and in an ultrahigh‐vacuum rapid thermal chemical vapor deposition reactor, we have investigated the effects of oxygen introduced during selective silicon deposition for both chlorinated and nonchlorinated process chemistries. The effects of oxygen have been investigated with regard to oxygen incorporation, selectivity with respect to thermal , growth rate, and epitaxial structure. Initial studies have revealed that during silicon depositions from , the inherent selectivity of to is enhanced upon the addition of oxygen to the process ambient. Furthermore, using a nonchlorinated process chemistry, oxygen adsorbs predominantly at the epitaxy‐substrate interface and causes increased surface roughness. We have found, however, that the addition of chlorine can play a significant role in the passivation of the epitaxy‐substrate interface with oxygen and improves the resulting film's surface morphology. © 1999 The Electrochemical Society. All rights reserved.

Effects of oxygen on selective silicon deposition using disilane

Using Si 2H 6 in an ultrahigh vacuum rapid thermal chemical vapor deposition reactor, we have investigated the role of high levels of oxygen (>5×10 −6 Torr) introduced during selective silicon deposition. The effects of oxygen have been investigated with regard to oxygen incorporation, selectivity with respect to thermal SiO 2, growth rate, and epitaxial quality. The addition of oxygen was found to enhance the inherent process selectivity of Si 2H 6 to SiO 2 while causing no reduction in the silicon growth rate or measurable oxygen incorporation into the growing film for oxygen pressures below 5×10 −5 Torr. Contrary to published reports, the silicon film was devoid of the pyramidal defects usually characteristic to highly oxygenated processes. The silicon surface morphology, however, exhibited increased roughness with increasing oxygen partial pressure. The surface roughness is believed to be a result of the high levels of oxygen adsorbed at the initial growth surface.

Effects on Selective CVD of Titanium Disilicide by Substrate Doping and Selective Silicon Deposition

AbstractDuring selective chemical vapor deposition (CVD) of titanium disilicide on silicon, consumption of As implanted silicon substrates is enhanced relative to Si substrates implanted with other species. In this study, a selective epitaxially grown Si (SEG Si) layer has been deposited prior to selective CVD of titanium disilicide on samples with different implanted doses of either As or B. If no SEG Si film is deposited, the selective CVD TiSi2 film properties strongly depended on dopant type (As vs. B) and on dopant dose. Addition of a SEG Si film prior to selective CVD TiSi2 improves process stability as a function of changes in initial ion implanted conditions. Use of a SEG Si film prior to selective CVD TiSi2 results in values of TiSi2 thickness and TiSi2 sheet resistance which are approximately constant as a function of initial ion implant dose, and are approximately equal for both the As and B implanted samples used in this study.

The Design and Fabrication of 0.35 µm Single-Polysilicon Self-Aligned Bipolar Transistors

Two innovative process technologies are introduced to overcome problems related to the downscaling of single-polysilicon self-aligned bipolar transistors. First, the use of a selective silicon deposition step before Ti salicidation of the structure is shown to improve TiSi2 formation on narrow As-doped polysilicon emitters. At the same time, the elevation of the extrinsic base regions around the emitter causes a significant reduction of peripheral electron recombination effects. Second, the implantation of the intrinsic base at a large tilt angle (LATIB) is demonstrated to suppress emitter-to-collector punchthrough along the isolation edges. The first 0.35 µm single-polysilicon self-aligned bipolar transistors fabricated using a 200 mm complementary metal oxide semiconductor (CMOS) derived bipolar process integrating these novel process technologies are described.

Optimization of Process Conditions for Selective Silicon Epitaxy Using Disilane, Hydrogen, and Chlorine

We have previously reported a process for low temperature selective silicon epitaxy using , and in an ultrahigh vacuum rapid thermal chemical vapor deposition reactor. Selective deposition implies that growth occurs on the Si surface but not on any of the surrounding insulator surfaces. Using this method and process chemistry, the level of Cl species required to maintain adequate selectivity has been greatly reduced in comparison to ‐based, conventional CVD approaches. In this report, we have extended upon the previous work and provide information regarding the selectivity of the silicon deposition process to variations in the growth conditions. We have investigated the selectivity of the process to variations in disilane flow/partial pressure, growth temperature, and system contamination. We demonstrate that increases in either the partial pressure or flow rate, the process temperature, or the source contamination levels can lead to selectivity degradation. In regard to the structural quality of the selective epitaxial layers, we have observed epitaxial defects that have appeared to be a strong function of two basic conditions: the contamination level of the process and the chlorine flow rate or chlorine partial pressure. Overall, the results in this study indicate several process conditions that can inhibit the quality of a selective silicon deposition process developed for single‐wafer manufacturing.

Low-resistance self-aligned Ti-silicide technology for sub-quarter micron CMOS devices

A low-resistance self-aligned Ti-silicide process featuring selective silicon deposition and subsequent pre-amorphization (SEDAM) is proposed and characterized for sub-quarter micron CMOS devices. 0.15-/spl mu/m CMOS devices with low-resistance and uniform TiSi/sub 2/ on gate and source/drain regions were fabricated using the SEDAM process. Non-doped silicon films were selectively deposited on gate and source/drain regions to reduce suppression of silicidation due to heavily-doped As in the silicon. Silicidation was also enhanced by pre-amorphization, using ion-implantation, on the narrow gate and source/drain regions. Low-resistance and uniform TiSi/sub 2/ films were achieved on all narrow, long n/sup +/ and p/sup +/ poly-Si and diffusion layers of 0.15-/spl mu/m CMOS devices. TiSi/sub 2/ films with a sheet resistance of 5 to 7 /spl Omega//sq were stably and uniformly formed on 0.15-/spl mu/m-wide n/sup +/ and p/sup +/ poly-Si. No degradation in leakage characteristics was observed in pn-junctions with TiSi/sub 2/ films. It was confirmed that, using SEDAM, excellent device characteristics were achieved for 0.15-/spl mu/m NMOSFET's and PMOSFET's with self-aligned TiSi/sub 2/ films.

Selective Deposition of Silicon and Silicon-Germanium Alloys by Rapid Thermal Chemical Vapor Deposition

AbstractSelective deposition of SiGe alloys by rapid thermal deposition has been studied using a commercially available Rapid Thermal Chemical Vapor Deposition (RTCVD) cluster tool. The precursors used in this work were dichlorosilane and germane diluted in either hydrogen or argon. An initial characterization was performed to find the appropriate temperature and GeH4 flow ranges to deposit epitaxial layers with low surface roughness. For layers with higher germanium concentration lower deposition temperatures are required to minimize surface roughness. The effects of the dilutant gas on the deposition were examined. An H2 dilutant affects the deposition by consuming chlorine released by the SiCl2H2 and forming HCI. When Ar is used as the dilutant, more chlorine is available for other reactions that can result in etching of the silicon surface. Finally, the effects of pre-deposition treatment were determined. When compared to a wet HF dip, a gas/vapor phase HF/methanol native oxide removal treatment appears to increase the initiation time for the epitaxial deposition reaction. This is most likely due to increased fluorine termination of the surface. When a wet HF or HF/methanol native oxide removal is followed by a UV-Cl2 process, the deposition reaction initiation time is reduced. The UV-Cl2 process was also found to etch silicon through the native oxide.

Progress in large area Selective Silicon Deposition for TFT/LCD Applications

We have previously demonstrated selective area deposition of n+ Macrocrystalline silicon at 250°C using time modulated silane flow into a hydrogen plasma, and applied the technique to form high performance top-gate Amorphous silicon TFT's with two mask sets. In this paper, we discuss issues related to process scale-up, including the effect of deposition rate on selectivity loss and non-uniformity. Uniformity can be achieved with higher growth rates by expanding the window for selectivity, and using conditions well within the process limits. We show that lower pressure and higher rf power can enlarge the window by enhancing the hydrogen-Mediated silicon etching.

Progress in Large Area Selective Silicon Deposition for TFT/LCD Applications

AbstractWe have previously demonstrated selective area deposition of n+ microcrystalline silicon at 250°C using time modulated silane flow into a hydrogen plasma, and applied the technique to form high performance top-gate amorphous silicon TFT's with two mask sets. In this paper, we discuss issues related to process scale-up, including the effect of deposition rate on selectivity loss and non-uniformity. Uniformity can be achieved with higher growth rates by expanding the window for selectivity, and using conditions well within the process limits. We show that lower pressure and higher rf power can enlarge the window by enhancing the hydrogen-mediated silicon etching.

Selective Deposition of Silicon by Mercury Sensitized Photochemical Vapor Deposition

The authors have developed a low-temperature process for selective deposition of silicon by mercury sensitized photochemical vapor deposition (Photo-CVD) without using ultraclean technology. It was found that hydrogen radical pretreatment was required to obtain selective deposition. There was an incubation period for not only SiO2 surface but also Si surface. It was confirmed that mercury sensitized Photo-CVD is a promising method for selective deposition process at low temperature using large-area glass substrate.

Selective deposition of silicon by plasma-enhanced chemical vapor deposition using pulsed silane flow

We report a new low-temperature (&amp;lt;300 °C) process for selective deposition of silicon using time modulated flow of silane into a hydrogen plasma. Time modulated gas flow allows the chemical processes associated with deposition and surface modification or etching to occur sequentially, and be controlled independently, giving an additional degree of freedom to the deposition process. The observed selective deposition is consistent with substrate specific nucleation, and preferential etching of the nuclei during the hydrogen plasma exposure. The application of the selective deposition process to the fabrication of thin-film transistor structures is also presented.

A self-aligned elevated source/drain MOSFET

An advanced elevated source/drain CMOS process which features self-aligned lightly-doped drain (LDD) and channel implantation is described. Unlike conventional elevated source/drain structures which employ separate polysilicon deposition steps to define the source/drain and gate electrodes, this new structure provides self-alignment of the LDD regions with the heavily doped channel regions to avoid dopant compensation effects. This process employs a single selective silicon deposition step to define both the epitaxial source/drain and polycrystalline gate regions. A single sidewall spacer is used for both LDD and salicide definition. Unlike conventional elevated source/drain CMOS processes, the final MOSFET structure provides self-alignment of the LDD regions with the heavily doped channel regions. Salicidation is performed after selective silicon deposition to provide low sheet resistances for the source/drain and gate regions. Small-geometry NMOS and PMOS devices have been fabricated which display excellent short channel behavior. >

Application of selective silicon epitaxial growth for CMOS technology

The application of selective silicon epitaxial growth for device isolation is described. An improved selective epitaxial isolation technology is presented in the fabrication of CMOS LSI. This advanced process technology results from a superior selectivity for selective silicon deposition. A CMOS ring oscillator with a twin-well structure is fabricated by using this selective epitaxial isolation technology. The feasibility of using an oversized contact, due to the nature of its steeper oxide-to-silicon isolation boundary, is demonstrated.