Second-order Phase-locked Loop Research Articles

ON THE DESIGN OF ADAPTIVE-BANDWIDTH ALL-DIGITAL PHASE-LOCKED LOOPS

The second-order adaptive-bandwidth all-digital phase-locked loop (ADB-ADPLL) is designed and analyzed by using a new design procedure. Based on a discrete-time analogy of a continuous-time PLL (CTPLL) with the z-transform, the design criterion of the ADB-ADPLL is derived and a design procedure is developed. Following the design criterion, the ADB-ADPLL can adapt its system parameters to balance the loop noise bandwidth and lock-in time. According to the design criterion, the ratio of the loop bandwidth to the reference input frequency can be maintained as a constant if the sampling frequency is a fixed multiplier of the input frequency. An example is given to illustrate the design procedure and simulation results are presented to validate the adaptive characteristics with respect to the phase noise and varying bands of input frequency.

An exact formula for the half-plane pull-in range of a PLL

Abstract A second-order phase-lock loop (PLL) that is based on a triangular-characteristic phase detector and imperfect-integrator loop filter is found in many applications where simplicity and economics are major considerations. For many of these applications, digital-logic-compatible reference and VCO signals are used, an exclusive-OR gate implements the phase detector, and the loop filter is constructed from passive components. When designing these loops, the half-plane pull-in range Ω 2 is of interest. Until now, this important loop parameter could only be calculated by using a computer-based technique that numerically integrated the nonlinear differential equation that describes the PLL model. This requirement/limitation is removed here by the development of an exact closed-form formula for Ω 2 , the main contribution of this paper. More generally, the value of Ω 2 is dependent on the PLL phase detector characteristic that is used, be it triangular, sinusoidal, or something else. With regard to the value of Ω 2 produced, a comparison is given of two PLLs, both described by the same linear model so that the comparison is meaningful. The first PLL is based on a triangular-characteristic phase detector; the second loop is based on a sinusoidal phase detector.

Low C/N0 Carrier Tracking Loop Based on Optimal Estimation Algorithm in GPS Software Receivers

Suppressing jitter noises in a phase locked loop(PLL) is of great importance in order to keep precise and continuous track of global positioning system(GPS) signals characterized by low carrier-to-noise ratio(C/N0). This article proposes and analyzes an improved Kalman-filter-based PLL to process weak carrier signals in GPS software receivers. After reviewing the optimal-bandwidth-based traditional second-order PLL, a Kalman-filter-based estimation algorithm is implemented for the new PLL by decorrelating the model error noises and the measurement noises. Finally, the efficiency of this new Kalman-filter-based PLL is verified by experimental data. Compared to the traditional second-order PLL, this new PLL is in position to make correct estimation of the carrier phase differences and Doppler shifts with less overshoots and noise disturbances and keeps an effective check on the disturbances out of jitter noises in PLL. The results show that during processing normal signals, this improved PLL reduces the standard deviation from 0. 010 69 cycle to 0. 007 63 cycle, and for weak signal processing, the phase jitter range and the Doppler shifts can be controlled within ±17° and ±5 Hz as against ±25° and ±15 Hz by the traditional PLL.

Design constraints for third-order PLL nodes in master-slave clock distribution networks

Clock signal distribution in telecommunication commercial systems usually adopts a master-slave architecture, with a precise time basis generator as a master and phase-locked loops (PLLs) as slaves. In the majority of the networks, second-order PLLs are adopted due to their simplicity and stability. Nevertheless, in some applications better transient responses are necessary and, consequently, greater order PLLs need to be used, in spite of the possibility of bifurcations and chaotic attractors. Here a master-slave network with third-order PLLs is analyzed and conditions for the stability of the synchronous state are derived, providing design constraints for the node parameters, in order to guarantee stability and reachability of the synchronous state for the whole network. Numerical simulations are carried out in order to confirm the analytical results.

Impact of Gate Leakage on Performances of Phase-Locked Loop Circuit in Nanoscale CMOS Technology

In the nanoscale CMOS technology, the thin gate oxide causes large gate-tunneling leakage. In this brief, the influence of gate-tunneling leakage in the MOS capacitor (used in the loop filter) on the circuit performance of the phase-locked loop (PLL) in the nanoscale CMOS technology has been investigated and analyzed. The basic PLL with a second-order loop filter is used to observe the impact of gate-tunneling leakage on the performance degradation of the PLL in a 90-nm CMOS process. The MOS capacitors with different oxide thicknesses are used to investigate their impact on the PLL performance. The locked time, static phase error, and jitter of the second-order PLL are found to be degraded by the gate-tunneling leakage of the MOS capacitor used in the loop filter.

Reachability of the synchronous state in a mutually connected PLL network

Second-order phase locked loops (PLLs) are devices that are able to provide synchronization between the nodes in a network even under severe quality restrictions in the signal propagation. Consequently, they are widely used in telecommunication and control. Conventional master–slave (M–S) clock-distribution systems are being replaced by mutually connected (MC) ones due to their good potential to be used in new types of application such as wireless sensor networks, distributed computation and communication systems. Here, by using an analytical reasoning, a nonlinear algebraic system of equations is proposed to establish the existence conditions for the synchronous state in an MC PLL network. Numerical experiments confirm the analytical results and provide ideas about how the network parameters affect the reachability of the synchronous state. The phase-difference oscillation amplitudes are related to the node parameters helping to design PLL neural networks. Furthermore, estimation of the acquisition time depending on the node parameters allows the performance evaluation of time distribution systems and neural networks based on phase-locked techniques.

Using bifurcations in the determination of lock-in ranges for third-order phase-locked loops

Transmission and switching in digital telecommunication networks require distribution of precise time signals among the nodes. Commercial systems usually adopt a master-slave (MS) clock distribution strategy building slave nodes with phase-locked loop (PLL) circuits. PLLs are responsible for synchronizing their local oscillations with signals from master nodes, providing reliable clocks in all nodes. The dynamics of a PLL is described by an ordinary nonlinear differential equation, with order one plus the order of its internal linear low-pass filter. Second-order loops are commonly used because their synchronous state is asymptotically stable and the lock-in range and design parameters are expressed by a linear equivalent system [Gardner FM. Phaselock techniques. New York: John Wiley & Sons; 1979]. In spite of being simple and robust, second-order PLLs frequently present double-frequency terms in PD output and it is very difficult to adapt a first-order filter in order to cut off these components [Piqueira JRC, Monteiro LHA. Considering second-harmonic terms in the operation of the phase detector for second order phase-locked loop. IEEE Trans Circuits Syst I 2003;50(6):805–9; Piqueira JRC, Monteiro LHA. All-pole phase-locked loops: calculating lock-in range by using Evan’s root-locus. Int J Control 2006;79(7):822–9]. Consequently, higher-order filters are used, resulting in nonlinear loops with order greater than 2. Such systems, due to high order and nonlinear terms, depending on parameters combinations, can present some undesirable behaviors, resulting from bifurcations, as error oscillation and chaos, decreasing synchronization ranges. In this work, we consider a second-order Sallen-Key loop filter [van Valkenburg ME. Analog filter design. New York: Holt, Rinehart & Winston; 1982] implying a third order PLL. The resulting lock-in range of the third-order PLL is determined by two bifurcation conditions: a saddle-node and a Hopf.

Linear Approach for Synchronous State Stability in Fully Connected PLL Networks

Synchronization is an essential feature for the use of digital systems in telecommunication networks, integrated circuits, and manufacturing automation. Formerly, master‐slave (MS) architectures, with precise master clock generators sending signals to phase‐locked loops (PLLs) working as slave oscillators, were considered the best solution. Nowadays, the development of wireless networks with dynamical connectivity and the increase of the size and the operation frequency of integrated circuits suggest that the distribution of clock signals could be more efficient if distributed solutions with fully connected oscillators are used. Here, fully connected networks with second‐order PLLs as nodes are considered. In previous work, how the synchronous state frequency for this type of network depends on the node parameters and delays was studied and an expression for the long‐term frequency was derived (Piqueira, 2006). Here, by taking the first term of the Taylor series expansion for the dynamical system description, it is shown that for a generic network with N nodes, the synchronous state is locally asymptotically stable.

A Design Procedure for All-Digital Phase-Locked Loops Based on a Charge-Pump Phase-Locked-Loop Analogy

In this brief, a systematic design procedure for a second-order all-digital phase-locked loop (PLL) is proposed. The design procedure is based on the analogy between a type-II second-order analog PLL and an all-digital PLL. The all-digital PLL design inherits the frequency response and stability characteristics of the analog prototype PLL

A 1.8-GHz Spur-Cancelled Fractional-N Frequency Synthesizer With LMS-Based DAC Gain Calibration

A 1.8-GHz wideband DeltaSigma fractional-N frequency synthesizer achieves the phase noise performance of an integer-N synthesizer using a spur-cancellation digital-to-analog converter (DAC). The DAC gain is adaptively calibrated with a least-mean-square (LMS) sign-sign correlation algorithm for better than 1% DAC and charge pump (CP) gain matching. The proposed synthesizer phase-locked loop (PLL) is demonstrated with a wide 400-kHz loop bandwidth while using a low 14.3-MHz reference clock, and offers a better phase noise and bandwidth tradeoff. Using an 8-bit gain-calibrated DAC, DeltaSigma-shaped divider ratio noise is suppressed by as much as 30 dB. The second-order DeltaSigma fractional-N PLL exhibits in-band and integrated phase noises of -98 dBc/Hz and 0.8deg. The chip, fabricated in 0.18-mum CMOS, occupies 2 mm2, and consumes 29 mW at 1.8-V supply. The spur cancellation and correlation function consumes 30% additional power

Double-frequency jitter in chain master-slave clock distribution networks: Comparing topologies

Master-slave (M-S) strategies implemented with chain circuits are the main option in order to distribute clock signals along synchronous networks in several telecommunication and control applications. Here, we study the two types of master-slave chains: Without clock feedback, i.e., one-way master-slave (OWMS) and with clock feedback, i.e., two-way master-slave (TWMS) considering the slave nodes as second-order phase-locked loops (PLL) for several types of loop low-pass filters.

Effect of loop delay on phase margin of first-order and second-order control loops

This paper analyzes the phase margin of first-order and second-order control loops in the presence of a loop delay and establishes rules of thumb on the maximum permissible delay for a given phase margin. Both discrete-time and continuous-time loops are considered. Results are applicable, for example, to adaptive filters and to first-order and second-order phase-locked loops.

Phase error dynamics of a class of modified second-order digital phase-locked loops in the background of cochannel interference

The present paper examines the dynamics of a nonuniform sampling second-order digital phase-locked loop (NUS-DPLL) with an effectively modified loop filter. Through an analytical study of the system response around the steady state, supported by detailed simulation results, the paper establishes the better performance of the modified DPLL. It has been shown by a simulation study as well as explained qualitatively, that the modified DPLL will be able to withstand the adverse effects of cochannel interference signals better than the conventional NUS-DPLL.

Using central manifold theorem in the analysis of master-slave synchronization networks

This work presents a stability analysis of the synchronous state for one-way master-slave time distribution networks with single star topology. Using bifurcation theory, the dynamical behavior of second-order phase-locked loops employed to extract the synchronous state in each node is analyzed in function of the constitutive parameters. Two usual inputs, the step and the ramp phase perturbations, are supposed to appear in the master node and, in each case, the existence and the stability of the synchronous state are studied. For parameter combinations resulting in non-hyperbolic synchronous states the linear approximation does not provide any information, even about the local behavior of the system. In this case, the center manifold theorem permits the construction of an equivalent vector field representing the asymptotic behavior of the original system in a local neighborhood of these points. Thus, the local stability can be determined.

Bifurcation Analysis for Third-Order Phase-Locked Loops

Second-order phase-locked loops (PLLs) are extensively used in applications related to recovering clock signals for synchronous demodulation in telecommunication networks. In situations where an improvement of the transient response of the local clocks is necessary, third-order PLLs are employed. Here, we use concepts taken from dynamical system theory for analytically determining the capture range of three nonlinear third-order PLLs subject to a ramp input. We show that saddle-node, saddle-saddle, and Hopf bifurcations can be produced by varying the values of the input signal velocity and of the PLL parameters, providing criteria for designing such PLLs.

A Collocation-Based Algorithm for Computing the Pull-In Range of a Class of Phase-Locked Loops

The pull-in range (ωp) of a phase-locked loop (PLL) is defined as the maximum value of loop detuning ω0s for which pull-in occurs from anywhere on the PLL's phase plane. That is, pull-in is guaranteed from anywhere on the phase plane if ω0s <ω p. Simple approximation is available for computing ωp for the high gain PLL where saddle-node bifurcation occurs at ω0s = ωp. Unlike the high gain case, a simple approximation for ωp is not available for the low gain case where bifurcation from a separatrix cycle occurs at ω0s = ωp. The vector field model for a class of second-order PLLs is shown to have rotational properties, which imply the existence of a separatrix cycle. The external stability of this separatrix cycle is an indicator of the type of bifurcation (saddle- node or separatrix cycle) which terminates the limit cycle associated with the PLL's stable false lock state and the PLL pulls-in (i.e. achieve phase lock). A formula is given for determining the separatrix cycle's stability, which indicates that the separatrix cycle is externally stable for small values of closed loop gain. A collocation- based algorithm is presented for computing the PLL's separatrix cycle and the value of pull-in range frequency ω0s = ωp at which a stable separatrix cycle exists.

Considering second-harmonic terms in the operation of the phase detector for second-order phase-locked loop

We study the influence of the double-frequency term in the operation of the nonlinear second-order phase-locked loop (PLL). We show that oscillations around the synchronous state obtained from simplified models are unavoidable and we give, in analytical and graphical form, an approximated expression of how the amplitude of the oscillations depends on the normalized loop gain. Numerical simulations confirm the results providing some hints about how to set the PLL gain.

Sincronismo em redes mestre-escravo com atraso

Estuda-se o comportamento dinâmico de redes de telecomunicações síncronas, frente a variações lentas causadas pela degradação dos osciladores que compõem a rede. Esses osciladores são malhas de sincronismo de fase (''phase-locked loops'' - PLLs). Através da Teoria de Sistemas Dinâmicos, analisam-se os comportamentos de um PLL de segunda ordem isolado e desse PLL formando redes mestre-escravo do tipo cadeia simples e do tipo enlace simples. O atraso na propagação do sinal entre os osciladores é levado em consideração. Discute-se a influência dos valores dos parâmetros dos osciladores na existência e na estabilidade da solução síncrona, para redes constituídas de um mestre e um escravo. Na rede cadeia simples, o atraso impede a existência de solução síncrona; na rede enlace simples, tal solução só pode existir quando são iguais os tempos de propagação do sinal do mestre para o escravo e do escravo para o mestre.

Computing with phase locked loops: choosing gains and delays

We simulate a four-node fully connected phase-locked loop (PLL) network with an architecture similar to the neural network proposed by Hoppensteadt and Izhikevich (1999, 2000), using second-order PLLs. The idea is to complement their work analyzing some engineering questions like:how the individual gain of the nodes affects the synchronous state of whole network; how the individual gain of the nodes affects the acquisition time of the whole network; how close the free-running frequencies of the nodes need to be in order to the network be able to acquire the synchronous state; how the delays between nodes affect the synchronous state frequency. The computational results show that the Hoppensteadt-Izhikevich network is robust to the variation of these parameters and their effects are described through graphics showing the dependence of the synchronous state frequency and acquisition time with gains, free-running frequencies, and delays.

Jitter optimization based on phase-locked loop design parameters

This paper investigates the effects of varying phaselocked loop (PLL) design parameters on timing jitter. The noise due to voltage-controlled oscillator (WO), input clock and buffering clock are considered. First, a closed-form equations are derived that relate PLL output clock jitter to parameters of a second-order PLL, i.e., damping factor and bandwidth. Then the second-order analysis is extended to a third-order PLL with inherent feedback/sampling delay. The sensitivity study clearly illustrates how to select design parameters to obtain minimum output jitter. To verify the analysis experimentally, a digitally tunable PLL architecture is designed and fabricated that allows independent adjustment of loop parameters. The design not only demonstrates the agreement between analysis and theory, but also shows an architecture that minimizes jitter.