Secco Etching Research Articles

High-Rate Epitaxial Growth of Silicon Using Electron Beam Evaporation at High Temperatures

This paper describes the high-rate (~1.5 μm/min) growth of Si films on Si supporting substrates with (100) crystallographic orientation at 600 °C, 800 °C, and 1000 °C in a vacuum environment of ~1 × 10−5 mbar using electron beam (e-beam) evaporation. The microstructure, crystallinity, and conductivity of such films were investigated. It was established that fully crystalline (Raman spectroscopy, EBSD) and stress-free epi-Si layers with a thickness of approximately 50 µm can be fabricated at 1000 °C, while at 600 °C and 800 °C, some poly-Si inclusions were observed using Raman spectroscopy. Hall effect measurements showed that epi-Si layers deposited at 1000 °C had resistivity, carrier concentration, and mobility comparable to those obtained for c-Si wafers fabricated through ingot growth and wafering using the same solar grade Si feedstock used for the e-beam depositions. The dislocation densities were determined to be ∼2 × 107 cm−2 and ∼5 × 106 cm−2 at 800 and 1000 °C, respectively, using Secco etch. The results highlight the potential of e-beam evaporation as a promising and cost-effective alternative to conventional CVD for the growth of epi-Si layers and, potentially, epi-Si wafers. Some of the remaining technical challenges of this deposition technology are briefly indicated and discussed.

Study of Flow Pattern Defects and Oxidation Induced Stacking Faults in Czochralski Single-Crystal Silicon Growth

This paper emphasizes that the furnace pressure, crucible rotation, and pulling rate have important effects on interstitial oxygen (Oi) concentrations and micro-defects during growth in a Czochralski single-crystal silicon (CZ-Si) growth furnace. Since oxygen in a silicon ingot influences minority carrier lifetime, different set-points of furnace pressure and crucible rotation were controlled to achieve different degrees of Oi. The Oi content has a positive correlation with furnace pressure and crucible rotation. Various numbers of micro-defects were generated under the influence of different pulling rates, owing to the transformation from liquid to solid. The sample also underwent Secco etching and a high-temperature wet oxidation to observe defects caused by the Oi concentration and pulling rate, namely, flow pattern defects (FPDs) and oxidation-induced stacking faults (OISFs). Optical microscopy was employed to confirm the surface topography, and for defect number counting, to observe the correlation between the defects and the minority carrier lifetime. The overall results show that the minority carrier lifetime is mainly dominated by OISFs under high Oi content and FPDs under low Oi content. Therefore, growth using a CZ-Si growth furnace should be carried out with low furnace pressure, low crucible rotation, and low pulling rate to reduce micro-defects.

Single-Crystal Islands (SCI) for Monolithic 3-D and Back-End-of-Line FinFET Circuits

A single-crystal islands (SCI) technique using low thermal budget pulse laser process is proposed and demonstrated to fabricate single-crystal silicon islands over amorphous dielectric for monolithic 3-D and back-end-of-line (BEOL) FinFET circuits. By laser recrystallizing mask-defined a-Si islands encapsulated with conformal silicon nitride film, designed single-crystal Si islands can be obtained. The single crystallinity of the island are verified with SECCO Etch, high-resolution electron microscopy (HREM), transmission electron microscopy (TEM), and electron backside scattering (EBSD). About 40 nm FinFETs were successfully fabricated in the SCI Si islands and shown to exhibit excellent electrical performance and low variability that are compatible with the FinFETs fabricated on commercial silicon-on-insulator (SOI) wafer.

Laser crystallized low-loss polycrystalline silicon waveguides

We report the fabrication of low-loss, low temperature deposited polysilicon waveguides via laser crystallization. The process involves pre-patterning amorphous silicon films to confine the thermal energy during the crystallization phase, which helps to control the grain growth and reduce the heat transfer to the surrounding media, making it compatible with CMOS integration. Micro-Raman spectroscopy, Secco etching and X-ray diffraction measurements reveal the high crystalline quality of the processed waveguides with the formation of millimeter long crystal grains. Optical losses as low as 5.3 dB/cm have been measured, indicating their suitability for the development of high-density integrated circuits.

Epitaxial Growth of Ge Strain Relaxed Buffer on Si with Low Threading Dislocation Density

Germanium, with its superior electron and hole mobility compared to Si, is considered as a channel material in future CMOS technology [1]. The band gap of Ge makes it attractive in optoelectronic devices. However, integration of crystalline Ge on Si wafers is challenging due to the high lattice mismatch, leading to misfit and threading dislocations in Ge strain relaxed buffers (SRBs) grown on Si. Threading dislocations reaching the device layer can degrade the carrier mobility and increase the junction leakage current of MOSFETs and photodetectors. Several groups have reported that threading dislocation density (TDD) can be reduced by implementing a two-step growth (Step 1: T~400°C, Step 2: T~600-800°C) and using post growth anneal and/or cyclic thermal annealing TDDs~107cm- 2 has been demonstrated for SRB thicknesses ~1µm [1]. Even lower TDDs~106cm-2 has been achieved by increasing the SRB thickness >3µm [2]. In this work, we show that further reduction of the Ge growth temperature during the initial step to less than 300°C together with Ge2H6 as precursor enables a 0.5µm thin Ge SRB with TDDs as low as 4·104cm- 2.The Ge SRB was grown on (100) oriented Si wafers by reduced pressure (20 torr) chemical vapor deposition (CVD) using Ge2H6 as precursor and H2 as carrier gas. Dopant sources were PH3 and B2H6 for n- and p-type Ge SRB, respectively. HF last Si wafers were loaded into the CVD reactor followed by a 2 min H2 bake at T=1050°C. The temperature was ramped down to 280°C and Ge2H6 was introduced in the chamber followed by a temperature ramp up to 300°C for 20 min growing a 40nm strained relaxed Ge layer. The temperature was ramped up to 600°C in H2 followed by the growth of a 460nm thick Ge layer. For comparison, a 3µm thick Ge SRB was deposited with the conventional method; i.e. first layer grown at T=400°Cfollowed by the second layer at T=600°C and post growth annealing at T=800°C.The grown Ge SRB was subjected to wet chemical etching using SECCO solution (K2Cr2O7:H2O:HF) in order to delineate the threading dislocations. TDD was determined by counting delineated defects on images obtained from dark field optical microscope, AFM and SEM. High Resolution Reciprocal Mapping (HRRLM) was used to compare crystalline quality and XTEM was implemented to image the defects at the interfaces. Surface morphology and roughness were investigated using AFM.Fig. 1 shows AFM images of the surface morphology for temperature ramped (T=280-300°C) Ge SRB (left image) and conventional (T=400°C) Ge SRB (right image). The images indicate that the strain relaxation occurred through pit formation in the temperature ramped Ge SRB while in the conventional Ge SRB, the strain relaxed through island and valley formation. Similar relaxation through pit formation has been found in Ge grown on Si at T=290°C [3]. The pits are formed in the first grown Ge layer at T=280-300ᵒC where the low temperature allows Ge growth in 2D mode instead of 3D. The 2D growth mode enables low TDD in the Ge layer grown at T=600°C. Fig. 2 shows dark field optical microscope images of the Ge SRB after delineation of the threading dislocations by SECCO etching. For the conventional 3µm thick Ge SRB (right image) a TDD~107cm-2 was measured. The Ge SRB with the temperature ramped (T=280-300°C) exhibits a comparably low TDD~4·104cm-2. Fig. 3 displays reported TDDs in grown Ge SRBs together with the TDDs achieved in this work. The conventionally 3µm thick Ge SRB (T=400°C) exhibits a TDD well in accordance with what has been reported in the literature. The Ge SRB grown with an initial temperature ramp (T=280-300°C) exhibits about 3 decades lower TDD at the same thickness compared to literature data.In conclusion, we have shown that by using Ge2H6 and optimizing the temperature profile of the initial Ge growth it is possible to grow a 0.5µm thin Ge SRB on Si with a threading dislocation density ~4·104cm-2without any post growth annealing.[1] H.-C. Luan, D. R. Lim, K. K. Lee, K. M. Chen, J. G. Sandland, K. Wada, and L. C. Kimerling, Appl. Phys. Lett., vol. 75, no. 1999, p. 2909, 1999.[2] Y. Yamamoto, P. Zaumseil, T. Arguirov, M. Kittler, and B. Tillack, Solid. State. Electron., vol. 60, no. 1, pp. 2–6, 2011. [3] B. W. Cheng, H. Y. Xue, D. Hu, G. Q. Han, Y. G. Zeng, A. Q. Bai, C. L. Xue, L. P. Luo, Y. H. Zuo, and Q. M. Wang, 5th Int. Conf. Gr. IV Photonics, GFP, pp. 140–142, 2008. Figure 1

Epitaxial Growth of Ge Strain Relaxed Buffer on Si with Low Threading Dislocation Density

Epitaxial Ge with low dislocation density is grown on a low temperature grown Ge seed layer on Si substrate by reduced pressure chemical vapor deposition. The surface topography measured by AFM shows that the strain relaxation occurred through pit formation which resulted in freezing the defects at Ge/Si interface. Moreover a lower threading dislocation density compared to conventional strain relaxed Ge buffers on Si was observed. We show that by growing the first layer at temperatures below 300 °C a surface roughness below 1 nm can be achieved together with enhancement carrier mobility. The different defects densities revealed from SECCO and Iodine etching shows that the defects types have been changed and SECCO is not always trustable.

(Invited) Strained SiGe on Insulator FinFETs: a P-FET Candidate for 10nm Node

Performance enhancement using conventional stress elements such as stress liners or embedded source/drain is significantly decreased at extremely tight gate pitch, required for 10nm node and beyond [1]. This issue is more pronounced for non-planar architectures such as FinFETs, especially those made on SOI substrates. For p-type MOSFETs, SiGe is a great candidate due to its intrinsic lower effective mass and better transport properties than Si. SiGe has been utilized in CMOS industry for IBM SOI 32nm and 22nm generations, as a knob to adjust the PFET threshold voltage and performance enhancement [2, 3]. However, it is shown that SiGe with moderate Ge content and no strain does not provide noticeable short-channel benefit over Si and as a result, strain plays a significant role in high-performance SiGe channel pFETs [4]. While higher Ge content SiGe materials can offer lower effective mass and have potential for better transport properties [5], their reduced bandgap by increasing Ge content brings concern for some CMOS applications. This results in increased gate-induced drain leakage and high off current due to increased band-to-band or trap-assisted tunneling [6]. Moreover, the interface passivation for higher Ge content SiGe is extremely challenging resulting in significant sub-threshold leakage and degraded low field mobility. The direct consequence is the degraded short channel on-state current at the target off-current at a scaled VDD. It has been shown that by patterning of biaxially strained SiGe layers, strain can be transformed to asymmetric strain [7, 8] where the effective mass is significantly lowered and higher hole velocities can be achieved [5]. Therefore, the strain state in a scaled fin fabricated from biaxially strained substrates is pure uniaxial with optimal benefit for hole transport. The combination of uniaxial strain with great electrostatic integrity due to the non-planar device architecture as well as more manufacturing-friendly process, makes the moderate Ge content (such x=0.2-0.3) SiGe a very promising candidate for future generation of FinFETs. In order to evaluate the performance of s-SiGe FinFETs, SGOI substrates were fabricated using Ge condensation technique. This process is SOI CMOS compatible, where SiGe can be locally condensed in the pFET region while Si can be used for nFET or other on-chip applications. A final Ge fraction of x = 27.5% was measured by XRD, with minimal strain relaxation consistent with SIMS results (Figure 1(a)). The defectivity of SGOI substrates was measured using ex-situ Si capping followed by SECCO etch and dislocation density of ~ 1e4 cm-2 was measured for an optimized epitaxy and Ge condensation process. A gate first process flow was developed to fabricate our SiGe pMOS FinFETs [9]. As s-SiGe reactive-ion-etch resistance is much less than that of Si, the spacer RIE process was optimized to minimize fin recess in S/D regions and thus minimize stress relaxation. Raised S/D regions were formed using an ion-implant-free process by in-situ Boron-doped (ISBD) Si1-yGey (y > 40%) epitaxy with high Boron concentration, and dopant drive-in under the spacer to form the extensions. SGOI fins with vertical sidewalls and widths as scaled as 10nm demonstrated. Figure 1(b) shows typical XTEM of s-SiGe PMOS FinFET with sub-20nm physical gate length.Typical transfer and output characteristics of single-fin SiGe-channel PFETs (Fig. 2) exhibit excellent electrostatics with DIBL~50mV/V and SS ~90 mV/decade. In spite of high REXT ~ 0.4kΩ.μm, ION = 1.1 mA/µm was obtained at IOFF = 100 nA/µm and VDD = 1V. This high on current is attributed to the high source injection velocity exceeding 1e7 cm/s which is higher than SOI FinFETs with no stressors [10], and also higher than state-of the art bulk FinFETs [11]. Moreover, the SiGe PMOS FinFETs offers low off-state leakage suitable for high-performance and low-power applications. These criteria are hard to meet using state of the art Ge pFETs due to the significantly smaller bandgap [12]. In addition, unlike state of the art Ge pFETs, using a metal gate with a mid-gap work-function, target Vth has been achieved. In conclusion, we have demonstrated that s-SiGe channel FinFETs are a promising pFET candidate for future generations of high-performance devices and have a more manufacturable friendly process, than high-Ge content SiGe or Ge.REFERENCES[1] W. Haensch, IBM J. Res. & Dev., 2006. [2] S. Krishnan, IEDM 2011. [3] C. Ortolland, IEDM 2013. [4] A. Khakifirooz, IEEE TED 2009. [5] L. Gomez, IEEE TED, 2009. [6] C. Ni Chleirigh, IEEE TED, 2008. [7] T. Irisawa, IEDM 2005. [8] P. Hashemi, APL 2007. [9] P. Hashemi, VLSI 2013. [10] T. Yamashita, VLSI 2011. [11] C. Auth, VLSI 2012. [12] B. Duriez, IEDM 2013.

Dislocation Generation and Propagation across the Seed in Seed Cast-Si Ingots

We have studied the dislocation generation and propagation from the seed crystals during seed cast Si growth. The grown ingot was cut into a vertical wafer, followed by the dislocation imaging using X-ray topography and Secco etching. The dislocation behavior at the seed area was compared with the dislocation generation at the top surface due to the thermal stress during cooling. The dislocations at the seed/crystal interface have propagated on the {111} plane toward top. When the seed surface was not melted su ciently, the interface defect density became high, but no clear dislocation propagation was recognized. This suggests that the thermal shock at the seed/melt interface was not high enough to propagate dislocations to the growth direction. A certain amount of dislocations has been introduced from the top into the ingot according to the thermal stress. These observations suggest that optimizing the initial growth condition is important to dislocation control.

HCl defect revelation in 200 mm SiGe virtual substrates: A systematic study

Gaseous HCl was used, instead of Secco or Schimmel etching solutions, to reveal the threading dislocations in thick SiGe virtual substrates (VS). The latters, which consisted in linearly graded layers (~8–9% Ge/μm) capped with more than 1μm thick constant composition SiGe layers, were grown at high temperatures on Si(001). Advantages of this revelation technique were obvious: HCl selective etching of the defects was indeed performed on full wafers in the very same chamber used for epitaxy, not on cleaved pieces of wafers in dedicated wet benches which contain toxic chromium ions. Reproducibility was thus better. The etch temperature was reduced from 772°C down to 700°C as the Ge content increased from 20% up to 50%, in order to have the same HCl etch rates (~14nmmin.−1). An automated light inspection tool was used to acquire polar maps of the inverted pyramid etch pits after the removal of ~120nm, 230 and 340nm of SiGe. The etch pit size increased linearly with the HCl etched thickness and somewhat linearly with the Ge content (20%, 30%, 40% or 50%). The Etch Pits Density (EPD) increased from the center towards the edges of the SiGe VS (~1.6×105cm−2 up to 6cm away from it ⇔ 2.7×105cm−2 2.7×105 cm−2 9cm away from it). Very similar mean EPDs, in the 1.75–2.05×105cm−2 range, were otherwise obtained irrespectively of the Ge content and the etched thickness. The EPD in SiGe VS depends instead on the growth temperature, the growth rate and the grading used.

Grown-in microdefects and photovoltaic characteristics of heavily Ge co-doped Czochralski-grown p-type silicon crystals

The minority carrier lifetime (MCL)/flow pattern defect of B and Ge co-doped Czochralski silicon (CZ-Si) was increased/decreased with the initial Ge concentration up to 3 × 10 20 cm −3 and decreased/increased at higher Ge concentrations. Secco etch pit defects were increased in heavily (⩾3 × 10 20 cm −3 ) Ge co-doped CZ-Si (grown at low growth rate), which resulted in a low MCL. The influence of Ge on microdefect variation was relatively lower than the crystal growth rate in heavily Ge co-doped CZ-Si.

Effects of annealing temperature on crystallisation kinetics, film properties and cell performance of silicon thin-film solar cells on glass

Solid-phase crystallisation (SPC) of Si films on glass prepared by three deposition methods, plasma enhanced chemical vapour deposition (PECVD), electron-beam evaporation, and a combination of both, are compared for different annealing temperatures. Three independent techniques, optical transmission microscopy, UV reflectance spectroscopy, and X-ray diffraction, are used to characterise the crystallisation kinetics and film properties. The activation energy for the incubation is estimated to be 2.7–3.0eV. The scanning electron microscopy images of polycrystalline Si films after Secco etching show a gradually decreasing average grain size in each film type for higher SPC temperatures. The crystal quality of all film types degrades at higher crystallisation temperatures. Solar cells fabricated from these polycrystalline Si films were characterised by Suns-Voc and spectral response measurements. According to both the resulting open-circuit voltage and the short-circuit current, the electronic quality of all polycrystalline Si film types and the corresponding cell performance degrade for higher crystallisation temperatures but to a different extent depending on the film deposition method.

Impacts of Metal Impurities on Recombination Properties at Small Angle Grain Boundaries in Multicrystalline Silicon for Solar Cells

The correlation between recombination properties and detailed misorientation angles at small angle grain boundaries SA-GBs in multicrystalline silicon (mc-Si) after metal contamination were evaluated. After metal contamination, EBIC contrast enhancements at > 1.5o SA-GBs were on the order of Fe/1000 oC > Ni/1000 oC > Ni/600 oC, while at < 1.5o SA-GBs they were seldom different from any contamination. These results might be attributed to Fe and Ni atoms forming different energy levels in recombination centers and the getting abilities of SA-GBs depending on misorientation angles, i.e., dislocation density at SA-GBs. Many dark spots were observed after Ni/600 oC. After Secco etching, we confirmed that the dark spots corresponded to etch pits. Denuded zones at vicinity of SA-GBs were observed after only Fe/1000 oC. The gettering ability of SA-GBs depends on dislocation density and the difference in recombination properties after metal contamination was affected by the types of metal impurities.

Chemical etching to dissolve dislocation cores in multicrystalline silicon

Multicrystalline silicon wafers are used for approximately half of all solar cells produced at present. These wafers typically have dislocation densities of up to ∼106cm−2. Dislocations and associated impurities act as strong recombination centres for electron–hole pairs and are one of the major limiting factors in multicrystalline silicon substrate performance. In this work we have explored the possibility of using chemical methods to etch out the cores of dislocations from mc-Si wafers. We aim to maximise the aspect ratio of the depth of the etched structure to its diameter. We first investigate the Secco etch (1K2Cr2O7 (0.15M): 2HF (49%)) as a function of time and temperature. This etch removes material from dislocation cores much faster than grain boundaries or the bulk, and produces tubular holes at dislocations. Aspect ratios of up to ∼7:1 are achieved for ∼15μm deep tubes. The aspect ratio decreases with tube depth and for ∼40μm deep tubes is just ∼2:1, which is not suitable for use in bulk multicrystalline silicon photovoltaics. We have also investigated a range of etches based on weaker oxidising agents. An etch comprising 1I2 (0.01M): 2HF (49%) attacked dislocation cores, but its etching behaviour was extremely slow (<0.1μm/h) and the pits produced had a low aspect ratio (<2:1).

On the Impact of Heavy Doping on Grown-In Defects in Czochralski-Grown Silicon

The effects of heavy doping of Si on grown-in void size-density distributions and on Flow Pattern Defect (FPD) and Secco Etch Pit Defect (SEPD) density are discussed. Grown-in defects are studied using Scanning Infra Red Microscopy (SIRM) and Secco etching. Doping with 10^20 Ge atoms cm^-3 has a limited effect on the grown-in void size-density distribution but has a clear effect on the FPD density. The observed lower FPD density is most probably related to a decrease of the multiple void density. Co-doping with 10^20 B atoms cm^-3 leads to strong a suppression of the void density by nearly two orders of magnitude in agreement with the reported strong reduction of Crystal Originated Particle (COP) density in low resistivity p-type Si.

Decoration and preferential etching of crystal defects in silicon materials: influence of metal decoration on the defect etching process

AbstractDelineation of crystal defects in SOI wafers can be accomplished by preferential etching with solutions such as dilute Secco etch. By application of decoration procedures with metals such as copper or lithium delineation of defects by preferential etching can be improved due to acceleration of the etching process at the metal decorated defects. Parameters such as removal rate, selectivity and activation energy for the etching process are used to describe the influence of metal decoration on preferential etching of defects in SOI wafers. In this work the selectivity of a dilute Secco etch was determined experimentally on dislocations generated by damaging silicon substrates by indentation with a diamond tip and subsequent annealing at 1000 °C. After dilute Secco etching the depth of the dislocation etch pits was measured by an atomic force microscope. Both the selectivity and the activation energy were compared for non‐decorated and copper or lithium decorated samples of SOI wafers or silicon substrates. Typical values obtained for activation energies of non‐decorated samples were 29‐33 kJ/mol, those of decorated samples were in the range of 25‐34 kJ/mol. For the selectivity the values for non‐decorated samples were about 1.95 and increased with the level of copper decoration up to 3.0. (© 2011 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Approaches in Wet Chemical Etching for Defect Delineation in Silicon-on-Insulator Substrates

The organic oxidizing agents 1,4-benzoquinone and its nontoxic derivative 2,3,5,6-tetrachloro-1,4-benzoquinone have been shown to be alternatives to the toxic and carcinogenic hexavalent chromium which is routinely used in most etching solutions. The newly developed etching solutions delineate both grown-in and process-induced defects in silicon-on-insulator substrates fabricated by the Smart-Cut technology and show a good correlation to the defect densities obtained with a dilute Secco etching solution serving as a reference. In combination with an aqueous solution of the nontoxic fluorinating agent tetrafluoroboric acid, which has been introduced as an alternative to the very toxic solution of hydrofluoric acid (49%), a completely nontoxic etching solution is presented. An etching mechanism will be discussed, explaining the generation of elemental hydrogen which is formed during the etching process.

Delineation of Microdefects in Silicon Substrates by Chromium-Free Preferential Etching Solutions and Laser Scattering Tomography

Chromium-free preferential etching techniques in combination with light optical microscopy were compared with the non-destructive Laser Scattering Tomography (LST) for the evaluation of crystal defect densities in Czochralski substrates grown under different conditions. Dichromate containing etching solutions (original Secco etch and dilute Secco etch) were included into the study as reference. The chromium-free etching solutions with high etch rates comprised mixtures of nitric, hydrofluoric and acetic acid with water (JEITA 1, MEMC). Those with low etch rates consisted of mixtures of nitric and acetic or propanoic acid with hydrogen peroxide which form peracetic or perpropanoic acid (Organic Peracid Etches). OPE solutions provide improved discrimination of different types of defects and work also on highly doped substrates. As a general result, it turned out that the defect densities determined by the preferential etching solutions applied were significantly higher than those evaluated by LST. Relatively close to the LST defect densities are those determined by original Secco etch for larger etch pits.

Highly p-doped regions in silicon solar cells quantitatively analyzed by small angle beveling and micro-Raman spectroscopy

Highly p-doped regions in multicrystalline silicon solar cells, such as the back surface field region, are analyzed by means of small angle beveling and micro-Raman spectroscopy. Small angle beveling and subsequent Secco etching are used to enhance the lateral resolution of the micro-Raman spectroscopic measurements and to investigate the microstructure of the back surface field region in detail. The position-dependent analysis of the free carrier concentrations within the back surface field region is based on the Raman specific Fano resonances. The Raman spectroscopic measurement results are compared to results obtained from electrochemical capacitance-voltage measurements, which allows a subsequent calibration of the Raman data for the quantitative analysis of the free carrier concentrations within the highly p-doped regions of silicon solar cells and other devices. Our investigations show that the free carrier as well as the dopant concentration profiles within the back surface field region exhibit a nearly step-functional shape instead of the extended gradient shape which the electrochemical capacitance-voltage measurements suggest. Moreover, we show that the shape of the back surface field is often influenced by grain boundaries and other defects that occur in multicrystalline silicon wafers.

Copper Decoration and Etching for Delineation of Crystal Defects in Thick SOI

The standard method for the delineation of crystal defects in the thin silicon film of Silicon-On-Insulator (SOI) wafers is preferential etching with solutions like the dilute Secco etch. Copper decoration, prior to etching, improves defect delineation by magnifying even small defects. However, artefact formation may contribute to deceptively high defect densities. Results are presented of studies concerning the design and improvement of copper decoration of crystal defects using different preferential etching solutions. Defects with and without a halo were characterized. Differences in the defect densities were obtained after etching with varying etching solutions.

42.4: Characterization of Electrochemically‐Active Defects in Si‐Film Laser‐Crystallized with Directional SLS by Measuring the Stress Release during Secco Etching

AbstractIt has been verified that the crystal quality of directional SLS film achieves a position between those of ELC and CLC. The SLS film contains some electrochemically‐active in‐grain defects, which is hard to be passivated by hydrogen; this kind of defects are not observed in CLC nor ELC films.