Scriptscriptstyle ON Research Articles

Vertically Stacked Strained 3-GeSn-Nanosheet pGAAFETs on Si Using GeSn/Ge CVD Epitaxial Growth and the Optimum Selective Channel Release Process

Fully compressively strained GeSn quantum-well channels sandwiched by Ge sacrificial layers on 200-mm silicon-on-insulator (SOI) wafers are grown using chemical vapor deposition. The transmission electron microscopy images indicate that dislocations are confined near the relaxed Ge buffer/SOI interface, resulting in low defect densities in the stacked GeSn channels. The top Ge cap is essential to ensure that the top GeSn channel matches the other two channels during the Ge etching. Channel release is obtained by etching of the Ge sacrificial layers with optimum ultrasonic-assisted H2O2. The low thermal budget gate-stack (400 °C) and S/D parasitic resistance reduction are achieved. The first stacked 3-Ge0.93Sn0.07-channel p-gate-all-around FET with ${L} _{\text {CH}}= 60$ nm has a record high ${I}_{ \mathrm{\scriptscriptstyle ON}}=1975~\mu \text{A}/\mu \text{m}$ (per channel width) at ${V}_{\text {OV}}={V}_{\text {DS}}=-1$ V, among all GeSn pFETs. The junctionless device structure is used to simplify the process.

High-Voltage Gain Quasi-SEPIC DC–DC Converter

This paper proposes a modified coupled-inductor SEPIC dc–dc converter for high-voltage-gain $(2 applications. It utilizes the same components as the conventional SEPIC converter with an additional diode. The voltage stress on the switch is minimal, which helps the designer to select a low-voltage and low $R_{\mathrm {DS}-\mathrm{\scriptscriptstyle ON}}$ MOSFET, resulting in a reduction of cost, conduction, and turn ON losses of the switch. Compared to equivalent topologies with similar voltage-gain expression, the proposed topology uses lower component count to achieve the same or even higher voltage gain. This helps to design a very compact and lightweight converter with higher power density and reliability. Operating performance, steady-state analysis and mathematical derivations of the proposed dc–dc converter have been demonstrated in this paper. Moreover, extension of the circuit for higher gain $(G>10)$ application is also introduced and discussed. Finally, the main features of the proposed converter have been verified through simulation and experimental results of a 400-W laboratory prototype. The efficiency is almost flat over a wide range of load with the highest measured efficiency of 96.2%, and the full-load efficiency is 95.2% at a voltage gain of 10.

A Carrier Stored SOI LIGBT With Ultralow ON-State Voltage and High Current Capability

A novel carrier stored (CS) SOI lateral insulated gate bipolar transistor (LIGBT) with ultralow on-state voltage drop ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ) and high current capability is proposed and its electronic performance is investigated by simulation. The device features the CS layer and the trigate (TG) structure, named TGCS LIGBT. The CS effect in the on-state delivers an ultralow ${V}_{ \mathrm{\scriptscriptstyle ON}}$ . The TG is employed to increase the channel density and modulate the current distribution, further reducing the ${V}_{ \mathrm{\scriptscriptstyle ON}}$ and achieving high current capability. Moreover, TG assists in depleting the highly doped CS layer, which enhances the conductivity modulation and maintains high breakdown voltage. The extended P+ in the comb-shaped P+ region provides a low-resistance hole current path, and thus enhances the latch-up immunity. At the same turn-off loss, the TGCS LIGBT reduces the ${V}_{ \mathrm{\scriptscriptstyle ON}}$ by 32.5% and 36.4% compared with the tridimensional channel (TC) LIGBT and the conventional (Con). LIGBT, respectively. The TGCS LIGBT exhibits high current capability, which has an improvement of 151% and 26.8% compared with those of the Con. LIGBT and the TC LIGBT, respectively. The TGCS LIGBT shows a little better short-circuit capability than does the Con. LIGBT.

High Performance Al0.10Ga0.90N Channel HEMTs

This letter reports the large maximum drain current AlGaN channel high-electron-mobility transistors (HEMTs) of 849 mA/mm with graded buffers and constant channel layer. The large drain current and the transconductance benefit from the high electronic mobility of 807 cm2/ $\mathrm {V}\cdot \mathrm {s}$ and high saturated velocity. Furthermore, the device also shows a low off-state drain current of ~1 nA/mm and an ultrahigh ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ up to ~109. To the best of the authors’ knowledge, the electronic mobility, the maximum drain current, and ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ ratio all are the largest reported results ever achieved on the AlGaN channel HEMTs. These results not only drastically reduce the performance gaps between the AlGaN channel HEMT and the GaN channel HEMT in the maximum drain current, the maximum transconductance, and the electronic mobility, but also demonstrate better performances in the gate leakage current, the off-state drain current, ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ ratio, and the breakdown voltage.

Nitrogen-Doped ZnO Film Fabricated Via Rapid Low-Temperature Atomic Layer Deposition for High-Performance ZnON Transistors

High-performance nitrogen-doped ZnO (ZnON)-based thin-film transistors (TFTs) were fabricated by atomic layer deposition (ALD) with a rapid purging time of only 5 s at a temperature as low as 150 °C. It is the first time to report ALD ZnON TFT using NH3 as N source. It is found that ZnON TFT with a N: Zn atomic ratio of 1:19 (ZnON 1:19) exhibited excellent properties, such as lower subthreshold swing of 0.47 V/decade and smaller $\Delta {V}_{\textsf {th}}$ of 0.71 V under the temperature stress from 25 to 105 °C. The ${I}_{ \mathrm{\scriptscriptstyle ON}}$ and ${I}_{ \mathrm{\scriptscriptstyle OFF}} $ decreased as N-doping concentration increased, and ZnON 1:19 TFT presented a high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of 1.75 $\times \,\,10^{\textsf {7}}$ . The density of state was calculated by temperature stress. Combining with the X-ray photoelectron spectroscopy analysis, we built a model to explain the reaction mechanism that the moderate amount of N doping could significantly suppress the creation of oxygen defects.

A Snapback-Free Fast-Switching SOI LIGBT With an Embedded Self-Biased n-MOS

A 600-V snapback-free fast-switching silicon-on-insulator lateral insulated gate bipolar transistor with an embedded self-biased n-MOS (SBM) is proposed and investigated by simulations. The proposed device features an n-MOS which consists of the N+ anode, p-layer, N-buffer, and the anode trench gate (ATG) embedded between the P+ anode and N+ anode. It is worth noting that the ATG is driven by the anode, without any additional control circuits. At the initial conduction stage, p-layer/N-buffer junction acting as electron barrier contributes to snapback-free with a reduced cell pitch. Simultaneously it provides an extra built-in path to extract electrons at the turn-OFF stage, which hence reduces the turn-OFF energy loss ( ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ ) and increases the switching speed. Furthermore, the hole leakage current of the SBM LIGBT in the blocking state is suppressed due to the electron accumulation/inversion formed along the sidewall of the ATG, avoiding triggering the P+NP transistor and thus increases the breakdown voltage by 11% in comparison with that of the conventional LIGBT. Simulation results show that the SBM LIGBT reduces ${E} _{ \mathrm{\scriptscriptstyle OFF}}$ by 31% and 43% compared to the conventional LIGBT with the same on-state voltage drop ( ${V} _{ \mathrm{\scriptscriptstyle ON}}$ ), at the load current of 100 and 200 A/cm2, respectively.

Numerical Simulation Study of a Low Breakdown Voltage 4H-SiC MOSFET for Photovoltaic Module-Level Applications

Silicon carbide (SiC) power MOSFETs are available only for high-power and medium-to-high-voltage applications, generally above 600 V, because for lower blocking voltages, they comparatively provide lower advantages in terms of efficiency. There are applications, however, for which ruggedness and reliability are as important as efficiency, such as power optimizers for photovoltaic (PV) modules, which fall within the low power, low voltage category of dc–dc converters. These circuits, which maximize the energy produced by each single PV module, operate in continuously changing and stressing conditions yet having to assure high performances in terms of efficiency as well as of temperature insensitivity and long-term reliability. The aim of this paper is to predict the basic characteristics of a 4H-SiC MOSFET tailored for this kind of applications and, therefore, characterized by a breakdown voltage BVDS of 150 V and currents of the order of 10 A. The study, based on numerical simulations, shows that, besides the expected higher ruggedness, the static characteristics would be comparable to those of silicon MOSFETs rated for a comparable BVDS, with $R_{\mathrm{\scriptscriptstyle ON}}$ in the order of 100 $\text{k}\Omega {\cdot} \mu \text{m}^{2}$ , while advantages would result in terms of dynamic characteristics, and in particular in terms of switching times.

N-Polar GaN HEMTs Exhibiting Record Breakdown Voltage Over 2000 V and Low Dynamic On-Resistance

Nitrogen polar (N-Polar) GaN high-electron-mobility transistors (HEMT) targeting high-voltage switching applications were fabricated on epi-layers grown by metal-organic chemical vapor deposition on sapphire substrates. Devices demonstrated a combination of high breakdown voltage and low dynamic ON-resistance. Breakdown voltages of over 2000 V were observed on transistors with ${L}_{G}=\text {1}\,\,\mu \text{m}$ , ${L}_{{\text {GS}}}=1\,\,\mu \text{m}$ , and ${L}_{{\text {GD}}}=28\,\,\mu \text{m}$ . These devices had a drain current density of ~ 575 mA/mm at ${V}_{{\text {GS}}}=1$ V, and the specific ON-resistance (active-area) was $ {4}~\text {m}\Omega \cdot \text {cm}^{2}~(10~\Omega \cdot \text {mm}$ ). Dynamic ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) was characterized $\text {5}~\mu \text{s}$ after the device was turned ON, with up to 575-V OFF-state stress. At ${V}_{{\text {DS}}, {Q}} = \text {575}$ V, the dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ was ~1.4 times the static ${R}_{ \mathrm{\scriptscriptstyle ON}}$ (40% increase). These transistors showed an ultra-low dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of ~5% when measured at 450-V stress. As one of the first demonstrations of N-Polar GaN HEMTs for power switching applications, the devices discussed in this letter achieve excellent ${V}_{ \mathrm{\scriptscriptstyle BR}}$ and dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ performance comparable to (and in most cases better than) the state-of-the-art Ga-Polar GaN HEMTs reported in the literature.

1100 V AlGaN/GaN MOSHEMTs With Integrated Tri-Anode Freewheeling Diodes

In this letter, we present high-performance reverse-conductionGaN-on-Si metal–oxide–semiconductor high-electron-mobility transistors (RC-MOSHEMTs) with integrated tri-anode freewheeling diodes. Tri-anode Schottky barrier diode presenting small turn- ON voltage ( ${V}_{ \mathrm{\scriptscriptstyle ON}}$ ), ultra-low reverse leakage current, and high breakdown voltage ( ${V}_{\textsf {BR}^{2}}$ ) was incorporated at portions of the drift region of AlGaN/GaN MOSHEMTs as freewheeling diodes. The tri-anode RC-MOSHEMTs exhibited outstanding reverse-conduction performance with a small ${V}_{ \mathrm{\scriptscriptstyle ON}}$ of 0.55 V, along with a high ${V}_{\textsf {BR}}$ of 1150 V, state-of-the-art low ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) of $8.83~\Omega \cdot \textsf {mm}$ , and high-power figure-of-merit ( $\textsf {FOM} = {V}_{\textsf {BR}^{\textsf {2}}}/{R}_{ \textsf{ON,SP}}$ ) of 1.32 GW/cm2. These results reveal the potential of the tri-gate/tri-anode technology for future integrated power electronic devices.

High-Performance Normally-OFF GaN MIS-HEMTs Using Hybrid Ferroelectric Charge Trap Gate Stack (FEG-HEMT) for Power Device Applications

A GaN metal-insulator-semiconductor-high electron mobility transistor (HEMT) using hybrid ferroelectric charge trap gate stack (FEG-HEMT) is demonstrated for normally-OFF operation. The ferroelectric (FE) polarization increases the number of trapped charges in the HfON charge trapping layer, leading to high positive threshold voltage (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> ) shift for the normally-OFF device. Besides, under the positive bias temperature instability (PBTI) test, the internal electric field induced by FE polarization causes smoother slope of the conduction band in FE gate stack, resulting in better V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> stability. With the proposed hybrid FE charge trap gate stack, the device exhibits a high V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> of +2.71 V at I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Dh</sub> = 1μA/mm, a high maximum current density of 820 mA/mm and low on-resistance (R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> ) of 11.1 Ω · mm. The FE device also shows good V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">th</sub> -temperature stability compared to the non-FE device results. Besides, a high current device with 40 A is also fabricated in this letter to demonstrate the feasibility of the proposed FEG-HEMT device for high power device application.

Impact of Gaussian Doping Profile and Negative Capacitance Effect on Double-Gate Junctionless Transistors (DGJLTs)

In this paper, we study the impact of vertical Gaussian doping (GD) profile and ferroelectric (FE) negative capacitance phenomenon on the performance of nanoscale double-gate junctionless (JL) transistor. The device characteristics have been obtained by using the baseline approach of combining Landau–Khalatnikov equation with TCAD simulations. Doped HfO2 has been incorporated as FE gate insulator and parameters such as coercive field ( ${E}_{c}$ ) and remanent polarization ( ${P}_{r}$ ) have been optimized to achieve nonhysteretic voltage amplification along with substantial gain. The impact of GD profile in the channel and FE gate insulator is examined by studying device characteristics for a wide range of projected range ( ${R}_{p}$ ), straggle ( $\sigma$ ), and peak doping ( ${N}_{\mathbf {pk}}$ ) values for optimized ${E}_{c}$ and ${P}_{r}$ . It has been demonstrated that the proposed device exhibits reduced leakage current, increase in ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio by 4 orders, and approximately 2 times improvement in ${g}_{m}/{I}_{d}$ values compared to the conventional double-gate GD JL transistor. Furthermore, the proposed device exhibits reverse drain induced barrier lowering effect which leads to increase in barrier even in nanoscale regime.

Low-Dispersion, High-Voltage, Low-Leakage GaN HEMTs on Native GaN Substrates

In this paper, the advantages of GaN high electron mobility transistors (HEMTs) grown on native GaN over GaN/Si or GaN/sapphire substrates are investigated and correlated with epitaxial material quality. Transmission electron microscopy plan-view and cross-sectional analyses of GaN/GaN reveal dislocation densities below ${1} \times {10}^{{6}}$ cm−2, which is at least three orders of magnitude lower than that of GaN/Si or GaN/sapphire. In the case of GaN/Si, the dislocations not only originate from the substrate/nucleation layer interface, but also the strain relief and isolation buffer stacks are main contributors to the dislocation density. GaN/GaN HEMTs show superior electrical and thermal performance and feature three orders of magnitude lower OFF-state leakage. The current collapse (also referred to as current dispersion or $R_{ \mathrm{\scriptscriptstyle ON}}$ -increase) after stress bias is less than 15% compared with 50% in the case of GaN/Si. A 2% drop of the ON-state current due to self-heating in dc operation when compared with 13% and 16% for GaN/Si and GaN/sapphire, respectively. The GaN/Si thermal performance becomes comparable to that of GaN/GaN only after substrate removal. Therefore, GaN/GaN provides high ON-state current, low OFF-state leakage current, minimal current collapse, and enhanced thermal power dissipation capability at the same time, which can directly be correlated with the absence of high dislocation density.

Planar Junctionless Silicon-on-Insulator Transistor With Buried Metal Layer

In this letter, we propose a novel structure of an n-channel silicon-on-insulator junctionless transistor (SOI-JLT) with improved ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio and scalability. A buried metal layer (BML) of appropriate workfunction ( $\phi _{\text {BM}}$ ) is used to create a Schottky junction at the bottom of Si device layer, whereas the source–channel–drain path is junctionless and hence named the buried-metal-SOI-lateral JLT (BM-SOI-LJLT). The BML-induced bottom depletion layer combined with the depletion region due to top gate results in a perfect volume depletion in OFF state. A 2-D calibrated simulation has shown an ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ ratio of ~108 in BM-SOI-LJLT compared to ~2 in the conventional SOI-JLT at $\phi _{\text {BM}}$ of 5.1 eV and a gate length of 20 nm. Furthermore, the lateral band-to-band tunneling parasitic leakage is significantly lower in the BM-SOI-LJLT and does not degrade its ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{ \mathrm{\scriptscriptstyle OFF}}$ ratio. Furthermore, high vertical field due to the Schottky junction minimizes the lateral coupling between the source and drain field lines and thus improves the short-channel-effect suppression and scalability of the proposed device.

Electron Trapping in Extended Defects in Microwave AlGaN/GaN HEMTs With Carbon-Doped Buffers

This paper investigates AlGaN/GaN high-electron mobility transistors (HEMTs) fabricated on epistructures with carbon (C)-doped buffers. Metalorganic chemical vapor deposition is used to grow two C-doped structures with different doping profiles, using growth parameters to change the C incorporation. The C concentration is low enough to result in n-type GaN. Reference devices are also fabricated on a structure using iron (Fe) as dopant, to exclude any process related variations and provide a relevant benchmark. All devices exhibit similar dc performance. However, pulsed ${I}$ – ${V}$ measurements show extensive dispersion in the C-doped devices, with values of dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}~3$ –4 times larger than in the dc case. Due to the extensive trapping, the devices with C-doped buffers can only supply about half the output power of the Fe-doped sample, 2.5 W/mm compared to 4.8 W/mm at 10 GHz. In drain current transient measurements, the trap filling time is varied, finding large prevalence of trapping at dislocations for the C-doped samples. Clusters of C around the dislocations are suggested to be the main cause for the increased dispersion.

Metal-CH3NH3PbI3-Metal Tunnel FET

A novel-gated structure of aluminum (Al)—perovskite (CH3NH3PbI3)—indium tin oxide (ITO), with Al as source and ITO as drain terminals, has been reported. Ambipolar nature of CH3NH3PbI3 has been explored for the device channel. Two Schottky junctions are present at source–channel and channel–drain junctions with barriers of 0.4 and 0.6 eV, respectively. Both, n- and p-type FET-like characteristics have been observed, when the device was biased, accordingly. The triangular tunneling has been observed in the output and transfer characteristics. The device shows a higher current on-off ratio ( ${I}_{ \mathrm{\scriptscriptstyle ON}}/_{ \mathrm{\scriptscriptstyle OFF}})$ of 106 with a steeper and improved sub-threshold swing (SS) of 20 ± 2 mV/decade for P tunnel field-effect transistor (TFET). However, for N TFET, ${I}_{ \mathrm{\scriptscriptstyle ON}}/_{ \mathrm{\scriptscriptstyle OFF}}$ of 104 with SS of 30 ± 2 mV/decade has been obtained.

High-Performance Amorphous Indium Gallium Zinc Oxide Thin-Film Transistors Fabricated by Atomic Layer Deposition

This letter reports the fabrication of high-performance amorphous indium gallium zinc oxide (a-IGZO) thin-film transistors (TFTs) via atomic layer deposition at a substrate temperature of 250 °C. The film thickness of In2O3, Ga2O3, and ZnO varied linearly with the number of deposition cycles. The cation composition of the IGZO film was controlled by an alternate stacking of In2O3, Ga2O3, and ZnO atomic layers. The fabricated a-IGZO TFTs exhibited a high electron mobility of 22.1 cm2/Vs, threshold voltage of 2.41 V, subthreshold gate swing of 0.30 V/decade, and an ${I}_{{ \mathrm{\scriptscriptstyle ON}}/{ \mathrm{\scriptscriptstyle OFF}}}$ ratio of $> \textsf {1} \times \textsf {10}^{\textsf {8}}$ .

Complete Solution-Processed Low-Voltage Hybrid CdS Thin-Film Transistors With Polyvinyl Phenol as a Gate Dielectric

In this letter, we fabricated cadmium sulfide (CdS)-based hybrid thin-film transistors (TFTs) using Poly(vinylphenol) (PVP) as the polymer dielectric gate. The synthesis of PVP crosslinked with trimethoxy propyl silane was made by solution processing, and the films were deposited by a dip-coating technique. The PVP films were cured at 200 °C after deposition, which was the highest temperature for the devices processing. The CdS films were deposited at room temperature using a UV photo-assisted chemical bath deposition technique. These dielectric layers have low leakage current density (10−8 A/cm2) and a high dielectric constant of 4.7 at 1 kHz. The TFTs exhibited superior performance with a low threshold voltage of 0.3 V, ${I}_{ \mathrm{\scriptscriptstyle ON}/ \mathrm{\scriptscriptstyle OFF}}$ current ratio of 105, subthreshold slope 0.25 V/dec, and a high mobility 36.1 cm $^{\textsf {2}}\text{V}^{-\textsf {1}}\text{s}^{-\textsf {1}}$ at operating voltages less than 3 V.

Stacked Sidewall-Damascene Double-Layer Poly-Si Trigate FETs With RTA-Improved Crystallinity

In this letter, stacked sidewall-damascene double-layer poly-silicon trigate field effect transistors (FETs) with and without rapid thermal annealing (RTA) are successfully demonstrated using a simple fabrication method. Devices with RTA exhibit superior electrical characteristics to those without RTA owing to better crystallinity. The better crystallinity of the device with RTA results from a larger grain size and fewer defects, leading to higher field-effect mobility $\mu _{\text {FE}}$ compared with devices without RTA. p-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA show excellent electrical characteristics, including an extremely low drain-induced barrier lowering (DIBL) of 7 mV/V, a steep subthreshold swing of 136 mV/decade, and high $\text{I}_{ \mathrm{\scriptscriptstyle ON}}/\text {I}_{ \mathrm{\scriptscriptstyle OFF}}$ current ratio of ${1.1}\times {10}^{7}$ . The fabricated n-type stacked sidewall-damascene double-layer poly-Si trigate FETs with RTA showed a low DIBL, subthreshold swing and an $\text{I}_{ \mathrm{\scriptscriptstyle ON}}/\text{I}_{ \mathrm{\scriptscriptstyle OFF}}$ current ratio larger than seven orders of magnitude. Their simple fabrication method makes them a promising candidate for future monolithic 3D integrated-circuit applications.

Studies on Fabrication and Reliability of GaN High-Resistivity-Cap-Layer HEMT

In this paper, we systematically investigate the effect of hydrogen plasma treatment radio frequency (RF) power, treatment time, and rapid thermal annealing (RTA) on the performance of high-resistivity-cap-layer high-electron-mobility-transistor (HRCL-HEMT). It is found that high RF power contributes to obtain high drain current, but induces more damage. An appropriate RTA process not only can repair the plasma damage but also improves the static characteristics of HRCL-HEMT. Subsequently, a large hydrogen plasma treatment time window of 4 min is demonstrated with an optimized RF power of 2 W and RTA at 350 °C for 5 min. Furthermore, the thermal stability of the optimized HRCL-HEMT is investigated by high temperature test and long-term thermal stress test. No obvious degradation of ${V}_{\text {TH}}$ , ${I}_{G}$ , ${R}_{\text {SH}}$ , and dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ is observed in both before and after passivation devices after 1000-h thermal stress. Finally, gate reliability of the HRCL-HEMT is also analyzed by time-to-failure test. The maximum gate voltage is determined to be 6.28 V for a ten-year lifetime with a failure rate of 1% at 25 °C.

High ${f}_{{T}}$ AlGa(In)N/GaN HEMTs Grown on Si With a Low Gate Leakage and a High ON/OFF Current Ratio

A 55-nm T-gate high-electron-mobility transistor was fabricated with a quaternary barrier AlGa(In)N/AlN/GaN heterostructure grown on a highly resistive Si substrate. The device shows a maximum current density of 1.25 A/mm, a peak extrinsic dc transconductance of 420 mS/mm, and the cutoff frequencies ${f}_{T}/{f}_{\text {max}}$ of 145/220 GHz, which gives a record high value of ( ${f}_{T}\cdot {f}_{\text {max}}{)}^{1/2} = 178$ GHz among the reported GaN-on-Si ratio frequency devices. The Al-rich quaternary barrier featured an incorporation of little indium, which yet significantly improved the crystalline quality, resulting in a record low gate leakage below 10−5 A/mm and a high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of $1.78\times 10^{5}$ .