Scriptscriptstyle ON Research Articles

SiC Trench MOSFET With Integrated Self-Assembled Three-Level Protection Schottky Barrier Diode

A silicon carbide (SiC) trench MOSFET (TMOS) with integrated three-level protection (TLP) Schottky barrier diode (SBD), named ITS-TMOS, is proposed and investigated by simulation. The device features the integrated TLP-SBD that remarkably improves body diode characteristics while guarantees excellent fundamental performance of TMOS. In the blocking state, the P-base region, the trench gate, and the P+ shield at the trench bottom serve as the TLP of the Schottky contact. Each protection assists in depleting the drift region beneath Schottky contact. Benefiting from the self-assembled TLP, the leakage current of the integrated body diode of the ITS-TMOS is significantly reduced. Moreover, the reverse turn-on voltage ( ${V} _{ \mathrm{\scriptscriptstyle ON}}$ ) and the gate charge ( ${Q} _{g}$ ) of the ITS-TMOS are 65% and 18% lower than those of the conventional TMOS, respectively. The improved overall performances make the SiC ITS-TMOS a competitive candidate for high-efficiency and high power density applications.

A U-Gate InGaAs/GaAsSb Heterojunction TFET of Tunneling Normal to the Gate With Separate Control Over ON- and OFF-State Current

A U-gate vertical tunneling field-effect transistor (TFET) of band-to-band tunneling (BTBT) normal to the gate at low operation voltages is proposed and investigated by TCAD simulation. In this structure, drive current and OFF-state leakage current can be separately controlled by the insertion of a spacer layer between the channel and drain layers. The dominant mechanisms for drive current and OFF-state leakage are BTBT and source-to-drain tunneling (SDT), respectively. A modified structure of side gates and a hetero-spacer enables high-performance InGaAs/GaAsSb heterojunction TFETs with low OFF-state leakage. Drive current as high as 520 $\mu \text{A}/\mu \text{m}$ with an $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of 107 at an overdrive voltage of 0.3 V was achieved in an InGaAs/GaAsSb heterojunction TFET of a small effective bandgap (0.02 eV). Furthermore, this U-gate TFET structure is fully compatible to VLSI technology without any complicated fabrication steps.

Demonstration of a Novel Two Source Region Tunnel FET

A novel silicon-on-insulator (SOI)-based tunnel FET (TFET) with two source regions (TSRs) is proposed and investigated by Sentaurus simulation. The incorporation of the TSR in the SOI platform augmented the effective tunneling area between source–channel junctions and hence boosts the drive current of the device. To restrain the leakage current at a lower value, we have introduced an isolator oxide which avoids the direct coupling of the source and the drain. The typical figure of merit of any device is its ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio, which is $\sim {9} \times {10}^{ {10}}$ of our proposed structure. The impact of various device geometry variations has been studied and optimized accordingly through extensive simulation. We have also benchmarked our proposed TSR-TFET results with the modified L-shaped TFET, line tunneling-based TFET, and point tunneling-based TFET and procured better results over all the reference devices.

Metal Grain Granularity Study on a Gate-All-Around Nanowire FET

The impact of the metal grain granularity (MGG) variations on subthreshold and ON-current of a 22-nm gate length Si gate-all-around (GAA) nanowire (NW) field-effect transistor (FET) is analyzed by assessing five figures-of-merit: threshold voltage ( ${V}_{T}$ ), OFF-current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ), subthreshold slope (SS) and drain-induced-barrier-lowering at low ( ${V}_{D}={50}$ mV) and high ( ${V}_{D}={1.0}$ V) drain biases, and ON-current variability at the high drain bias. We assume a TiN metal gate with four grain sizes (GS): 10, 7, 5, and 3 nm. The simulations carried out employ: 1) a 3-D finite element (FE) drift-diffusion (DD) simulator with density-gradient (DG) quantum corrections (QC) in the subthreshold region and 2) a 3-D FE Monte Carlo (MC) simulation toolbox with Schrodinger equation QC for the ON-current. We have found that the ${\sigma }{V}_{T}$ due to the MGG variability is 10% higher in the GAA-NW FET (GS of 10 nm) than in a 20-nm gate FinFET. For a GS of 3 nm, the variability becomes comparable between the GAA-NW FET and the FinFET. Comparison against the line-edge-roughness (LER) variability shows that the MGG (GS of 10 nm) affects ${\sigma }{V}_{T}~92$ % more than the LER (root-mean-square height of 0.85nm and correlation length of 20 nm). Finally, the ON-current of the FinFET (GS of 10 nm, ${V}_{D}=\textsf {0.9}$ V) has a 43% higher ${\sigma }{I}_{ \mathrm{\scriptscriptstyle ON}}$ than that of the GAA-NW (GS of 10 nm, ${V}_{D}=\textsf {1.0}$ V) making the GAA-NW FETs a much better solution for sub-10-nm technology nodes.

900 V Reverse-Blocking GaN-on-Si MOSHEMTs With a Hybrid Tri-Anode Schottky Drain

In this letter, we present high-performance GaN-on-Si metal-oxide-semiconductor high electron mobility transistors with record reverse-blocking (RB) capability. By replacing the conventional ohmic drain with a hybrid tri-anode Schottky drain, a high reverse breakdown voltage ( ${V}_{\text {B}}^{\text {R}}$ ) of −900 V was achieved (at $1~\mu \text{A}$ /mm with grounded substrate), along with a small reverse leakage current ( ${I}_{\text {R}}$ ) of ~20 nA/mm at −750 V. The devices also presented a small turn- on voltage ( ${V}_{{ \mathrm{\scriptscriptstyle ON}}}$ ) of 0.58 ± 0.02 V, a small increase in forward voltage ( $\Delta {V}_{\text {F}}$ ) of ~0.8 V, a high ON/OFF ratio over 1010, and a high forward breakdown voltage ( ${V}_{{{\text {B}}}}^{{{\text {F}}}}$ ) of 800 V at 20 nA/mm with grounded substrate. These results demonstrate a new milestone for RB GaN transistors, and open enormous opportunities for integrated GaN power devices.

Impact of Substrate Bias Polarity on Buffer-Related Current Collapse in AlGaN/GaN-on-Si Power Devices

Bulk traps in the high-resistivity buffer stack underneath the 2-dimensional electron gas (2DEG), which can interact with the high vertical electric field at OFF state, impose a critical challenge to the dynamic ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}})$ of AlGaN/GaN-on-Si power devices. In this paper, the impact of substrate bias polarity on carrier injection/transport and buffer-induced current collapse has been investigated by using ramped and transient back-gating characterizations as well as TCAD simulations. High voltage applied to the conductive Si substrate can modulate 2DEG conductivity through the back-gate effect, whereby the dynamics of both acceptor and donor buffer traps are identified. Distinct buffer trapping and asymmetric vertical leakage under opposite top-to-substrate bias polarities have been observed, which are attributed to the fundamentally different carrier injection/transport mechanisms. It is suggested that the energy barrier at the nucleation-layer/Si interface can limit the electron injection from Si substrate into the buffer stack and consequently influence the buffer-related current collapse.

Design and Investigation of Dielectric Engineered Dopant Segregated Schottky Barrier MOSFET With NiSi Source/Drain

In this paper, to solve an important issue of low ON-state current in the nickel silicide (NiSi) metal source/drain Schottky barrier (SB) MOSFET (SBMOS), we have reported a novel dielectric engineered (DE) dopant segregated (DS) SBMOS structure using gate dielectric engineering. In a proposed device, we employ two different gate dielectric materials. The high-k gate dielectric is used at the source side and low-k gate dielectric at the drain side. Beneath the high-k gate dielectric, electron accumulation increases due to large gate dielectric capacitance density. As a result, reduction in depletion of source side dopant segregation layer further decreases the SB tunneling width for the electron injection. Consequently, improvement in ON-state current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) is obtained. In addition, the low-k gate dielectric and drain side dopant segregation layer increases the effective SB height and tunneling width for the hole injection. Thus, the OFF-state current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) is suppressed. The optimization of proposed device has been performed by modulating the length of high-k and the low-k gate dielectric. In addition, we have compared the performance of the proposed device in terms of ON to OFF current ratio $({I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}})$ , subthreshold swing (SS), transconductance $({g}_{ {m}})$ , transconductance generation factor $({g}_{ {m}}/{I}_{ {D}})$ , cut-off frequency $({f}_{ {T}})$ , and gain-bandwidth product $({f}_{ {A}})$ to the SBMOS, DS SBMOS, and DS SBMOS with the full high-k gate dielectric. Moreover, we have proposed the possible process flow for the DE DS SBMOS fabrication.

A Novel PNPN-Like Z-Shaped Tunnel Field- Effect Transistor With Improved Ambipolar Behavior and RF Performance

To suppress the ambipolar behavior and improve RF performance in tunnel field-effect transistors (TFETs), a Z-shaped (ZS)-TFET is proposed. The proposed ZS-TFET is more scalable than other vertical band-to-band-based TFETs and provides higher ON-state current ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}$ ), larger ON/OFF current ratio ( ${I} _{ {\mathrm{\scriptscriptstyle ON}}}/{I} _{ {\mathrm{\scriptscriptstyle OFF}}}$ ) and lower subthreshold swing compared to conventional TFETs. These advantages stem from the tunneling junction in the ZS-TFET being perpendicular to the channel direction, which facilitates the formation of a relatively large tunneling junction area. The ZS body makes use of both vertical and horizontal fields while suppressing the lateral parasitic tunneling current. In addition, by using a ZS gate in the proposed device, the energy band diagram near the source is modulated to create an N+ source pocket which creates a downward band bending of the potential, similar to PNPN-like structures. Finally, the proposed structure significantly improves the analog/RF figure-of-merit.

4H-SiC Trench MOSFET With Floating/Grounded Junction Barrier-controlled Gate Structure

A novel silicon carbide (SiC) trench MOSFET with floating/grounded junction barrier-controlled gate structure (FJB-MOS/GJB-MOS) is presented and investigated utilizing Sentaurus TCAD simulations. The split P+ region introduced beneath the trench could better shield the gate oxide from the high electric field in the blocking mode, leading to an enhancement in the breakdown voltage while without significant degradation of other characteristics. As a result, the FJB-MOS with floating P+ shielding exhibits a higher figure of merit related to the breakdown voltage and the specific on-resistance ( ${V}_{\textsf {BR}}^{{\,\textsf {2}}}/{R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ ), which is improved by 15% and 49%, respectively, with comparison to those of the state-of-the-art double-trench MOSFET and L-shaped gate trench MOSFET. In terms of the GJB-MOS with grounded P+ shielding, it shows great advantage in reducing the switching losses thanks to the lower specific gate–drain charge ${Q}_{{\:\textsf {gd,sp}}}$ and is more conductive to high frequency applications. Additionally, the formation of the P+ region is aided by the Sentaurus Process and the processing implementation of the proposed structure is discussed.

Polarity Control of GaN and Realization of GaN Schottky Barrier Diode Based on Lateral Polarity Structure

This paper reports investigation on a polarity control scheme of GaN thin films and realization of Schottky barrier diode (SBD) fabricated on a lateral-polarity-structure (LPS) GaN without intentionally doping. Specifically, Ga-polar and N-polar GaN were grown simultaneously side by side on sapphire substrate with patterned AlN buffer. Due to the surface energy difference between two polarities, N-polar regions are n-type conductive with rough surface morphology, while Ga-polar regions are semi-insulating with atomic flat surface morphology. Annealing conditions of both ohmic contact and Schottky contact were investigated. Current–voltage (I–V) characteristic revealed that the SBD fabricated on LPS GaN has higher forward current, barrier height closer to 0.7 eV, and ideality factor closer to unity compared to SBD fabricated on conventional undoped GaN. The specific on-state resistance ( ${R}_{{ \mathrm{\scriptscriptstyle ON}}})$ for the SBD based on LPS GaN is 77 $\text{m}\Omega \cdot \text {cm}^{{{{2}}}}$ lower than the SBD fabricated on conventional GaN. With oxide passivation on SBD surface, forward current exceeds 0.2 A at 10 V, while reverse current is less than 10−5 A at −10 V, respectively. The utilization of LPS in SBD demonstrates a promising approach for the development of lateral n+/n− SBD with a simple fabrication scheme.

Performance Improvement of p-Channel Tin Monoxide Transistors With a Solution-Processed Zirconium Oxide Gate Dielectric

This letter reports the fabrication of p-channel tin monoxide (SnO) thin-film transistors (TFTs) with a high-permittivity zirconium oxide (ZrO2) gate insulator film, which were prepared by a low-cost spin-cast method. The spin-cast ZrO2 dielectrics exhibit a low leakage current density of $4.5 \times 10^{{\textsf {-8}}}$ A/cm2 at 1 MV/cm. Introducing the ZrO2 dielectric in top-type SnO TFTs allows for a reduction in the driving gate voltage range from 80 to 10 V, as compared with devices with a thermal SiO2 gate insulator. Additionally, a high field-effect mobility of 2.5 cm2/Vs and an $I_{{ \mathrm{\scriptscriptstyle ON} / \mathrm{\scriptscriptstyle OFF}}}$ of $3 \times 10^{{\textsf {3}}}$ were preserved.

RF Performance of <italic>In Situ</italic> SiN<italic>x</italic>Gate Dielectric AlGaN/GaN MISHEMT on 6-in Silicon-on-Insulator Substrate

A high power-added efficiency and low dynamic on-resistance ( $R_{ \mathrm{\scriptscriptstyle ON}})$ AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistor (MISHEMT) with in situ SiN x insulator design was demonstrated on 150-mm silicon-on-insulator (SOI) substrate. Compared to traditional high-resistivity Si substrate, SiN x /AlGaN/GaN MISHEMT grown on the SOI 5- $\mu \text{m}$ -thick Si active layer performed better tensile stress relaxation and surface flatness. Based on Hall measurement results, electron mobility and the sheet charge density on SOI substrate were improved simultaneously owing to a lower-defect density which is also proofed by pulse measurement and low-frequency noise measurement. Due to the low-feedback substrate capacitance, the bandwidth, and the linearity were also improved simultaneously by SOI substrate design.

Ultra-Wideband Low-Loss Switch Design in High-Resistivity Trap-Rich SOI With Enhanced Channel Mobility

In this paper, the stress memorization technique (SMT) effects upon ultra-wideband RF switch performance are investigated for the first time. Low insertion loss (IL), high isolation, ultra-wideband (dc to 50 GHz) single-pole double-throw (SPDT), and single-pole four-throw (SP4T) switches designed with commercial 0.13- $\mu \text{m}$ high-resistivity (HR) trap-rich SOI technology with/without SMT are presented and investigated. 2.5 V nMOS transistor ( $L_{g} = 0.2~\mu \text{m}$ ) with low $R_{\mathrm{\scriptscriptstyle ON}} {^\ast} C_{\mathrm{\scriptscriptstyle OFF}}$ from GF 130RFSOI PDK is used. It is found that channel mobility of switch transistor is improved by SMT and thus switch performance can be further improved. Moreover, the impact of transistor channel length, which has dominant effects on both IL and isolation of the switches, under different gate bias on switch performance are also studied and verified experimentally. Low measured IL of less than 2.1 dB and good isolation of better than 27 dB from dc to 50 GHz are obtained for the SPDT switch. For SP4T switch, the measured IL of less than 2.6 dB and isolation of better than 27 dB are achieved from dc to 35 GHz. The active chip areas of designed SPDT and SP4T switches are compact with size of only $0.214 \times 0.19~\text {mm}^{2}$ and $0.36 \times 0.19~ \text {mm}^{2}$ , respectively.

Improvement of Subthreshold Characteristic of Gate-Recessed AlGaN/GaN Transistors by Using Dual-Gate Structure

The subthreshold characteristic of gate-recessed high-electron-mobility transistors (HEMTs) using dual-gate (DG) architectures is systematically studied. The recessed DG structure can effectively shift the threshold voltage ( ${V}_{\text {th}}$ ) in the positive direction. Different from the complex function expression between ${V}_{\text {th}}$ and AlGaN thickness ( $\text{t}_{b}$ ) in the recessed single-gate (SG) device, the variation of $\text{V}_{\text {th}}$ with ${t}_{b}$ is monotonic in the recessed DG devices. Recessed DG device exhibits a low off-state leakage current of $\sim {3}\times {10}^{{-10}}$ A/mm and gate induced drain leakage is effectively improved. A higher $I_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ range of recessed DG devices broadens about 2 times and provide a wider range of ${t}_{b}$ than that of recessed SG devices. The DG structure has a stronger modulation effect on drain–source resistance ( ${R}_{\text {ds}}$ ) and gate–drain resistance ( ${R}_{\text {gd}}$ ) than the SG devices. A lower subthreshold swing (SS) of ~100 mV/dec is obtained by recessed DG design. Due to the second gate inducing the lateral extension of depletion region between the first gate and drain, the off-state leakage and first gate reverse leakage have been significantly improved. Therefore, the recessed DG architecture design can effectively improve the fluctuation of SS and off-state current versus the different AlGaN barrier thickness.

Evidence of Hot-Electron Effects During Hard Switching of AlGaN/GaN HEMTs

This paper reports on the impact of soft- and hard-switching conditions on the dynamic ON-resistance of AlGaN/GaN high-electron mobility transistors. For this study, we used a special double pulse setup, which controls the overlapping of the drain and gate waveforms (thus inducing soft and hard switching), while measuring the corresponding impact on the ON-resistance, drain current, and electroluminescence (EL). The results demonstrate that the analyzed devices do not suffer from dynamic ${R}_{ {\mathrm{\scriptscriptstyle ON}}}$ increase when they are submitted to soft switching up to ${V}_{{\text {DS}}}= 600$ V. On the contrary, hard-switching conditions lead to a measurable increase in the dynamic ON-resistance (dynamic- ${R}_{ \mathrm{\scriptscriptstyle ON}})$ . The increase in dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ induced by hard switching is ascribed to hot-electrons effects: during each switching event, the electrons in the channel are accelerated by the high electric field and subsequently trapped in the AlGaN/GaN heterostructure or at the surface. This hypothesis is supported by the following results: 1) the increase in ${R}_{ \mathrm{\scriptscriptstyle ON}}$ is correlated with the EL signal measured under hard-switching conditions and 2) the impact of hard switching on dynamic ${R}_{ \mathrm{\scriptscriptstyle ON}}$ becomes weaker at high-temperature levels, as the average energy of hot electrons decreases due to the increase scattering with the lattice.

Numerical Investigation of High-Voltage Partial Buried P/N-Layer SOI LDMOS

High-voltage lateral double-diffused MOSFETs with partial buried P/N-type silicon layers (PBPL/PBNL) in silicon-on-insulator (SOI) technology are investigated numerically. In the lateral direction, the partial buried silicon layer (PBL) can introduce an additional electric field peak, which improves the surface electric field distribution and increases the charge accommodation in the drift region. Consequently, in the vertical direction, PBPL and PBNL can both induce higher electric field into the buried-oxide layer, and thus enhance the breakdown voltage (BV) significantly. Due to the higher electron concentration in the drift region, the ON-resistance ( ${R}_{ \mathrm{\scriptscriptstyle ON}}$ ) can be also reduced remarkably. The 2-D simulation results show that PBPL and PBNL SOIs can achieve BVs of 296 and 365 V, respectively, in comparison to the conventional SOI (BV ~ 225 V) and the buried N-layer SOI (BV ~ 231 V). In addition, by comparison with the conventional SOI, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ can be reduced about 31.7% and 13.8% for PBPL and PBNL SOIs, respectively. Finally, hybrid PBPL/PBNL SOIs are studied and shown to be capable of further improving the device performance.

A Snapback-Free Fast-Switching SOI LIGBT With Polysilicon Regulative Resistance and Trench Cathode

A snapback-free fast-switching lateral insulated-gate bipolar transistor (LIGBT) with low power loss and high ruggedness is proposed and investigated by simulation. The proposed device features a polysilicon regulative resistance (PR) and a trench cathode (TC), named PRTC LIGBT. The PR is employed to not only suppress the snapback effect by regulating the voltage drop between P+ anode and N-buffer, but also improve the tradeoff between the on-state voltage drop ( $\text{V}_{ \mathrm{\scriptscriptstyle ON}})$ and turn-off loss ( $\text{E}_{ \mathrm{\scriptscriptstyle OFF}})$ . The TC widens the hole current path and decreases the distributed resistance under N+ cathode, and thus delivers a high latch-up ruggedness. Additionally, the PRTC LIGBT exhibits a blocking characteristic irrelevant to P+ anode concentration (NA), like a p-i-n diode (P-well, N-drift, and N-buffer), owing to its undepleted N-buffer region. Simulation results show that the PRTC LIGBT eliminates the snapback and reduces the $\text{E}_{ \mathrm{\scriptscriptstyle OFF}}$ by 28% compared to the segmented trenches in the anode (STA) region LIGBT. Its short-circuit time is prolonged by 53% and 40% compared to those of the STA LIGBT and PR LIGBT (without TC), respectively.

Insights Into the Operation of Hyper-FET-Based Circuits

Devices combining transistors and phase transition materials are being investigated to obtain steep switching and a boost in the ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio and, thus, to solve power and energy limitations of CMOS technologies. This paper analyzes the operation of circuits built with these devices. In particular, we use a recently projected device called hyper-FET to simulate different circuits, and to analyze the impact of the degraded dc output voltage levels of hyper-FET logic gates on their circuit operation. Experiments have been carried out to evaluate power of these circuits and to compare with counterpart circuits using FinFETs. The estimated power advantages from device level analysis are also compared with the results of circuit level measurements. We show that these estimations can reduce, cancel, or even lead to power penalties in low switching and/or low-frequency circuits. We also discuss relationships with some device level parameters showing that circuit level considerations should be taken into account for device design.

Reduced Junction Leakage by Hot Phosphorus Ion Implantation of NiGe-Contacted Germanium n+/p Shallow Junction

Effects of hot phosphorus (P) implantation on the NiGe-contacted Ge n+/p junction are studied in this work. At an adequately high ion-implantation temperature (150°C), the P depth profiles of the hot-implanted samples are similar to that of the room-temperature implanted ones. Hot P implantation is demonstrated effectively in reducing ion implantation induced defect formation and suppressing nickel atoms diffusion. Therefore, hot P implantation is efficient in lowering junction leakage and excellent junction characteristics exhibiting $\sim 1\times 10^{6}~{J}_{ \mathrm{\scriptscriptstyle ON}}/{J}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio is achieved.

Modeling of a Vertical Tunneling Transistor Based on Graphene–MoS2Heterostructure

In this paper, for the first time, we present a computational study on the electrical behavior of the field-effect tunneling transistor based on vertical graphene–MoS2 heterostructure and vertical graphene nanoribbon–MoS2 heterostructure. Our simulation is based on nonequilibrium Green’s function formalism along with an atomistic tight-binding (TB) model. The TB parameters are obtained by fitting the bandstructure to first-principle results. By using this model, electrical characteristics of device, such as ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio, subthreshold swing, and intrinsic gate-delay time, are investigated. We show that the combination of tunneling and thermionic transport allows modulation of current by four orders of magnitude confirming experimental results. The results indicate that the increase of MoS2 layer numbers leads to a higher ${I}_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio but degrades the intrinsic gate-delay time. Furthermore, it can be observed from the results that as the ribbon width increases the ${I}_{ \mathrm{\scriptscriptstyle ON}}$ of device increases at the cost of a lower ${I}_{ \mathrm{\scriptscriptstyle ON}}/I_{ \mathrm{\scriptscriptstyle OFF}}$ ratio.