Schottky Barrier MOSFETs Research Articles

Scalability of Schottky barrier metal-oxide-semiconductor transistors.

In this paper, the general characteristics and the scalability of Schottky barrier metal-oxide-semiconductor field effect transistors (SB-MOSFETs) are introduced and reviewed. The most important factors, i.e., interface-trap density, lifetime and Schottky barrier height of erbium-silicided Schottky diode are estimated using equivalent circuit method. The extracted interface trap density, lifetime and Schottky barrier height for hole are estimated as 1.5 × 1013 traps/cm2, 3.75 ms and 0.76 eV, respectively. The interface traps are efficiently cured by N2 annealing. Based on the diode characteristics, various sizes of erbium-silicided/platinum-silicided n/p-type SB-MOSFETs are manufactured and analyzed. The manufactured SB-MOSFETs show enhanced drain induced barrier lowering (DIBL) characteristics due to the existence of Schottky barrier between source and channel. DIBL and subthreshold swing characteristics are comparable with the ultimate scaling limit of double gate MOSFETs which shows the possible application of SB-MOSFETs in nanoscale regime.

Design of a novel high performance Schottky barrier based compact transmission gate

In this work, we propose and simulate a novel single transistor based transmission gate. The proposed device is a double gate Schottky device employing a stack of platinum silicide and erbium silicide materials to realize metal source and drain regions. The novelty of the proposed device lies in its ability to realize both n and p type modes simultaneously, which is normally being realized by a parallel combination of NMOS and PMOS transistors in a conventional transmission gate. The proposed device is compact, has reduced number of regions, junctions and interconnects in comparison to the conventional transmission gate. A two dimensional (2D) calibrated simulation study has shown a reduction of 10.42% in average delay and 18.7% in the total power dissipation in the proposed transmission gate in comparison to the conventional Schottky barrier MOSFETs based transmission gate. Furthermore, it has been observed that such a transmission gate action cannot be realised by folding the conventional NMOS and PMOS transistors.

Comprehensive Analysis on Characteristics of SiC Power Device

Analyzing the research status and development trend of SiC (Silicon Carbide) power device, this article describes the latest research results of switching characteristics and power loss characteristics of SiC power device. With detailed analysis on switching characteristics of Schottky Barrier Diode (SBD) and MOSFET, this paper emphasizes on the differences between them and the corresponding power devices. The comparison study between power loss characteristics of MPS and valve loss of silicon carbide thyristor for ultra-high voltage, also and the differences in power loss of switching power supply between SiC MOSFET and Si MOSFET provide scientific basis for the optimal selection and application of SiC power device.

Design and investigation of double gate Schottky barrier MOSFET using gate engineering

For the first time, a distinctive approach to design and investigate double-gate Schottky Barrier MOSFET (DG SB-MOSFET) using gate engineering is reported. Three isolated gates (one Control gate and two N-gates) of different work-functions on both sides of the gate oxides have been used. In the proposed device, without the need of doping, n-type region is formed at the source/drain contact-channel interfaces by inducing electron in the ultrathin intrinsic silicon channel using appropriate work-function metal N-gates. Using N-gates, the Schottky barrier height and tunnelling barrier width have been modulated to enhance the carrier injection similar to conventional dopant segregated (DS) SB-MOSFET. Moreover, the proposed DG SB-MOSFET behaves such as a conventional DS SB-MOSFET. The proposed device is expected to be free from variability caused by random dopant fluctuations. Furthermore, it offers simplified process flow with relaxing the need of doping to form dopant segregation layer and increased immunity to device variability.

Analysing black phosphorus transistors using an analytic Schottky barrier MOSFET model

Owing to the difficulties associated with substitutional doping of low-dimensional nanomaterials, most field-effect transistors built from carbon nanotubes, two-dimensional crystals and other low-dimensional channels are Schottky barrier MOSFETs (metal-oxide-semiconductor field-effect transistors). The transmission through a Schottky barrier-MOSFET is dominated by the gate-dependent transmission through the Schottky barriers at the metal-to-channel interfaces. This makes the use of conventional transistor models highly inappropriate and has lead researchers in the past frequently to extract incorrect intrinsic properties, for example, mobility, for many novel nanomaterials. Here we propose a simple modelling approach to quantitatively describe the transfer characteristics of Schottky barrier-MOSFETs from ultra-thin body materials accurately in the device off-state. In particular, after validating the model through the analysis of a set of ultra-thin silicon field-effect transistor data, we have successfully applied our approach to extract Schottky barrier heights for electrons and holes in black phosphorus devices for a large range of body thicknesses.

A High-Performance Source Engineered Charge Plasma-Based Schottky MOSFET on SOI

In this paper, we address an important issue of low ON current in a Schottky barrier (SB) MOSFET by proposing a novel structure of Schottky MOSFET on silicon on insulator. The proposed Schottky device employs a dual material at the source side and is being named as the source engineered SB MOSFET (SE-SB-MOSFET). Erbium silicide (ErSi1.7) is used as the main source material, and Hafnium is used as a source extension. The use of Hafnium as a source extension induces an n+-type charge plasma in an undoped silicon film, which significantly reduces the SB thickness. A calibrated simulation study has shown that the ON current ( $I_{{{\mathrm{{\scriptscriptstyle ON}}}}}$ ) and $I_{{{\mathrm{{\scriptscriptstyle ON}}}}}/I_{{{\mathrm{{\scriptscriptstyle OFF}}}}}$ have increased by 225 and $65\times $ , respectively, in the proposed device in comparison with the conventional SB-MOSFET device. The ac analysis has shown that the cutoff frequency ( $f_{T}$ ) in the proposed SE-SB-MOSFET ( $\sim 200$ GHz) has increased by $200\times $ as compared with the conventional SB-MOSFET ( $\sim 1$ GHz). Furthermore, the performance of the proposed device has been tested at the circuit level also. It has been observed from the transient analysis that a significant reduction in switching ON delay ( $65\times $ ) and switching OFF delay (33%) has been achieved in the proposed SE-SB-MOSFET-based inverter in comparison with the conventional device-based inverter. Furthermore, the use of the charge plasma concept makes the fabrication of the proposed device relatively easy as it uses low thermal budget.

Suppression of ambipolar leakage current in Schottky barrier MOSFET using gate engineering

A novel asymmetric isolated gates dopant segregated Schottky barrier MOSFET (AIG DS-SBMOS) for the suppression of ambipolar leakage current (I AMB) using gate engineering is reported. The AIG DS-SBMOS consists of a dopant segregated source/drain with two asymmetric isolated gates (control gate, fixed gate) having different metal work functions. The control gate is used to control current conduction by modifying the Schottky barrier height and width at the source/channel junction; while, the fixed gate modulates the drain side Schottky barrier to the suppress I AMB caused by hole injection in the off-state condition. In contrast to the conventional SBMOS and DS-SBMOS that suffer from ambipolarity, the proposed device is free from severe I AMB. Moreover, the proposed AIG DS-SBMOS has a high I ON/I OFF ratio of 107 with nearly the same I ON and subthreshold swing as that of the DS-SBMOS. The proposed device structure is especially beneficial for nanowire-based transistors.

A planar Al-Si Schottky barrier metal–oxide–semiconductor field effect transistor operated at cryogenic temperatures

Schottky Barrier-MOSFET technology offers intriguing possibilities for cryogenic nano-scale devices, such as Si quantum devices and superconducting devices. We present experimental results on a device architecture where the gate electrode is self-aligned with the device channel and overlaps the source and drain electrodes. This facilitates a sub-5 nm gap between the source/drain and channel, and no spacers are required. At cryogenic temperatures, such devices function as p-MOS Tunnel FETs, as determined by the Schottky barrier at the Al-Si interface, and as a further advantage, fabrication processes are compatible with both CMOS and superconducting logic technology.

Ambipolar Leakage Suppression in Ge n-channel Schottky Barrier MOSFET

ABSTRACTThis work presents a comprehensive study on ambipolar leakage suppression in Ge n-channel Schottky barrier MOSFETs (Ge n-SB MOSFETs). Also, Fermi level pinning due to metal-induced gap states between the metal contact and semiconductor is another constraint in this device, which restricts the modulation of Schottky barrier height. Here, we effectively suppress the ambipolar leakage by employing underlap gate structure over drain-channel junction, in addition with dopant segregation (DS) to depin the Fermi level. We also investigate the influence of the DS layer doping, thickness, and temperature dependence of ambipolar behaviour using two-dimensional numerical device simulations.

The Impact of Temperature and Switching Rate on the Dynamic Characteristics of Silicon Carbide Schottky Barrier Diodes and MOSFETs

Silicon carbide Schottky barrier diodes (SiC-SBDs) are prone to electromagnetic oscillations in the output characteristics. The oscillation frequency, peak voltage overshoot, and damping are shown to depend on the ambient temperature and the metal-oxide- semiconductor field-effect transistor (MOSFET) switching rate (dI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> /dt). In this paper, it is shown experimentally and theoretically that dI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> /dt increases with temperature for a given gate resistance during MOSFET turn-on and reduces with increasing temperature during turn-off. As a result, the oscillation frequency and peak voltage overshoot of the SiC-SBD increases with temperature during diode turn-off. This temperature dependence of the diode ringing reduces at higher dI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> /dt and increases at lower dI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> /dt. It is also shown that the rate of change of dIDS/dt with temperature (d <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> /dtdT) is strongly dependent on R <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> and using fundamental device physics equations, this behavior is predictable. The dependence of the switching energy on dI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> /dt and temperature in 1.2-kV SiC-SBDs is measured over a wide temperature range (-75 °C to 200 °C). The diode switching energy analysis shows that the losses at low dI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> /dt are dominated by the transient duration and losses at high dI <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> /dt are dominated by electromagnetic oscillations. The model developed and results obtained are important for predicting electromagnetic interference, reliability, and losses in SiC MOSFET/SBDs.

Formation of PtSi Schottky barrier MOSFETs using plasma etching

PtSi Schottky barrier (SB) MOSFETs were fabricated and their device performance was characterized. PtSi was selected instead of NiSi to form the p-type SB junction since such a configuration would be easy to fabricate through SF6 based plasma etching. The addition of He-O2 in SF6 decreases the etching rate of PtSi while the etching rate of Pt remains unchanged. The retardation in the etching rate of PtSi in He-O2/SF6 is attributed to the formation of a metal oxide on the etched PtSi surface, as evidenced by the x-ray photoelectron spectroscopy results. Optical emission spectroscopy was conducted to establish the endpoint where the wavelength from the feed gas was traced instead of tracing the etching by-products since the by-products have little association with the plasma reaction. The IDS–VDS curves at various VG–VTH indicate that plasma etching resulted in the successful removal of the Pt on the sidewall region, with negligible damage to the S/D area.

Performance Assessment of III–V Channel Ultra-Thin-Body Schottky-Barrier MOSFETs

The performance of III-V channel ultra-thin-body Schottky barrier (SB) MOSFETs is assessed by quantum mechanical simulations. All the Γ-, L-, and Δ-valleys are included in the calculations, with their effective masses adjusted by the sp 3 d 5 s* tight-binding method. Our results show that InSb and InAs channel devices are not adequate for SB devices due to high ambipolar currents. InSb, InAs, and GaAs channel devices suffer from the serious density-of-states (DOS) bottleneck problem. Their transconductances are only about 1/4 of that of Si channel devices. On the other hand, GaSb channel devices which are immune from the DOS bottleneck show excellent performance. The transconductance and ON-state current that are, respectively, 1.2 and 1.8 times as large as that of Si-based devices can be achievable.

2D physics-based closed-form modeling of dopant-segregated Schottky barrier UTB MOSFETs

A 2D closed-form, analytical compact current model for long and short-channel Schottky barrier (SB) Multi-Gate MOSFETs is presented. The physics-based two-dimensional model for the electrostatic potential and electric field of a ultra-thin body (UTB) MOSFET is derived with the help of Poisson’s equation and the conformal mapping technique by Schwarz–Christoffel. Furthermore, simple closed-form current equations were derived by using analytical expressions for the tunneling and thermionic currents. Essential 2D effects on the currents are included in the model which are combined with diffusion effects in the channel region. A comparison of our 2D physics-based compact model is done versus measurement data for a dopant segregated fully-depleted Schottky barrier MOSFET.

Operation and scalability of dopant-segregated Schottky barrier MOSFETs with recessed channels

Recessed channels were used in scaled dopant-segregated Schottky barrier MOSFETs (DS-SBMOS) to control the severe short-channel effect. The physical operation and device scalability of the DS-SBMOS resulting from the presence of recessed channels and associated gate-corners are elucidated. The coupling of Schottky and gate-corner barriers has a key function in determining the on–off switching and drain current. The gate-corner barriers divide the channel into three regions for protection from the drain penetration field. To prevent resistive degradations in the drive current, an alternative asymmetric recessed channel (ARC) without a source-side gate-corner is proposed to simultaneously optimize both the short-channel effect and drive current in the scaled DS-SBMOS. By employing the proposed ARC architecture, the DS-SBMOS devices can be successfully scaled down, making them promising candidates for next-generation CMOS devices.

Performance assessment of nanoscale Schottky MOSFET as resonant tunnelling device: Non-equilibrium Green’s function formalism

A comprehensive study is performed on the electrical characteristics of Schottky barrier MOSFET (SBMOSFET) in nanoscale regime, by employing the non-equilibrium Green’s function (NEGF) approach. Quantum confinement results in the enhancement of effective Schottky barrier height (SBH). High enough Schottky barriers at the source/drain and the channel form a double barrier profile along the channel that results in the formation of resonance states. We have, for the first time, proposed a resonant tunnelling device based on SBMOSFET in which multiple resonance states are modulated by the gate voltage. Role of essential factors such as temperature, SBH, bias voltage and structural parameters on the feasibility of this device for silicon-based resonant tunnelling applications are extensively studied. Resonant tunnelling appears at low temperatures and low drain voltages and as a result negative differential resistance (NDR) is apparent in the transfer characteristic. Scaling down the gate length to 6 nm increases the peak-to-valley ratio (PVR) of the drain current. As the effective SBH reduces, the curvature of the double barrier profile is gradually diminished. Therefore, multiple resonant states are contributed to the current and consequently resonant tunnelling is smoothed out.

Fast High Voltage Switching with SiC Majority Carrier Devices

Raising operation voltage of power conversion circuit is effective in reducing conduction loss. It requires power switching device to have high breakdown voltage. High voltage Si power device requires bipolar operation to reduce conduction loss sufficiently. However, bipolar operation worsens the switching characteristics of the device especially in turn off operation; such as reverse recovery for PiN diode and tail current for IGBT. The high critical electric field of SiC semiconductor realizes high break down voltage majority carrier device with substantially low on resistance. It can achieve fast switching capability for it only requires conducting and blocking majority carrier in the device for switching operation. This paper demonstrates the fast high voltage switching operation of SiC Schottky barrier diode (SBD) and MOSFET with comparing to the conventional Si device.

Compact modeling solutions for short-channel SOI Schottky barrier MOSFETs

In this paper we present the modeling of the main current transport mechanisms in Schottky barrier (Double-Gate) MOSFET devices. A detailed way of the two-dimensional modeling approach with further analyses of the primary current components is given. Afterwards, these analyses are the basis of the development of a fully 2D compact model, which is able to predict the current behavior in reasonable device structures. A comparison and verification with TCAD simulation and measurement data is done with the evolved model current equations.

Simulation Study of Germanium p-Type Nanowire Schottky Barrier MOSFETs

Ambipolar currents in Germanium p-type nanowire Schottky barrier MOSFETs were calculated fully quantum-mechanically by using the multi-band k.p method and the non-equilibrium Green's function approach. We investigated the performance of devices with 100, 110, and 111 channel orientations, respectively, by varying the nanowire width, Schottky barrier height, and EOT. The 111 oriented devices showed the best performance. In comparison to Si as a channel material, Ge is more desirable because more current can be injected into the channel, resulting in steeper subthreshold slope and higher on-state current. Our calculations predict that the Ge channel devices should have an EOT gain of 0.2-0.5 nm over Si channel devices.

Nanometer scale p-type Schottky barrier metal–oxide-semiconductor field-effect transistor using platinum silicidation through oxide technique combined with two-step annealing process

25-nm-gate-length Schottky barrier metal–oxide-semiconductor field-effect transistors (SB-MOSFETs) with platinum silicide (PtSi) was fabricated using silicidation through oxide technique coupled with two-step annealing process. The manufactured SB-MOSFET showed a large on/off current ratio (>107) with excellent short-channel characteristics such as low values of subthreshold swing (83mV/dec.) and drain induced barrier lowering (23mV). A controlled Pt flux caused by the densification of SiOx during low temperature 1st step annealing leads to the homogeneous growth of PtSi films at high temperature 2nd step annealing, which was responsible for the superior device performance of nanometer scale SB-MOSFET.

Impact of Silicon Wafer Orientation on the Performance of Metal Source/Drain MOSFET in Nanoscale Regime: a Numerical Study

A comprehensive study of Schottky barrier MOSFET (SBMOSFET) scaling issue is performed to determine the role of wafer orientation and structural parameters on the performance of this device within Non-equilibrium Green's Function formalism. Quantum confinement increases the effective Schottky barrier height (SBH). (100) orientation provides lower effective Schottky barrier height in comparison with (110) and (111) wafers. As the channel length of ultra thin body SBMOSFET scales down to nanoscale regime, especially for high effective SBHs, quantum confinement is created along the channel and current propagates through discrete resonance states. We have studied the possibility of resonant tunneling in SBMOSFET. Resonant tunneling for (110) and (111) orientations appear at higher gate voltages.