SAR Logic Research Articles

A Non-Linear Successive Approximation Finite State Machine for ADCs with Robust Performance

This work presents the detailed design of a Successive Approximation Analog to Digital Data Converter (SAR ADC) using bulk 180 nm CMOS IC technology. The focus of the study is on replacing the typical Successive Approximation Register array with a Finite State Machine. This converter features a fully differential and bipolar architecture, which leads to the logic SAR nonlinear behavior. A novel digital control logic mitigates the conversion errors through the conditions in the previous logic states. The logic scheme, in combination with a robust continuous comparator, demonstrates tolerance to Process, Voltage, and Temperature variations. The architecture does not include calibration or additional redundancies in post-layout simulations to emphasize the exclusive benefits of the new SAR logic. The proposed SAR ADC achieves a 14.07 effective number of bits with 7.04 fJ/conversion step Walden figure of merit in biomedical applications.

A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications.

A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage Vaq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s.

A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient Switching Scheme for Wearable Biosensor Applications.

A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage Vcm, and common-mode techniques, the proposed switching scheme achieves 93.76% less switching energy compared to the conventional scheme with common-mode voltage shift in one LSB. With the switching scheme, the proposed SAR ADC can lower the dependency on the accuracy of Vcm and the complexity of digital control logic and DAC driver circuits. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low sampling error sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrate that the ADC achieves a 61.77 dB SNDR and a 78.06 dB SFDR and consumes 4.45 μW of power in a 180 nm process with a 1 V power supply, a full-swing input signal frequency of 93.33 kHz, and a sampling rate of 200 kS/s.

A 12~14-Bit SAR-SS Hybrid ADC with SS Bit Shifting Resolution Reconfigurable Method for Bio-Signal Processing

This paper presents a low-power, high-resolution reconfigurable hybrid ADC for bio-electrical signal processing. The proposed ADC contains a SAR ADC for the most significant bit (MSB) and a single-slope ADC for the least significant bit (LSB). To solve the issue of exponentially increasing sampling speed based on the resolution of the single-slope ADC, the SAR ADC is designed to be reconfigurable with a resolution of 8–10-bit, while the single-slope ADC is configured with a resolution of 4-bit. To achieve this resolution reconfiguration, the bit shifting method is proposed and implemented with reconfigurable SAR logic circuit and 4-bit single-slope digital ramp generator. Measurement results demonstrate the power consumption of 34.0 uW, which includes analog power of 23.8 uW and digital power of 10.2 uW, INL/DNL of ±3.5 LSB and −1.0/+2.5 LSB. The ENOB and FoM are measured to be 10.8 bits and 53 fJ/step, respectively.

A ENOB 10.3 bit, 103 μW ON-CHIP CALIBRATION SAR ADC

Across the board, the performance of ADCs has been under increasing scrutiny because of the rapid growth of portable electronic devices and biomedical sensors. As part of the sensor’s long-term work, its power consumption should also be as low as possible. Sensors benefit from SAR ADCs’ small size and low power consumption, making them an ideal fit for ADCs. To overcome the limitations of accuracy and linearity of ADCs caused by manufacturing process deviations, a 12-bit, 1 MS/s low-power SAR ADC based on 180 nm CMOS technology is presented. The front-end analog calibration system ensures the ADC is at its best. The design also includes low fan-in SAR logic to reduce the capacitive load on the comparator and increase the comparison speed. The layout area is 0.3 mm2, approximately 30% less than conventional products of the same process.

A 13b 600-675MS/s Tri-State Pipelined-SAR ADC With Inverter-Based Open-Loop Residue Amplifier

This article presents a 13-b high-speed pipelined-successive-approximation-register (pipelined-SAR) analog-to-digital converter (ADC). By utilizing the comparator metastability, a tri-state SAR logic is introduced to achieve a fast approximation process. The tri-state SAR outputs three states by one comparator after each comparison cycle, and the effective-number-of-bits (ENOBs) can improve up to 1 b when the metastability boundary is set at ±1/4 LSB. In addition, an open-loop inverter-based residue amplifier (RA) is proposed with simple circuit implementation. The RA gain is well defined by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$g_{m}$ </tex-math></inline-formula> ratio and is immune to process, voltage, and temperature (PVT) variations. Fabricated in 40-nm CMOS technology, the prototype ADC achieves a mean signal-to-noise plus distortion ratio (SNDR) of 59.8–62.8 dB, with 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\sigma $ </tex-math></inline-formula> than 1.7 dB, at 600–625 MS/s over −40° to 125° temperature range and 1.1–1.2 V power supply range, a 67 dB dynamic range (DR), and a 62.4 dB SNDR for a Nyquist input while sampling at 625 MS/s. The overall power consumption is 7.05 mW.

A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor

A 10 bit 1 MS/s SAR ADC with one LSB common-mode shift energy-efficient switching scheme for image sensor is presented. Based on the two sub-capacitor arrays architecture and the common-mode technique, the proposed switching scheme achieves 98.45% less switching energy over the conventional architecture with common-mode shift in one LSB. The comparator uses a low power dynamic comparator. The sampling switch adopts a bootstrap circuit with low sampling error. SAR logic is composed of Bit-Slice circuit with low power consumption and few transistors. Simulated in 180 nm CMOS process and 1 MS/s sampling rate, the ADC achieves the 60.06 dB SNDR, the 75.43 dB SFDR and the 10.45 μW power consumption.

A 72-dB SNDR 130-MS/s 0.8-mW Pipelined-SAR ADC Using a Distributed Averaging Correlated Level Shifting Ring Amplifier

This article presents a 14-b 130-MS/s two-stage pipelined-SAR analog-to-digital converter (ADC) using a distributed averaging correlated level shifting (DACLS) ring amplifier as its residue amplifier (RA). Compared to the prior CLS and ACLS techniques that reduce the RA gain error due to their finite open-loop gain, the proposed DACLS ring amplifier no longer requires an extra level-shifting capacitor ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$C_{\mathrm {LS}}$ </tex-math></inline-formula> ) at the RA output, such that the RA bandwidth can be improved. Furthermore, instead of a single-level shift in the prior arts, the DACLS ring amplifier provides an option for multiple level shifts and thereby accomplishes a greater RA gain error reduction. In addition, a customized bypass-window scheme is applied, which can skip some power-wasting digital-to-analog converter (DAC) switchings by window detection and thus reduces the power consumption of the ADC. To reduce the bit-cycling time of the SAR conversion, a delay-reduced (DR) SAR logic is introduced to increase the ADC speed. The ADC chip is fabricated in 28-nm CMOS technology and occupies an active area of 0.013 mm2. At 130-MS/s and the Nyquist-rate input frequency, the measured SNDR is 72.5 dB, while the power consumption is only 0.82 mW. Without any calibration, the proposed ADC achieves a Walden and a Schreier figure-of-merit (FoM) of 1.8 fJ/conversion step and 181.5 dB, respectively. Compared to the prior-art ADCs with an input bandwidth ≥ 40 MHz and a SNDR > 68 dB, this work shows the best FoMs.

A 7.6-nW 1-kS/s 10-Bit SAR ADC for Biomedical Applications.

This paper presents a 10-bit successive approximation register analog-to-digital converter with energy-efficient low-complexity switching scheme, automatic ON/OFF comparator and automatic ON/OFF SAR logic for biomedical applications. The energy-efficient switching scheme achieves an average digital-to-analog converter switching energy of 63.56 CVref2, achieving a reduction of 95.34% compared with the conventional capacitor switching scheme for CDACs. With the switching scheme, the ADC can lower the dependency on the accuracy of Vcm and complexity of DAC control logic and DAC driver circuit. Moreover, dynamic circuits and automatic ON/OFF technology are used to reduce power consumption of comparator and SAR logic. The prototype is designed and fabricated in a 180 nm CMOS with a core size of 500 μm × 300 μm (0.15 mm2). It consumes 7.6 nW at 1 kS/s sampling rate and 1.8-V supply with an achieved signal-to-noise-and distortion ratio of 45.90 dB and a resulting figure of merit of 51.7 fJ/conv.-step.

A 14-b 20-MS/s 78.8 dB-SNDR Energy-Efficient SAR ADC With Background Mismatch Calibration and Noise-Reduction Techniques for Portable Medical Ultrasound Systems.

This paper presents a 14-b 20-MS/s energy-efficient SAR ADC in 65-nm CMOS technology for portable medical ultrasound systems. To break the limitation of the ADC linearity on the DAC size in a SAR ADC, a background mismatch calibration technique is employed. As a result, the thermal noise will be the major constraint for the DAC size. In addition, a compact noise-reduction technique is proposed to alleviate the adverse impact of the input-referred comparator noise on the effective resolution. Moreover, a 2.5-V on-chip LDO, which serves as the reference generator for the ADC core, is also integrated to guarantee the reference accuracy and to suppress the supply noise. To reduce the capacitive load of the comparator and boost the comparison speed, a low fan-in SAR logic is also designed. With the proposed mismatch calibration technique and the noise-reduction technique activated, measured results indicate that the peak signal-to-noise-and-distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) achieve 78.8 dB and 95.4 dB, respectively. At 20 MS/s, the ADC consumes 6.8mW from its 1.2 V/3.3V supplies in total, leading to an SNDR-based Schreier FOM of 170.5 dB at Nyquist. The active area of the ADC is 450 × 540μm2.

Multi-threshold window discriminator based on SAR logic

The new X-ray imaging detectors allow capturing an X-ray image in various photon energy ranges in one shot. This technique is called X-ray color imaging, and it is becoming a promising method in fields such as medical imaging, computed tomography, and non-destructive material testing. To measure the energy spectrum in one shot, discriminant circuits need to be integrated into the pixel front-end electronics. Several solutions of in-pixel discriminators exist. However, current designs suffer from a low number of discrimination bins and need to adjust each threshold separately, leading to relatively complicated calibration procedures. This work introduces a novel design of a multi-threshold window discriminator based on successive approximation register logic. This circuit realizes in-pixel binning to ten equidistant windows. Two variables are used for tuning the multi-threshold window discriminator: offset of the first window and width of the windows. Setting these parameters allows the user to fulfill the need of the target application.

A 2.4 GHz receiver with a current-reused inductor-less noise-canceling balun LNA in 40 nm CMOS

A low power receiver is designed and implemented for 2.4 GHz Industrial-Scientific-Medical (ISM) band in a 40 nm CMOS process. To obtain good noise and linearity performance at low cost, a current-reused low power inductor-less balun low noise amplifier (LNA) structure is proposed without use of monolithic spiral inductors or transformers. The receiver adopts a zero-IF architecture and current mode mixing operation which avoid need of large voltage headroom for the radio frequency (RF) voltage swing under strong interferers. A third order active-RC low pass filter (LPF) with RC calibration and DC offset cancelation (DCOC) blocks are carefully designed. Current reusing technique and timing optimized asynchronous SAR logic are adopted in LNA and ADC design respectively, featuring high-power efficiency. The total receiver chain achieves maximum conversion gain of 80.32 dB, noise figure (NF) of 6.27 dB and input referred third-order intercept point (IIP3) of −0.6 dBm with 32.8 mW power consumption.

Design of 16-Bit SAR ADC Using DTMOS Technique

This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

Design of 16-Bit SAR ADC Using DTMOS Technique

This paper presents a 16-bit 100MS/s SAR ADC with 1V power supply for biomedical implant systems developed with low power technique i.e., DTMOS logic. It consists of a R-2R DAC, low-power comparator, a digital SAR logic with low-leakage. The designed comparator is a differential architecture that has used to have an excellent, common-mode noise rejection. Comparator was created for proper operation to remain in saturation and could be used with differential amplifier. The comparator is the chief block of power consumption, so we focused mainly much of ability we make to design this module. The ADC is designed using Cadence virtuoso with CMOS 45nm technology. For SFDR, SNR, ENOB and power consumption, the converter utilizes 63.97dB, 51.06 dB, 15.15 and 528.8uw.

A 6.4-GS/s 10-b Time-Interleaved SAR ADC with Time-Skew Immune Sampling Network in 28-nm CMOS

This paper presents a 6.4-GS/s 16-way 10-bit time-interleaved (TI) SAR ADC for wideband wireless applications. A two-stage master–slave hierarchical sampling network, which is immune to the time skew of multi-phase clocks, is introduced to avoid the time-skew calibration for design simplicity and hardware efficiency. To perform low distortion and fast sampling at acceptable power consumption, a linearity- and energy efficiency-improved track-and-hold (T&amp;H) buffer with current-feedback compensation scheme is proposed. Accompanied by its low-output-impedance feature, the buffer obtains adequate bandwidth which can cover the entire ADC Nyquist sampling range. Moreover, the split capacitor DAC combined with a novel nonbinary algorithm is adopted in single-channel ADC, enabling a shorter DAC settling time as well as less switching energy. Capacitor mismatch effect with related design trade-off is discussed and behavior models are built to evaluate the effect of capacitor mismatch on ENOB. An asynchronous self-triggered SAR logic is designed and optimized to minimize the delay on logic paths to match up the acceleration on DAC and comparator. With these proposed techniques, the 10-b sub-ADC achieves a 400-MHz conversion rate with only 3.5-mW power consumption. The circuit is designed and simulated in TSMC 28 HPC process and the results show that the overall ADC achieves 54.6-dB SNDR and 58.1-dB SFDR at Nyquist input while consuming 127-mW power from 1-V/1.5-V supply and achieving a Walden FoM of 45[Formula: see text]fJ/conv-step.

Design of 10 Bit ADC of SAR Type to Increase the Accuracy for Biomedical Applications

In this paper a low power consuming 10 bit SAR ADC which is suitable for Biomedical applications is presented. It was designed with 180nm technology using cadence tool. SAR ADC is made of dynamic comparator, sample and hold circuit, SAR logic, and DAC block. The designed circuit works on a supply voltage of 1V. The proposed SAR design, with the use of dynamic comparator circuit will help to reduce power and even at the same time with the use of binary weighted CDAC also provides low power dissipation. In order to decide the next significant bit by the knowledge of previous bits the successive approximation algorithm runs over several clock cycles for analog to digital conversion. Power usage and complexity of the circuit is minimized by low conversion rate i.e permitting one clock for each bit in the proposed method.

A No-Trim, Scaling-Friendly Thermal Sensor in 16nm FinFET Using Bulk Diodes as Sensing Elements

We present a simple, yet robust architecture to achieve accurate temperature sensing without the need for costly calibration. For the first time, the active bulk diode of a standard CMOS process is utilized in replacement of BJT devices. Two such diodes are forward biased by a charge pump, which periodically discharges two sampling capacitors across the diodes. The sampled voltages are then combined to generate PTAT and CTAT signals. A passive charge-balancing scheme creates a digital output, which only requires a comparator, an 8-bit capacitive divider and SAR logic. Occupying 2500 μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area in 16-nm FinFET, the sensor operates down to 0.85 V and features intrinsic supply robustness. It achieves an uncalibrated accuracy of +1.5/-2.0 °C (min/max) across the consumer temperature range, and dissipates 230 pJ in a 12.8 μs conversion time. Due to the simplicity and low analog content of this concept, it is insensitive to future scaling and well suited for use at multiple locations in SoCs.

A Calibration-Free 12-bit 50-MS/s Full-Analog SAR ADC With Feedback Zero-Crossing Detectors

This paper presents a calibration-free 12-bit 50-MS/s full-analog SAR analog-to-digital (A-to-D) converter (ADC) in 40-nm CMOS, which integrates the functions of comparator, SAR logic, and digital-to-analog converter (DAC) switches into multiple feedback zero-crossing detectors (FB-ZCDs). By eliminating all the digital circuits, the full-analog bit conversions operate with the asynchronous amplification-to-regeneration (A-to-R) operation that highly relaxes the requirements of the analog circuits and reference generator. This paper is implemented without any calibration, where the non-ideal effects (offset mismatch, insufficient residue, and noise) are mitigated and eliminated with the proposed techniques as follows. The offset mismatches among the FB-ZCDs are covered by the redundancies of the sub-radix DAC arrangement in the coarse ADC. The bottom-plate coupling compensators (BPCCs) are proposed to correct the consecutive SAR decision errors as quantizing the insufficient residue. The shared FB-ZCD with capacitor coupling decision (CCD) network is developed to obtain the identical offset in the fine ADC. Amplification extension (AE) technique is proposed to enhance the precision of the shared FB-ZCD by reconfiguring as a complementary inverter-based amplifier with the extended amplification period to enhance the output SNR. This paper occupies an active area of 0.01 mm2 and achieves the Nyquist-rate signal-to-noise-and-distortion ratio (SNDR), spurious-free dynamic range (SFDR), Walden figure-of-merit (FoMW), and Schreier FoM (FoMS) of 64.1, 75.6 dB, 5.3 fJ/conversion step, and 172.8 dB, respectively.

A 0.9-V 12-bit 100-MS/s 14.6-fJ/Conversion-Step SAR ADC in 40-nm CMOS

This paper presents a low-power 12-bit 100-MS/s asynchronous successive approximation register analog-to-digital converter (SAR ADC). Several techniques are developed to enhance the ADC performance. The nonbinary capacitor array with small digital-to-analog converter (DAC) capacitors (total 394 fF) allows for reducing DAC settling time and power consumption while maintaining extremely high hardware utilization. The proposed nonlinear capacitance correction method solves the nonlinear capacitance problems of the comparator when the small unit capacitor is used. The latch output glitch removal method ensures the speed and accuracy of the comparator at the low supply voltage. Furthermore, the proposed high-speed SAR logic and timing sequence improved SAR logic’s operating speed by 75% compared with traditional SAR logic. The prototype was fabricated using a 40-nm CMOS technology. At a 0.9-V supply and 100-MS/s sampling rate, the ADC achieves a signal-to-noise distortion ratio of 67.3 dB and consumes 2.6 mW, resulting in a figure of merit of 14.6 fJ/conversion-step. The ADC core occupies an active area of only $50 \times 280\,\,\mu \text{m}^{2}$ .

A System-Level Correction SAR ADC with Noise-Tolerant Technique

A system-level correction successive approximation register analog-to-digital converter (SAR ADC) with regulated comparator of noise-tolerant technique is proposed. First, a substrate voltage boost technique is provided to improve the linearity and speed of sampling switch. Secondly, the proposed SAR ADC provides a comparator of noise regulation without redundant comparison cycle. The proposed comparator would be regulated in high-speed large noise state in large input differential signals. In the condition of small input differential signals, the comparator would be adjusted to low-speed small noise state. Furthermore, a high-speed low-power technique is proposed to optimize the performance of dynamic comparator. Additionally, a fast SAR logic structure is provided to increase the conversion speed of SAR ADC. To demonstrate the proposed techniques, a design example of SAR ADC is fabricated in 65[Formula: see text]nm CMOS technology. The SAR ADC is able to tolerate about 1.1 LSB noise errors in post-simulation with the operation state regulated automatically. The core occupies an active area of only 0.025[Formula: see text]mm2 and consumes 1.5[Formula: see text]mW. Measurement results achieve SFDR [Formula: see text][Formula: see text]dB and SNDR [Formula: see text][Formula: see text]dB, resulting in the FOM of 21.6[Formula: see text]fJ per conversion step.