Runtime Resource Research Articles

Parallel and Distributed Computing Techniques, Selection of papers from ISPDC 2008

Parallel and Distributed Computing Techniques, Selection of papers from ISPDC 2008

Space profiling for parallel functional programs

This paper presents a semantic space profiler for parallel functional programs. Building on previous work in sequential profiling, our tools help programmers to relate runtime resource use back to program source code. Unlike many profiling tools, our profiler is based on a cost semantics. This provides a means to reason about performance without requiring a detailed understanding of the compiler or runtime system. It also provides a specification for language implementers. This is critical in that it enables us to separate cleanly the performance of the application from that of the language implementation. Some aspects of the implementation can have significant effects on performance. Our cost semantics enables programmers to understand the impact of different scheduling policies while hiding many of the details of their implementations. We show applications where the choice of scheduling policy has asymptotic effects on space use. We explain these use patterns through a demonstration of our tools. We also validate our methodology by observing similar performance in our implementation of a parallel extension of Standard ML.

QoS-Aware service management for component-based distributed applications

Component-based software development has evolved from a tightly coupled style to a loosely coupled style in the recent few years. The paradigm shift will eventually allow heterogeneous systems to interoperate in open networks such as the Internet and will make software development more of a management task than a development task. Envisioning that future applications may comprise dynamically aggregated component services possibly distributed widely, we develop a Quality of Service (QoS)-aware service management framework in the middleware layer to make the component services infrastructure transparent to the applications. Specifically, we manage services not only as individuals, but more importantly as meaningful aggregated entities based on the logical compositional needs coming from the applications, by composing services properly according to QoS requirements at application setup time, and performing continuous maintenance at application runtime seamlessly. Our service management framework is scalable in two dimensions: network size and application's client population size. Specifically, the framework employs a decentralized management solution that scales to large network size, and explores resource sharing in one-to-many group-based applications by means of multicasting mechanisms. Moreover, it incorporates local adaptation operations and distributed failure detection, reporting, and recovery mechanisms to deal with runtime resource fluctuations and failures.

Simulation of Multiple Implementation Queries

This work describes methods to extend a conventional query optimizer to model and yield multiple plans per query, and to schedule the resulting multiple-plan packages. This research focuses on one run-time resource, the buffer pool. A query’s plans for a given query are bundled together into a package. At run-time, a scheduler decides when to admit a package, and then chooses one among the plans in an admitted package. The chosen plan is one that is compatible with available buffers as determined by a variety of scheduling policies. The experimental results verified that a single plan as generated by a query optimizer is not the best one when run-time resources are considered.

Runtime resource checking at WENDELSTEIN 7-X during plasma operation

The super conducting stellarator WENDELSTEIN 7-X (W7-X) is designed as a steady-state device which will run pulses of 30 min or more. During discharges W7-X will be controlled by a dedicated “segment control system” addressed in this article. Due to the innovative nature of a fusion device and its subsystems a failure of a subsystem during a discharge cannot be ruled out. Safety critical failures are handled by the safety system. In many cases a failure leads only to a degradation of the plasma quality and not to a safety critical situation. Because of the long pulses the segment control has to detect the situation and steer the discharge into another state in which preferably the discharge can continue without the failed subsystem or the discharge is gracefully brought to an end. After a short summary of the main aspects of the “segment control system” this paper deals with the online resource check required for fault detection and recovery. It explains how the online resource check is integrated in the control system and how the control system support recovery strategies.

A simulation test-bed for mobile adaptive architectures

Existing mobile systems are typically highly constrained with regards to their run-time resources: CPU, memory, communication bandwidth, screen real-estate, battery, and so forth. In current mobile systems, resource allocation decisions are almost always fixed at the time of system creation. However, this situation is arguably changing as mobile systems are becoming more powerful and as the demands being placed upon them are also increasing dramatically. For this reason, such systems need effective methods to manage and control their resources at run-time, particularly in the face of changing environmental conditions and user needs. This paper presents a simulation test-bed for experimenting with architectural design decisions such as communication and negotiation strategies among components, scheduling algorithms, and usability considerations. One significant area that we have begun to experiment with is the use of user-defined “utility” as a means of making dynamic resource allocation decisions. We will discuss the use of utility as a guide for scheduling, describe the test-bed, and present some examples of the results that we have derived, comparing utility-based scheduling with traditional scheduling methods.

Spout: a transparent proxy for safe execution of Java applets

The advent of executable contents such as Java applets exposes World Wide Web (WWW) users to a new class of attacks that were not possible before. Despite an array of security checking, detection, and enforcement mechanisms built into the language model, the compiler, and the run-time system of Java, serious security breach incidents due to implementation bugs still arose repeatedly in the past several years. Without a provably correct implementation of Java's security architecture specification, it is difficult to make any conclusive statements about the security characteristic of current Java virtual machines. The Spout project takes an alternative approach to address Java's security problems. Rather than attempt a provable secure implementation, we aim to confine the damages of malicious Java applets to selective machines, thus, preventing the machines behind an organization's firewall from being attacked by malicious or buggy applets. More concretely, Spout is a distributed Java execution engine that transparently decouples the processing of an incoming applet's application logic from that of graphical user interface (GUI), such that the only part of an applet that is actually running on the requesting user's host is the harmless GUI code. A unique feature of the Spout architecture that does not exist in other similar systems, is that it is completely transparent to and does not require any modifications to WWW browsers or class libraries on the end hosts. This paper describes the detailed design, implementation, and performance measurements of the first Spout prototype, which also incorporates run-time resource monitoring mechanisms to counter denial-of-service attacks.

Integrating Run-Time Scheduling and Pre-Run-Time Scheduling of Real-Time Processes

This paper presents a new approach that integrates run-time scheduling with prerun-time scheduling, for the scheduling of both periodic and asynchronous processes with hard or soft deadlines, and different a priori knowledge of the process characteristics. A guiding principle for this approach is that the scheduling algorithm should exploit to a maximum extent of any knowledge about system processes’ characteristics that are available to the scheduler both before run-time and during run-time. The approach consists of two phases: a pre-run-time phase and a run-time phase. In the pre-run-time phase, some of the asynchronous processes with hard deadlines and known characteristics will be converted into periodic processes while processor capacity will be reserved for all the remaining asynchronous processes with hard-deadlines. With the use of an optimal scheduling algorithm, the schedulabiilty of the set of periodic processes with hard or soft deadlines and known characteristics will be determined respectively, while the schedulability of all the remaining asynchronous processes with hard deadlines and known characteristics will be verified by checking their worst-case response times. For the set of asynchronous processes with soft deadlines, a best effort approach is used for their scheduling. The advantages of this approach include: (a) the majority of the processes are scheduled before run-time. As the pre-run-time scheduler is not constrained to make scheduling decisions in a short amount of time, it can use better algorithms to take advantage of known process characteristics, handle more complex constraints，and achieve higher schedulability. (b) As only a small number of asynchronous processes with hard deadlines is scheduled at run-time, it reduces the amount of run-time resources required for scheduling and context switching. (c) As the run-time scheduler is aware of the future start times of processes in the pre-run-time schedule, the run-time scheduler can make more informed decisions at run-time. Thus this approach increases the chances that one can guarantee satisfaction of all constraints before run-time.

Replicating parallel simulation on heterogeneous clusters

Abstract An effective approach of replicating parallel discrete-event simulation on heterogeneous workstation clusters is presented. In this approach, each replication of parallel simulation known as replicated parallel simulator (RPS) can reconfigure adaptively according to runtime resource availability. RPSs compete with other applications for computing resources in a shared-network environment of workstation clusters through a runtime system called Comedians . This approach aims to combine the benefits of parallelism and replication so that overall simulation performance can be enhanced. Experimental studies presented in this paper exhibit the effectiveness and the adaptability of the approach with different scheduling policies. The studies also show that coalition formation among the RPSs can further improve simulation performance and avoid counter-productive competition.

A VLIW architecture for a trace scheduling compiler

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a VLIW machine was expected to provide from ten to thirty times the performance of a more conventional machine built of the same implementation technology.Multiflow Computer, Inc., has now built a VLIW called the TRACE TM along with its companion Trace Scheduling TM compacting compiler. This new machine has fulfilled the performance promises that were made. Using many fast functional units in parallel, this machine extends some of the basic Reduced-Instruction-Set precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for runtime resource usage).This paper discusses the design of this machine and presents some initial performance results.

A VLIW architecture for a trace scheduling compiler

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a VLIW machine was expected to provide from ten to thirty times the performance of a more conventional machine built of the same implementation technology.Multiflow Computer, Inc., has now built a VLIW called the TRACE TM along with its companion Trace Scheduling TM compacting compiler. This new machine has fulfilled the performance promises that were made. Using many fast functional units in parallel, this machine extends some of the basic Reduced-Instruction-Set precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for runtime resource usage).This paper discusses the design of this machine and presents some initial performance results.

A VLIW architecture for a trace scheduling compiler

Very Long Instruction Word (VLIW) architectures were promised to deliver far more than the factor of two or three that current architectures achieve from overlapped execution. Using a new type of compiler which compacts ordinary sequential code into long instruction words, a VLIW machine was expected to provide from ten to thirty times the performance of a more conventional machine built of the same implementation technology.Multiflow Computer, Inc., has now built a VLIW called the TRACE TM along with its companion Trace Scheduling TM compacting compiler. This new machine has fulfilled the performance promises that were made. Using many fast functional units in parallel, this machine extends some of the basic Reduced-Instruction-Set precepts: the architecture is load/store, the microarchitecture is exposed to the compiler, there is no microcode, and there is almost no hardware devoted to synchronization, arbitration, or interlocking of any kind (the compiler has sole responsibility for runtime resource usage).This paper discusses the design of this machine and presents some initial performance results.