Room Temperature Capacitance-voltage Research Articles

Voltage-Tunable Quantum-Dot Array by Patterned Ge -Nanowire-Based Metal-Oxide-Semiconductor Devices

Semiconductor quantum dots (QDs) are being regarded as the primary unit for a wide range of advanced and emerging technologies including electronics, optoelectronics, photovoltaics and biosensing applications as well as the domain of q-bits based quantum information processing. Such QDs are suitable for several novel device applications for their unique property of confining carriers 3-dimensionally creating discrete quantum states. However, the realization of such QDs in practice exhibits serious challenge regarding their fabrication in array with desired scalability and repeatability as well as control over the quantum states at room temperature. In this context, the current work reports the fabrication of an array of highly scaled Ge-nanowire (radius ~25 nm) based vertical metal-oxide-semiconductor devices that can operate as voltage tunable quantum dots at room temperature. The electrons in such nanowire experience a geometrical confinement in the radial direction, whereas, they can be confined axially by tuning the applied bias in order to manipulate the quantum states. Such quantum confinement of electrons has been confirmed from the step-like responses in the room temperature capacitance-voltage (C-V) characteristics at relatively low frequency (200 kHz). Each of such steps has observed to encompass convolution of the quantized states occupying ~6 electronic charges. The details of such carrier confinement are analyzed in the current work by theoretically modeling the device transport properties based on non-equilibrium Green's function (NEGF) formalism.

Co/aniline blue/silicon sandwich hybrid heterojunction for photodiode and low-temperature applications

The temperature dependence of the current–voltage and room temperature capacitance–voltage measurements of Co/aniline blue/ n-Si sandwich-type rectifying device was investigated.Furthermore, the effects of the illumination on the current–voltage measurements were tested with 100 mW/cm2 light intensity, and it was seen that Co/aniline blue/ n-Si sandwich-type device showed a clear response to illumination, and it may be a candidate for solar cells or photodiode applications. The rectifying device parameters, such as the barrier height (Ф), the ideality factor ( n), the rectification ratio, and the series resistance ( Rs), were obtained as a function of temperature using thermionic emission, Cheung function, and Norde function. The interface state densities versus energy were obtained. The Richardson constant ( A*) obtained from the In( Io/ T2) versus 1000/ T plot was much less than the theoretical value for n-Si. The mean Schottky barrier height[Formula: see text] and the standard deviation ( σo) were calculated using the apparent Schottky barrier height Фap versus 1/2 kT plot. So, it has been found to be 1.08 eV and 0.15 V (260–460 K) and 0.79 eV and 0.10 V (100–260 K), respectively. The results were discussed based on the presence of two Gaussian distributions of Фb potential in the contact area of Co/aniline blue/ n-Si/Al device.

Electrical behavior of CdS/Al Schottky barrier diode at low temperatures

In this study CdS/Al Schottky barrier diode (SBD) was fabricated by depositing Al metal dot of area 0.001256 cm2 on spray deposited CdS thin film. Current-voltage characteristics of CdS/Al SBD were measured at different temperatures ranging 303-193 K and were analysed to understand the effect of temperature on the electrical parameters of the diode. Both forward and reverse current was found to decrease with the decrease of temperature. The series resistance (RS) and ideality factor (n) were found to increase for the decrease of temperature. The barrier height (ϕb), and Richardson constant (A∗∗) are found to be equal to 0.128 eV and 8.94 x 10-5 AK-2cm-2, respectively. Room temperature capacitance-voltage (C-V) measurement was used to find the carrier concentration (NA) and built in voltage (Vbi) of the CdS/Al Schottky barrier diode. Carrier concentration and the built in potential were found to be 1.84 x 1023 m-3 and 0.393 V, respectively. Schottky barrier height (ɸb) was also measured from C-V characteristics at room temperature and is equal to 0.399 eV. The value of barrier height obtained from low temperature I-V measurements was smaller than that obtained from C-V characteristics. This can be due to the existence of an interface layer or due to spatial inhomogeneities at the CdS/Al contact.

Device application of AgGa0.5In0.5Se2 thin films deposited by thermal sequential stacked layer method

An In/n-AgGa0.5In0.5Se2/p-Si/Al heterostructure was produced by thermal sequential stacked layer deposition method and the device characteristics were investigated. The compositional analysis showed that the depositions of the intended stoichiometric composition of AgGa0.5In0.5Se2 structure were obtainable by controlling and providing the necessary deposition conditions during the deposition processes. By means of the room temperature Hall effect and transmission measurements, the carrier concentration and optical band gap values were determined as cm−3 and 1.65 eV, respectively. In addition, temperature-dependent current-voltage (I–V) and the room temperature capacitance-voltage (C–V) measurements of this heterostructure were carried out. The rectification factor was obtained as about 104 at 1.20 V for all sample temperatures. Depending on the change in the temperature, the series and shunt resistances were calculated as 101 and 106 Ω, respectively. The studies on the current transport mechanisms showed that there were two different mechanisms at two different voltage regions: tunneling enhanced recombination mechanism in the voltage range of 0.08 and 0.30 V and the space charge limited current mechanism in the voltage range of 0.30 and 0.60 V. The barrier height, built-in potential and interface states density of the deposited heterostructure were also calculated and discussed.

Analysis of Temperature-Dependent Electrical Characteristics of n-ZnO Nanowires (NWs)/p-Si Heterojunction Diodes

This paper presents the electrical characteristics of n-zinc oxide (ZnO) nanowires (NWs)/p-Si (100) heterojunction diodes fabricated by the oxidation of thermally deposited metallic Zn on Al:ZnO-coated p-Si 〈1 0 0〉 substrates. The electrical parameters of the n-ZnO NWs/p-Si diodes have been estimated by using the room temperature capacitance-voltage (C-V) and temperature-dependent current-voltage (I-V) characteristics of the heterojunction. The carrier concentration of the ZnO NW film and the barrier height of the diode estimated from the C-V characteristics at room temperature are 1.54 × 10 15 cm -3 and 0.75 eV, respectively. The thermionic emission model was used to analyze the temperature-dependent measured I-V characteristics to estimate the parameters of the diode. The estimated values of the barrier height and ideality factor at room temperature were 0.715 eV and 2.13, respectively. The spatial barrier inhomogeneity was included in the aforementioned analysis by assuming a Gaussian distribution for the barrier height at the n-ZnO NWs/p-Si heterojunction. The Richardson constant A* of ZnO was found to be increased from a relatively low value of 9.75 ×10 - 8 A ·cm - 2 ·K - 2 to a more realistic value of 49A ·cm - 2 ·K - 2 after incorporating the barrier inhomogeneity phenomenon in the aforementioned analysis.

Analysis of temperature dependent electrical properties of Au/perylene-diimide/n-Si Schottky diodes

The electrical properties of Au/perylene-diimide/n-Si Schottky diode have been determined by means of current–voltage measurements in the temperature range of 75–300K. These devices showed good rectifying behavior and the temperature dependence of the current–voltage characteristics could be explained by thermionic emission mechanism. The experimental values of barrier height and ideality factor for device have been calculated as 0.168eV and 7.63eV at 75K and 0.690eV and 1.57eV at 300K, respectively. The fabricated Schottky diode shows non-ideal current–voltage behavior and so it is thought that the device have a metal-interface layer-semiconductor configuration. In addition to current–voltage measurements, the room temperature capacitance–voltage characteristics of Au/perylene-diimide/n-Si devices were also investigated. The barrier height value of 1.051eV obtained from the capacitance–voltage measurements was found to be higher than that of 0.690eV obtained from the current–voltage measurements at room temperature. Furthermore, the energy distribution of the interface state density determined from current–voltage characteristics increases exponentially with bias from 8.01×1012eV−1cm−2 at (Ec−0.666)eV to 5.86×1013eV−1cm−2 at (Ec−0.575)eV.

The modification of Schottky barrier height of Au/p-Si Schottky devices by perylene-diimide

Perylene-diimide (PDI) thin film was fabricated by spin coating method on p-Si single-crystal substrate to prepare Au/PDI/p-Si Schottky device. The electrical properties of the Au/PDI/p-Si Schottky device were investigated by current-voltage (I–V) measurements in the temperature range 80–300 K and room temperature capacitance-voltage (C–V) measurement. Results showed a rectification behavior. Junction parameters such as ideality factor (n), barrier height (ϕB0), series resistance (Rs) interface state density (Nss), built-in potential (Vbi), carrier concentration (NA), and the width of the depletion layer (WD) were obtained from the I–V and C–V measurements. The values of ideality factor (n) and barrier height (BH) for the Au/PDI/p-Si structure from the I–V measurements were obtained as 1.77 and 0.584 eV at 300 K, 7.78 and 0.176 eV at 80 K, respectively. It was seen that the BH value of 0.584 eV calculated for the Au/PDI/p-Si structure was significantly larger than the value of 0.34 eV of conventional Au/p-Si Schottky diodes at room temperature. Thus, modification of the interfacial potential barrier for Au/p-Si diodes has been achieved using a thin interlayer of the peryleen-diimide organic semiconductor; this has been ascribed to the fact that the peryleen-diimide interlayer increases the effective barrier height because of the interface dipole induced by passivation of the organic layer. Furthermore, the energy distribution of the interface state density determined from I–V characteristics increases exponentially with bias from 1.11 × 1012 eV−1 cm−2 at (0.556−Ev) eV to 11.01 × 1013 eV−1 cm−2 at (0.449−Ev) eV.

Study of n-ZnO/p-Si (100) thin film heterojunctions by pulsed laser deposition without buffer layer

ZnO/Si heterojunctions were fabricated by growing ZnO thin films on p-type Si (100) substrate by pulsed laser deposition without buffer layers. The crystallinity of the heterojunction was analyzed by high resolution X-ray diffraction and atomic force microscopy. The optical quality of the film was analyzed by room temperature (RT) photoluminescence measurements. The high intense band to band emission confirmed the high quality of the ZnO thin films on Si. The electrical properties of the junction were studied by temperature dependent current–voltage measurements and RT capacitance–voltage (C–V) analysis. The charge carrier concentration and the barrier height (BH) were calculated, to be 5.6×1019cm−3 and 0.6eV respectively from the C–V plot. The BH and ideality factor, calculated using the thermionic emission (TE) model, were found to be highly temperature dependent. We observed a much lower value in Richardson constant, 5.19×10−7A/cm2K2 than the theoretical value (32A/cm2K2) for ZnO. This analysis revealed the existence of a Gaussian distribution (GD) with a standard deviation of σ2=0.035V. By implementing the GD to the TE, the values of BH and Richardson constant were obtained as 1.3eV and 39.97A/cm2K2 respectively from the modified Richardson plot. The obtained Richardson constant value is close to the theoretical value for n-ZnO. These high quality heterojunctions can be used for solar cell applications.

Transport-mechanism analysis of the reverse leakage current in GaInN light-emitting diodes

The reverse leakage current of a GaInN light-emitting diode (LED) is analyzed by temperature dependent current–voltage measurements. At low temperature, the leakage current is attributed to variable-range-hopping conduction. At high temperature, the leakage current is explained by a thermally assisted multi-step tunneling model. The thermal activation energies (95–162 meV), extracted from the Arrhenius plot in the high-temperature range, indicate a thermally activated tunneling process. Additional room temperature capacitance–voltage measurements are performed to obtain information on the depletion width and doping concentration of the LED.

Effect of biasing at elevated temperature on the electronic structure of Pt/HfO 2/Si stacks

The spatial distribution of charges in a Pt/HfO 2/Si stack has been manipulated by applying a cyclic bias voltage ±2.5 V in combination with moderate ( T ∼ 630 K) heating. The modifications were monitored in situ by room temperature capacitance–voltage ( C–V) and current–voltage ( I–V) measurements and analyzed ex situ by hard X-ray photoelectron spectroscopy which additionally provides information on possible chemical changes at the interfaces. The experimental data on the charge/potential distributions resulting from the different steps of bias-temperature stress (BTS) are consistent with the model that additional oxygen vacancies, which are generated in HfO 2 and positively charged by charge transfer across the interface with a high work function metal (Pt), are driven across the HfO 2 layer. These vacancies ultimately control the observed growth/dissolution of SiO x at the bottom interface upon negative/positive BTS, respectively.

Room temperature capacitance-voltage profile and photoluminescence for delta doped InGaAs single quantum well

Room temperature capacitance-voltage (C-V) profile and photoluminescence (PL) studies of δ-doped single InGaAs quantum well samples are reported. The purpose was to obtain the confined carrier occupancy in the conduction band offset and observe any relevant phenomena. The results show that the peak intensity of the C-V profiles was almost linearly proportional to sheet carrier concentration and the full width at half maximum of the C-V profiles became narrower with increasing doping level in the barrier layer. This is interpreted as being due to improved confinement of electrons as a result of band bending induced by the δ-doping layer. This explanation was further supported by PL data that show the transition corresponding to the dominant peak changed with different δ-doping levels and that all of the transitions were redshifted. Finally, theoretical calculations of the band structure based on a four band k⋅p method are presented to explain the observed results.

Fabrication and electrical characterization of p-NiPc/n-Si heterojunction

Nickel–phthalocyanine (NiPc) thin film was prepared by thermal evaporation method on n-Si single-crystal substrate to fabricate p-NiPc/n-Si heterojunction. The electrical transport properties of the p-NiPc/n-Si heterojunctions were investigated by temperature-dependent current–voltage (I–V) measurements and room temperature capacitance–voltage (C–V) measurements. The temperature-dependent I–V characteristics revealed that the forward conduction was determined by thermionic-emission and space-charge-limited current (SCLC) mechanisms at low and high voltage, respectively⋅ On the other hand, the reverse current is limited by the carrier generation process. The 1/C2–V plot indicated the junction was abrupt and the junction built-in potential was 0.61V at room temperature.

InGaAs metal-oxide-semiconductor capacitors with HfO2 gate dielectric grown by atomic-layer deposition

The influence of various process conditions on the structural integrity and electrical properties of Al∕HfO2∕p-In0.13Ga0.87As metal-oxide-semiconductor capacitors was investigated. Room temperature capacitance voltage measurements revealed postdielectric deposition anneal reduced hysteresis by more than 0.5V and sulfur passivation of InGaAs improved the capacitance frequency dispersion properties as well as reduced interface trap density. At V=VFB−1V, the leakage current densities ∼1.3×10−7, 0.4×10−6, and 1.3×10−6A∕cm2 were measured in devices with annealed HfO2 (110 and 32Å) and sulfur-passivated InGaAs (110Å unannealed HfO2), respectively. Transmission electron microscopy revealed sharp epitaxial InGaAs/crystalline HfO2 and GaAs∕InGaAs interfaces.

The origin of the weak ferroelectric-like hysteresis effect in paraelectricBa0.5Sr0.5TiO3 thin films grownepitaxially on LaAlO3

Perovskite Ba0.5Sr0.5TiO3 (BST) thin films, with thickness of about 350 nm, have been epitaxially grown on (001)LaAlO3 substrates by pulsed-laser deposition. The good crystallography and epitaxy characteristicswere confirmed using x-ray diffraction and transmission electron microscopy (TEM). Thedielectric properties of the BST thin films were measured with a planar capacitorconfiguration in the temperature range of 77–300 K. The capacitance–temperaturecharacteristics, measured with no and several different DC biases, reveal thatthe BST films are in the paraelectric state at room temperature, with a verygood dielectric tunability. However, a butterfly-shaped curve, typical for aferroelectric material, was obtained from room temperature capacitance–voltage(C–V) measurements, suggesting a faint ferroelectric-like effect for the BST thin films. Careful dielectricproperty characterizations showed significant temperature and frequency dependence, probablyindicating a behaviour of Maxwell–Wagner-type dielectric relaxation. As a result, the weakC–V hysteresis effect in our paraelectric BST thin films is believed to be ascribable both tooxygen vacancies and to the presence of other space charges, trapped at the grainboundaries and/or at the substrate/dielectric film interface, which give rise tolocal polar regions in the thin-film samples. Furthermore, this explanation issupported by cross-sectional TEM and off-axis electron holographic observations.

Voltage-Tunable Dielectric Properties of Pyrochlore Bi–Zn–Nb–Ti–O Solid-Solution Thin Films

The structural and dielectric properties of Bi2Ti2O7–Zn2Nb2O7 solid-solution thin films were investigated using (Bi2-xZnx)(NbxTi2-x)O7 (BZNT, 0.05≤x≤1.0) pyrochlore thin films prepared on platinized Si substrates by metalorganic decomposition (MOD) process. Thermal analysis and X-ray diffraction (XRD) results confirmed that the crystallization of the BZNT thin films started below 600°C and was completed at approximately 750°C. Broad ranges of single-phase solid-solutions based on cubic (Bi1.5Zn0.5)(Nb0.5Ti1.5)O7 were observed with x values from 0.1 to 0.7. Compared with bulk ceramics, a restriction in the lattice shrinkage of BZNT thin films with x values under 0.5 was apparent, which may have introduced internal stress in the thin films and eventually affected the dielectric properties of BZNT thin films. The BZNT thin films investigated had dielectric constants in the range of 142–242, and the maximum dielectric constant was 242 when x=0.5. Room-temperature capacitance–voltage measurements at 1 MHz demonstrated a tunability of 30%, with a zero-bias tan δ of 0.005.

Fabrication and electrical characterization of nanocrystalline ZnO/Si heterojunctions

Abstract Nanocrystalline zinc oxide (nc-ZnO) films were prepared by a sol–gel process on p-type single-crystalline Si substrates to fabricate nc - ZnO/p-Si heterojunctions. The structure and morphology of ZnO films on Si substrates, which were analyzed by X-ray diffraction (XRD) spectroscopy and atomic force microscopy (AFM), showed that ZnO films consisted of 50–100 nm polycrystalline nanograins with hexagonal wurtzite structure. The electrical transport properties of the nc-ZnO/p-Si heterojunctions were investigated by temperature-dependent current–voltage ( I–V ) measurements and room temperature capacitance–voltage measurements. The temperature-dependent I–V characteristics revealed that the forward conduction was determined by multi-step tunneling current, and the activation energy of saturation current was about 0.26 eV. The 1/ C 2 – V plots indicated the junction was abrupt and the junction built-in potential was 1.49 V at room temperature.

Observation of capacitance?voltage oscillations in porous silicon

This paper presents the experimental observation of room temperature capacitance–voltage oscillations in porous silicon (PS). Analysis of the experimental data suggests density-of-states discontinuities in the PS nanostructures to be the likely origins of the oscillations. From the experimental data, a sub-band energy separation of 0.19 eV is estimated for the dominant silicon nanostructures. This corresponds to a nanostructure dimension of approximately 3 nm , which agrees well with the value expected for the PS fabrication conditions.

Observation of capacitance–voltage oscillations in porous silicon

This paper presents the experimental observation of room temperature capacitance–voltage oscillations in porous silicon (PS). Analysis of the experimental data suggests density-of-states discontinuities in the PS nanostructures to be the likely origins of the oscillations. From the experimental data, a sub-band energy separation of 0.19 eV is estimated for the dominant silicon nanostructures. This corresponds to a nanostructure dimension of approximately 3 nm , which agrees well with the value expected for the PS fabrication conditions.

Electrical properties of metal–oxide–silicon structures with LaAlO3 as gate oxide

In this paper, electrical investigations performed on complex metal–oxide–semiconductor (MOS) structures with amorphous LaAlO3 deposited as gate oxide on a rapid thermal processed SiO2 buffer layer are presented. Current–voltage (I–V) measurements at different temperatures and high frequency room-temperature capacitance–voltage (C–V) measurements indicate the presence of a non-equilibrium state in p-type Si (100) substrate under reverse polarization of the structure. The asymmetry in I–V characteristics is opposite to the expected one for the high-κ/interfacial layer stack behavior. Different indications for the non-equilibrium MOS state are inferred from the experimental data, and the extraction of MOS physical parameters by using the classical C–V method is shown to be unreliable. For small and large applied forward voltages defect-related charge transport and tunneling currents dominate, respectively.

GaAs 기판 위에 EDMIn과 TBP로부터 성장되고 양극산화 처리된 InP Schottky Diode

Au/oxide/n-InP Schottky diodes were fabricated from heteroepitaxial InP layers grown on GaAs substrates by the metalorganic vapor phase epitaxy (MOVPE) method from a new combination of source materials: ethyldimethylindium (EDMIn) and tertiarybutylphosphine (TBP). Anodic oxidation technique by using a solution of 10 g of ammonium pentaborate in 100 cc of ethylene glycole as the electrolyte was used to deposit a thin oxide layer. The barrier heights determined from three different techniques, current-voltage (I-V) measurements at room temperature and in the temperature range of 273 K - 373 K, and room temperature capacitance-voltage (C-V) measurements are in good agreement, 0.7 - 0.9 eV which is considerably high as compared to the 0.45 - 0.55 eV in Au/n-InP Schottky diode without a Passivation layer. The ideality factors of 1.1 - 1.3 of the Schottky diodes were also determined from the I-Y characteristics. Deep level transient spectroscopy (DLTS) studies revealed only one shallow electron state at 92.6 meV below the bottom of the conduction band and no deep state in the heteroepitaxial InP layers grown from EDMIn and TBP.